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EP3888244A1 - Power switch arrangement - Google Patents

Power switch arrangement

Info

Publication number
EP3888244A1
EP3888244A1 EP19809807.1A EP19809807A EP3888244A1 EP 3888244 A1 EP3888244 A1 EP 3888244A1 EP 19809807 A EP19809807 A EP 19809807A EP 3888244 A1 EP3888244 A1 EP 3888244A1
Authority
EP
European Patent Office
Prior art keywords
transistor
low
circuit breaker
side transistor
lss
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19809807.1A
Other languages
German (de)
French (fr)
Inventor
Joachim Joos
Alexander SPAETH
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP3888244A1 publication Critical patent/EP3888244A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H03K17/164—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/001—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection limiting speed of change of electric quantities, e.g. soft switching on or off
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0029—Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H03K17/167—Soft switching using parallel switching arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0072—Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load

Definitions

  • the present invention relates to a circuit breaker arrangement comprising a low-side transistor and a high-side transistor, which are set up in such a way that they are switched on or off in alternating periods of a switching period of the circuit breaker arrangement, with a source connection of the low-side transistor is connected to a load connection and a drain connection of the low-side transistor is connected to a supply voltage via a memory inductor, and a drain connection of the high-side transistor is connected to the load connection and a source connection of the high-side transistor is connected to a supply voltage via a memory inductance.
  • Such a circuit breaker arrangement is also referred to as a synchronous converter and is basically an extension of one in its construction
  • Step-up converter in which the otherwise used diode was replaced by another power transistor. Operation of such
  • Circuit breaker arrangement is generally divided into two periods per switching period.
  • the low-side power transistor is low-resistance and conducts, whereas the high-side power transistor is in a high-resistance state and blocks.
  • the high-side power transistor is in a high-resistance state and blocks.
  • the coil current of the storage inductance remains positive. This means that only energy is transferred from the input side to the output side.
  • a circuit breaker which includes, for example, MOSFET or IGBT, is switched, it does not suddenly change from the non-conductive to the conductive state (or vice versa). Rather, the transistor runs through a certain resistance range depending on the charging voltage of the gate capacitance.
  • EMC electromagnetic compatibility
  • a circuit breaker arrangement of the type mentioned at the outset characterized in that the low-side transistor comprises at least two transistor segments, at least two of the transistor segments having a different electrical resistance in connection with the memory inductance, the circuit breaker arrangement being set up in this way is that at least two of the transistor segments are switched at a different time during a switching operation of the circuit breaker arrangement.
  • the present invention thus makes it possible not to change the steepness of the voltage switching edge in the middle part. Only at the beginning
  • the modulation is achieved with time-delayed or “staggered” switching of different large transistor segments, since this results in different time-dependent path resistances of the low-side power transistor.
  • the surge is reduced / avoided by the sudden
  • Recommutation of the current is prevented by the staggered switching of the “one low-side transistor” that is visible from the outside.
  • At least two of the transistor segments comprise areas of the low-side transistor of different sizes. Except for a little more overhead, the area on the chip of the low-side transistor remains constant despite segmentation. Due to the different area proportions, different path resistance values of the transistor segments result. By switching the individual transistor segments on and off in a short time, the current does not have to commute suddenly. Overvoltage and subsequent settling is prevented, which results in improvements in the spectrum. The steepness of the voltage switching edge (for example the drain voltage of the low-side transistor) is hardly influenced here and the switching losses are thus kept low.
  • the power switch arrangement is set up in such a way that each of the transistor segments is assigned to its own gate segment of the gate connection of the low-side transistor, the associated transistor segment being switched by switching one of the gate segments becomes.
  • the gate connection is then also segmented in accordance with the transistor segments, so that by switching a gate segment
  • the circuit breaker arrangement is set up in such a way that the time interval during a switching process between the switching of two successively switched transistor segments is less than 100 ns, preferably less than 30 ns, preferably less than 5 ns.
  • the circuit breaker arrangement is preferably set up such that the time interval during a switching operation between the switching of two successively switched transistor segments is in each case less than Ts, where Ts is the effective length of the switching process.
  • the time intervals can vary between the individual pairs of successively connected transistor segments.
  • circuit breaker arrangement is set up in such a way that when the low-side transistor is switched, the
  • Memory inductance can be switched sorted. As a result, the switching process can take place sequentially and, despite a steep switching edge in the middle of the switching process (low switching losses), unwanted voltage fluctuations at the end of the switching edge can be reduced (good EMC behavior).
  • the circuit breaker arrangement is set up in such a way that when the low-side transistor is switched on, the transistor segments are switched on in succession from the highest resistance to the lowest resistance.
  • the transistor segment with the highest resistance can then have, for example, the smallest area portion of the low-side transistor, while the transistor segment with the lowest resistance can have the largest area portion of the low-side transistor.
  • the transistor segments are then switched on in succession from the lowest area to the highest area.
  • Circuit breaker arrangement set up in such a way that when the low-side transistor is switched off, the transistor segments are switched off with a time delay from the lowest resistance to the highest resistance.
  • the transistor segment with the lowest resistance can then have, for example, the largest area portion of the low-side transistor, while the transistor segment with the highest resistance can have the smallest area portion of the low-side transistor.
  • FIG. 1 shows a circuit diagram of an embodiment of a circuit breaker arrangement according to the invention
  • FIG. 2 shows a simplified diagram of the drain current and the drain voltage of a circuit breaker in the prior art
  • FIG. 3 shows a simplified diagram of the drain current and the drain voltage of a circuit breaker arrangement according to the invention
  • Figure 4 is a simplified diagram of the drain voltage of a
  • FIG. 5 is a simplified diagram of the drain voltage
  • Circuit breaker arrangement according to the invention.
  • Figure 1 shows a circuit diagram of an embodiment of an inventive
  • Circuit breaker arrangement 1 comprising a low-side transistor LSS and a high-side transistor HSS.
  • the low-side transistor LSS and the high-side transistor HSS are set up in such a way that they alternate in relation to one another
  • a source connection 2 of the low-side transistor LSS is connected to a load connection 3, via which one
  • a drain connection 5 of the low-side transistor LSS is connected to a supply voltage V m via a memory inductance L.
  • a drain terminal 6 of the high-side transistor HSS is connected to the load terminal 3 and a source terminal 7 of the high-side transistor HSS is via the
  • the low-side transistor LSS now comprises at least two (here three) transistor segments LSS1, LSS2, LSS3. At least two of the transistor segments LSS1, LSS2, LSS3 have a different electrical resistance R1, R2, R3 in connection with the memory inductance L.
  • the transistor segments LSS1, LSS2, LSS3 are shown here as parallel-connected power transistors with separate track resistors R1, R2, R3, but they are actually combined in a common low-side transistor LSS.
  • the transistor segments LSS1, LSS2, LSS3 can also be connected in parallel as discrete components.
  • the circuit breaker arrangement 1 is set up such that at least two of the transistor segments LSS1, LSS2, LSS3 are switched at a different time during a switching operation of the circuit breaker arrangement 1.
  • At least two of the transistor segments LSS1, LSS2, LSS3 can be any transistor segment LSS1, LSS2, LSS3.
  • Transistor segments LSS1, LSS2, LSS3 do not have to commute suddenly in a short time. Overvoltage and subsequent settling is prevented, which results in improvements in the spectrum.
  • low-side transistor LSS is not affected.
  • the transistor segments LSS1, LSS2, LSS3 can also be of the same size
  • Resistors for memory inductance L can be interposed. In the circuit in FIG. 1, the resistors R1, R2, R3 are then separate
  • Each of the transistor segments can be assigned to its own gate segment 8 of the gate connection of the low-side transistor LSS, with one
  • Transistor segments LSS1, LSS2, LSS3 is effected.
  • FIGS. 2 and 3 illustrate the background of the invention.
  • the drain current and the drain voltage of a low-side transistor LSS versus time t are each shown in a simplified diagram over two switching operations.
  • FIG. 2 shows the drain current IDS and the drain voltage VDS of a low-side transistor LSS in the prior art.
  • Switching edges 9 of the drain voltage VDS are relatively sharp and lead to overvoltages (see also FIG. 4) if the duration of the switching process is chosen too short. This leaves only the choice to accept longer switching times and larger switching losses in order to achieve sufficient EMC compatibility.
  • FIG. 3 shows the drain current IDS and the drain voltage VDS of a low-side circuit breaker LSS of a circuit breaker arrangement according to the invention.
  • switching edges 10 of the drain voltage VDS are now flatter and no longer lead to overvoltages, even if the duration of the switching process in the middle of the switching process of the low-side transistor LSS is chosen to be quite short.
  • the greater steepness of the switching edge in the middle of the switching process and the shorter switching time lead to lower switching losses with improved EMC emissions.
  • FIGS. 4 and 5 illustrate the main effect of the invention.
  • a somewhat more realistic curve of the drain voltage VDS of a low-side circuit breaker LSS versus time t is shown over two switching operations.
  • Figure 4 shows a low-side circuit breaker LSS of the prior art (corresponding to Figure 2), which has a relatively short switching time, low switching losses and thus a steep switching edge.
  • a low-side circuit breaker LSS also leads to quite pronounced ones
  • Switching vibrations 11 at the end of a switch-off process or one Switch-on process can lead to overvoltages and worsen the EMC compatibility.
  • FIG. 5 shows a low-side circuit breaker LSS according to the invention
  • the low-side transistor LSS now comprises at least two transistor segments LSS1, LSS2, LSS3, which have a different electrical resistance R1, R2, R3 in connection with the memory inductance L, the transistor segments can be staggered LSS1, LSS2, LSS3 significantly reduced switching vibrations 12 can be achieved at the end of a switch-off process or a switch-on process. This reduces overvoltages and improves EMC compatibility without significantly increasing switching losses.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Electronic Switches (AREA)

Abstract

The invention relates to a power switch arrangement (1) comprising a low-side transistor (LSS) and a high-side transistor (HSS), which are designed such that the low-side transistor and the high-side transistor are conductingly switched or blockingly switched, each in alternating time periods of a switching period of the power switch arrangement (1). A source terminal (2) of the low-side transistor (LSS) is connected to a load terminal (3) and a drain terminal (5) of the low-side transistor (LSS) is connected to a supply voltage (Vin) via a storage inductance. A drain terminal (6) of the high-side transistor (HSS) is connected to the load terminal (3) and a source terminal (7) of the high-side transistor (HSS) is connected to the supply voltage (Vin) via the storage inductance. According to the invention, a power switch arrangement (1) of the aforementioned type is provided, characterized in that the low-side transistor (LSS) comprises at least two transistor segments (LSS1, LSS2, LSS3). At least two of the transistor segments have a different electrical resistance (R1, R2, R3) in their connection to the storage inductance. The power switch arrangement (1) is designed such that at least two of the transistor segments (LSS1, LSS2, LSS3) are switched at different times during a switching process of the power switch arrangement (1). This reduces unwanted voltage fluctuations without the switching losses significantly rising.

Description

Beschreibung description

Titel title

Leistunqsschalteranordnunq Circuit breaker arrangement

Die vorliegende Erfindung betrifft eine Leistungsschalteranordnung umfassend einen Low-Side-Transistor und einen High-Side-Transistor, die so eingerichtet sind, dass sie in jeweils zueinander abwechselnden Zeitabschnitten einer Schaltperiode der Leistungsschalteranordnung leitend geschaltet sind oder sperrend geschaltet sind, wobei ein Source-Anschluss des Low-Side-Transistors mit einem Lastanschluss und ein Drain-Anschluss des Low-Side-Transistors über eine Speicherinduktivität mit einer Versorgungsspannung verbunden ist und wobei ein Drain-Anschluss des High-Side-Transistors mit dem Lastanschluss verbunden ist und ein Source-Anschluss des High-Side-Transistors über eine Speicherinduktivität mit einer Versorgungsspannung verbunden ist. The present invention relates to a circuit breaker arrangement comprising a low-side transistor and a high-side transistor, which are set up in such a way that they are switched on or off in alternating periods of a switching period of the circuit breaker arrangement, with a source connection of the low-side transistor is connected to a load connection and a drain connection of the low-side transistor is connected to a supply voltage via a memory inductor, and a drain connection of the high-side transistor is connected to the load connection and a source connection of the high-side transistor is connected to a supply voltage via a memory inductance.

Stand der Technik State of the art

Eine solche Leistungsschalteranordnung wird auch als Synchronwandler bezeichnet und ist prinzipiell in seinem Aufbau eine Erweiterung eines Such a circuit breaker arrangement is also referred to as a synchronous converter and is basically an extension of one in its construction

Aufwärtswandlers, bei dem die sonst verwendete Diode durch einen weiteren Leistungstransistor ersetzt wurde. Der Betrieb einer derartigen Step-up converter, in which the otherwise used diode was replaced by another power transistor. Operation of such

Leistungsschalteranordnung wird generell in zwei Zeitabschnitte je Schaltperiode unterteilt. Während des ersten Zeitabschnitts ist der Low-Side-Leistungstransistor niederohmig und leitet, wohingegen sich der High-Side-Leistungstransistor in einem hochohmigen Zustand befindet und sperrt. Dabei liegt die Circuit breaker arrangement is generally divided into two periods per switching period. During the first time period, the low-side power transistor is low-resistance and conducts, whereas the high-side power transistor is in a high-resistance state and blocks. Here lies the

Eingangsspannung über der Speicherinduktivität an. Infolge dessen steigt der Spulenstrom linear an und führt zu einer Energieaufnahme der Input voltage above the storage inductance. As a result, the coil current increases linearly and leads to an energy consumption of the

Speicherinduktivität. In dem zweiten Zeitabschnitt sperrt der Low-Side- Leistungstransistor und der High-Side-Leistungstransistor leitet. Über der Speicherinduktivität liegt eine Spannung an, die der Differenz der Memory inductance. In the second period, the low-side power transistor blocks and the high-side power transistor conducts. A voltage is present across the memory inductance, which is the difference between the

Ausgangsspannung und der Eingangsspannung entspricht. Dabei sinkt der Spulenstrom in der Speicherinduktivität ab und die Speicherinduktivität gibt Energie an die Ausgangsseite des Synchronwandlers ab. Bei einem Output voltage and the input voltage corresponds. The sinks Coil current in the storage inductance and the storage inductance delivers energy to the output side of the synchronous converter. At a

unidirektionalen Betrieb bleibt der Spulenstrom der Speicherinduktivität positiv. Hierdurch wird nur Energie von der Eingangsseite zur Ausgangsseite übertragen. In unidirectional operation, the coil current of the storage inductance remains positive. This means that only energy is transferred from the input side to the output side.

Wird ein Leistungsschalter, der beispielsweise MOSFET oder IGBT umfasst, umgeschaltet, so geht er nicht schlagartig vom nichtleitenden in den leitenden Zustand (oder umgekehrt) über. Vielmehr durchläuft der Transistor je nach Ladespannung der Gate-Kapazität einen gewissen Widerstandsbereich. If a circuit breaker, which includes, for example, MOSFET or IGBT, is switched, it does not suddenly change from the non-conductive to the conductive state (or vice versa). Rather, the transistor runs through a certain resistance range depending on the charging voltage of the gate capacitance.

Während des Umschaltens unter Stromfluss wird eine mehr oder weniger große Leistung im Transistor umgesetzt, welche ihn erwärmt und im ungünstigsten Fall sogar beschädigen kann. Daher ist es regelmäßig gewünscht, den During the switching under current flow, a more or less large power is implemented in the transistor, which heats it up and, in the worst case, can even damage it. Therefore, it is regularly requested that

Umschaltvorgang des Transistors so kurz wie möglich zu gestalten, um die Schaltverluste so gering wie möglich zu halten. Make the switching process of the transistor as short as possible in order to keep the switching losses as low as possible.

Durch schnelle Schaltvorgänge entstehen aber Überspannungen durch schlagartiges Umkommutieren des Stromes an internen Parasiten der verbundenen Elektronikkomponenten. Insbesondere moderne Bordnetze von Kraftfahrzeugen/Schienenfahrzeugen/Flugzeugen (mit Spannungen von zum Beispiel 24 V/48 V) haben regelmäßig eine geringe Toleranz gegenüber However, rapid switching operations result in overvoltages due to sudden commutation of the current at internal parasites of the connected electronic components. In particular, modern on-board electrical systems of motor vehicles / rail vehicles / aircraft (with voltages of, for example, 24 V / 48 V) regularly have a low tolerance towards one another

Überspannungen (als zum Beispiel 12 V-Bordnetze). Gleichzeitig gewinnt durch fortschreitende Miniaturisierung elektromagnetische Verträglichkeit (EMV) immer mehr an Bedeutung und Bauelemente schädigende Überspannungen sollten soweit möglich vermieden werden. Overvoltages (as, for example, 12 V electrical systems). At the same time, progressive miniaturization is making electromagnetic compatibility (EMC) more and more important and overvoltages damaging components should be avoided as far as possible.

Im Stand der Technik ist es bekannt, zur Verbesserung der EMV-Emissionen (zum Beispiel zur Einhaltung des CISPR 22-Standards) und zur Verringerung der Überspannung einen Gate-Vorwiderstand in eine Treiberschaltung It is known in the prior art to improve a gate circuit in a driver circuit to improve the EMC emissions (for example to comply with the CISPR 22 standard) and to reduce the overvoltage

vorzuschalten, was den Schaltvorgang nachträglich verlangsamt. Hierdurch entstehen aber erhöhte Schaltverluste. Die erzeugte Wärme muss dann durch zusätzliche Kühlung abgeführt werden. Insgesamt verschlechtern sich somit der Wirkungsgrad und die Lebensdauer des Leistungsschalters. Offenbarung der Erfindung upstream, which slows down the switching process. However, this results in increased switching losses. The heat generated must then be removed by additional cooling. Overall, the efficiency and service life of the circuit breaker deteriorate. Disclosure of the invention

Erfindungsgemäß wird eine Leistungsschalteranordnung der eingangs genannten Art bereitgestellt, dadurch gekennzeichnet, dass der Low-Side-Transistor mindestens zwei Transistor-Segmente umfasst, wobei mindestens zwei der Transistor-Segmente in der Verbindung zur Speicherinduktivität einen anderen elektrischen Widerstand aufweisen, wobei die Leistungsschalteranordnung so eingerichtet ist, dass mindestens zwei der Transistor-Segmente während eines Schaltvorgangs der Leistungsschalteranordnung zu einem anderen Zeitpunkt geschaltet werden. According to the invention, a circuit breaker arrangement of the type mentioned at the outset is provided, characterized in that the low-side transistor comprises at least two transistor segments, at least two of the transistor segments having a different electrical resistance in connection with the memory inductance, the circuit breaker arrangement being set up in this way is that at least two of the transistor segments are switched at a different time during a switching operation of the circuit breaker arrangement.

Vorteile der Erfindung Advantages of the invention

Aufgrund der oben beschriebenen Überspannungsgefahr muss eine größere Due to the surge hazard described above, a larger one must be used

Sicherheit beim Design von Leistungsschaltern kalkuliert werden, um den Safety in the design of circuit breakers are calculated around the

Leistungsschalter zu schützen, wodurch Mehrkosten beim Design und der Protect circuit breakers, creating additional design and design costs

Produktion der Leistungsschalter entstehen. Die erfindungsgemäße Lösung Production of circuit breakers arise. The solution according to the invention

erlaubt es, durch die Modulation der Schaltflanken das Spektrum der allows the spectrum of the. by modulating the switching edges

Spannungsschwankungen zu verbessern, ohne dass die Verluste ansteigen. Improve voltage fluctuations without increasing losses.

Somit kann eine höhere Steilheit im Mittelteil der Schaltflanke erreicht werden im Vergleich zur bekannten Gate-Vorwiderstandssteuerung. Gleichzeitig können Thus, a higher slope in the middle part of the switching edge can be achieved compared to the known gate series resistor control. Can at the same time

Spannungsschwingungen an parasitären Induktivitäten reduziert werden, Voltage vibrations at parasitic inductances are reduced,

wodurch die EMV-Verträglichkeit verbessert wird und Überspannungen which improves EMC compatibility and overvoltages

vermieden werden können. can be avoided.

Sowohl der Ausschaltvorgang als auch der Einschaltvorgang lassen sich mit dieser Art der Modulation modulieren. Tests ergeben beispielsweise deutlich gedämpftere Schwingungen in der Phasenspannung und der Both the switch-off process and the switch-on process can be modulated with this type of modulation. Tests, for example, show significantly more damped vibrations in the phase voltage and the

Ausgangsspannung eines angeschlossenen Wandlers (DC-DC/AC-DC/DC- AC/AC-AC). Die größere Steilheit der Schaltflanke in der Mitte des Output voltage of a connected converter (DC-DC / AC-DC / DC-AC / AC-AC). The greater steepness of the switching edge in the middle of the

Schaltvorgangs und die kleinere Schaltzeit führen zu geringeren Schaltverlusten bei trotzdem verbesserter EMV-Emission. Switching process and the shorter switching time lead to lower switching losses with improved EMC emissions.

Die vorliegende Erfindung erlaubt es also, die Steilheit der Spannungs- Schaltflanke im Mittelteil nicht zu verändern. Lediglich am Anfang The present invention thus makes it possible not to change the steepness of the voltage switching edge in the middle part. Only at the beginning

sowie am Ende des Schaltvorgangs wird die Steilheit der Flanke deutlich and at the end of the switching process, the slope of the flank becomes clear

moduliert und somit ungewollte Schwingungen vermieden. Durch das zeitverzögerte beziehungsweise„gestaffelte“ Schalten unterschiedlicher großer Transistor-Segmente wird die Modulation erreicht, da hierbei unterschiedliche zeitabhängige Bahnwiderstände des Low-Side-Leistungstransistors resultieren. Die Überspannung wird verringert/vermieden, indem das schlagartige modulated and thus unwanted vibrations avoided. By the The modulation is achieved with time-delayed or “staggered” switching of different large transistor segments, since this results in different time-dependent path resistances of the low-side power transistor. The surge is reduced / avoided by the sudden

Umkommutieren des Stromes verhindert wird durch das gestaffelte Schalten des von außen sichtbaren„einen Low-Side-Transistors“. Recommutation of the current is prevented by the staggered switching of the “one low-side transistor” that is visible from the outside.

Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben und in der Beschreibung beschrieben. Advantageous developments of the invention are specified in the subclaims and described in the description.

In einer Ausführungsform umfassen mindestens zwei der Transistor-Segmente unterschiedlich große Flächenanteile des Low-Side-Transistors. Bis auf ein wenig mehr Overhead bleibt die Fläche auf dem Chip des Low-Side-Transistors konstant trotz Segmentierung. Durch die unterschiedlich großen Flächenanteile resultieren unterschiedliche Bahnwiderstandswerte der Transistor-Segmente. Durch zeitlich gestaffeltes Einschalten/Ausschalten der einzelnen Transistor- Segmente innerhalb kurzer Zeit muss der Strom nicht schlagartig kommutieren. Überspannung und anschließendes Einschwingen wird verhindert, wodurch sich Verbesserungen im Spektrum ergeben. Die Steilheit der Spannungsschaltflanke (beispielsweise der Drain-Spannung des Low-Side-Transistors) wird hierbei kaum beeinflusst und somit werden die Schaltverluste geringgehalten. In one embodiment, at least two of the transistor segments comprise areas of the low-side transistor of different sizes. Except for a little more overhead, the area on the chip of the low-side transistor remains constant despite segmentation. Due to the different area proportions, different path resistance values of the transistor segments result. By switching the individual transistor segments on and off in a short time, the current does not have to commute suddenly. Overvoltage and subsequent settling is prevented, which results in improvements in the spectrum. The steepness of the voltage switching edge (for example the drain voltage of the low-side transistor) is hardly influenced here and the switching losses are thus kept low.

Es ist bevorzugt, wenn die Leistungsschalteranordnung so eingerichtet ist, dass jedes der Transistor-Segmente einem eigenen Gate-Segment des Gate- Anschlusses des Low-Side-Transistors zugeordnet ist, wobei über ein Schalten eines der Gate-Segmente das zugehörige Transistor-Segment geschaltet wird. Der Gate-Anschluss ist dann entsprechend der Transistor-Segmente ebenfalls segmentiert, sodass durch ein Umschalten eines Gate-Segments das It is preferred if the power switch arrangement is set up in such a way that each of the transistor segments is assigned to its own gate segment of the gate connection of the low-side transistor, the associated transistor segment being switched by switching one of the gate segments becomes. The gate connection is then also segmented in accordance with the transistor segments, so that by switching a gate segment

Umschalten des zugehörigen Transistor-Segments bewirkt wird. Switching the associated transistor segment is effected.

In einer Ausführungsform ist die Leistungsschalteranordnung so eingerichtet, dass der Zeitabstand während eines Schaltvorgangs zwischen dem Schalten zweier nacheinander geschalteter T ransistor-Segmente weniger als 100 ns beträgt, vorzugsweise weniger als 30 ns beträgt, vorzugsweise weniger als 5 ns beträgt. Vorzugsweise ist die Leistungsschalteranordnung so eingerichtet, dass der Zeitabstand während eines Schaltvorgangs zwischen dem Schalten zweier nacheinander geschalteter Transistor-Segmente jeweils weniger als Ts beträgt, wobei Ts die effektive Länge des Schaltvorgangs ist. Die Zeitabstände können dabei zwischen den einzelnen Paaren von nacheinander geschalteten Transistor- Segmenten variieren. In one embodiment, the circuit breaker arrangement is set up in such a way that the time interval during a switching process between the switching of two successively switched transistor segments is less than 100 ns, preferably less than 30 ns, preferably less than 5 ns. The circuit breaker arrangement is preferably set up such that the time interval during a switching operation between the switching of two successively switched transistor segments is in each case less than Ts, where Ts is the effective length of the switching process. The time intervals can vary between the individual pairs of successively connected transistor segments.

In einer weiteren Ausführungsform ist die Leistungsschalteranordnung so eingerichtet, dass bei einem Schaltvorgang des Low-Side-Transistors die In a further embodiment, the circuit breaker arrangement is set up in such a way that when the low-side transistor is switched, the

Transistor-Segmente nach ihrem elektrischen Widerstand zur Transistor segments according to their electrical resistance

Speicherinduktivität sortiert geschaltet werden. Dadurch kann der Schaltvorgang sequentiell erfolgen und trotz einer steilen Schaltflanke in der des Schaltvorgangs Mitte (niedrige Schaltverluste) ungewollte Spannungsschwingungen am Ende der Schaltflanke verringert werden (gutes EMV-Verhalten). Memory inductance can be switched sorted. As a result, the switching process can take place sequentially and, despite a steep switching edge in the middle of the switching process (low switching losses), unwanted voltage fluctuations at the end of the switching edge can be reduced (good EMC behavior).

In einer bevorzugten Ausführungsform ist die Leistungsschalteranordnung so eingerichtet, dass bei einem Einschaltvorgang des Low-Side-Transistors die Transistor-Segmente der Reihe nach vom höchsten Widerstand zum niedrigsten Widerstand zeitversetzt eingeschaltet werden. Das Transistor Segment mit dem höchsten Widerstand kann dann beispielsweise den kleinsten Flächenanteil des Low-Side-Transistors aufweisen während das Transistor Segment mit dem niedrigsten Widerstand den größten Flächenanteil des Low-Side-Transistors aufweisen kann. Bei einem Einschaltvorgang des Low-Side-Transistors werden dann die Transistor-Segmente der Reihe nach vom niedrigsten Flächenanteil zum höchsten Flächenanteil zeitversetzt eingeschaltet. In a preferred embodiment, the circuit breaker arrangement is set up in such a way that when the low-side transistor is switched on, the transistor segments are switched on in succession from the highest resistance to the lowest resistance. The transistor segment with the highest resistance can then have, for example, the smallest area portion of the low-side transistor, while the transistor segment with the lowest resistance can have the largest area portion of the low-side transistor. When the low-side transistor is switched on, the transistor segments are then switched on in succession from the lowest area to the highest area.

In einer weiteren bevorzugten Ausführungsform ist die In a further preferred embodiment, the

Leistungsschalteranordnung so eingerichtet, dass bei einem Abschaltvorgang des Low-Side-Transistors die Transistor-Segmente der Reihe nach vom niedrigsten Widerstand zum höchsten Widerstand zeitversetzt abgeschaltet werden. Das Transistor Segment mit dem niedrigsten Widerstand kann dann beispielsweise den größten Flächenanteil des Low-Side-Transistors aufweisen während das Transistor Segment mit dem höchsten Widerstand den kleinsten Flächenanteil des Low-Side-Transistors aufweisen kann. Bei einem Circuit breaker arrangement set up in such a way that when the low-side transistor is switched off, the transistor segments are switched off with a time delay from the lowest resistance to the highest resistance. The transistor segment with the lowest resistance can then have, for example, the largest area portion of the low-side transistor, while the transistor segment with the highest resistance can have the smallest area portion of the low-side transistor. At a

Ausschaltvorgang des Low-Side-Transistors werden dann die Transistor- Segmente der Reihe nach vom höchsten Flächenanteil zum niedrigsten Switching off the low-side transistor then the transistor segments in turn from the highest area share to the lowest

Flächenanteil zeitversetzt eingeschaltet. Zeichnungen Area share switched on with a time delay. drawings

Ausführungsbeispiele der Erfindung werden anhand der Zeichnungen und der nachfolgenden Beschreibung näher erläutert. Es zeigen: Exemplary embodiments of the invention are explained in more detail with reference to the drawings and the following description. Show it:

Figur 1 ein Schaltdiagramm einer Ausführungsform einer erfindungsgemäßen Leistungsschalteranordnung, FIG. 1 shows a circuit diagram of an embodiment of a circuit breaker arrangement according to the invention,

Figur 2 ein vereinfachtes Schaubild des Drain-Stroms und der Drain-Spannung eines Leistungsschalters im Stand der Technik, FIG. 2 shows a simplified diagram of the drain current and the drain voltage of a circuit breaker in the prior art,

Figur 3 ein vereinfachtes Schaubild des Drain-Stroms und der Drain-Spannung einer erfindungsgemäßen Leistungsschalteranordnung, FIG. 3 shows a simplified diagram of the drain current and the drain voltage of a circuit breaker arrangement according to the invention,

Figur 4 ein vereinfachtes Schaubild der Drain-Spannung eines Figure 4 is a simplified diagram of the drain voltage of a

Leistungsschalters im Stand der Technik, und Circuit breaker in the prior art, and

Figur 5 ein vereinfachtes Schaubild der Drain-Spannung einer Figure 5 is a simplified diagram of the drain voltage

erfindungsgemäßen Leistungsschalteranordnung. Circuit breaker arrangement according to the invention.

Ausführungsformen der Erfindung Embodiments of the invention

Figur 1 zeigt ein Schaltbild einer Ausführungsform einer erfindungsgemäßen Figure 1 shows a circuit diagram of an embodiment of an inventive

Leistungsschalteranordnung 1 umfassend einen Low-Side-Transistor LSS und einen High-Side-Transistor HSS. Der Low-Side-Transistor LSS und der High-Side-Transistor HSS sind so eingerichtet, das sie in jeweils relativ zueinander abwechselnden Circuit breaker arrangement 1 comprising a low-side transistor LSS and a high-side transistor HSS. The low-side transistor LSS and the high-side transistor HSS are set up in such a way that they alternate in relation to one another

Zeitabschnitten einer Schaltperiode der Leistungsschalteranordnung 1 leitend geschaltet sind oder sperrend geschaltet sind. Ein Source-Anschluss 2 des Low-Side- Transistors LSS ist mit einem Lastanschluss 3 verbunden, über den eine Periods of a switching period of the circuit breaker arrangement 1 are switched on or are switched off. A source connection 2 of the low-side transistor LSS is connected to a load connection 3, via which one

angeschlossene Last 4 mit einer Ausgangsspannung Vout gespeist wird. Ein Drain- Anschluss 5 des Low-Side-Transistors LSS ist über eine Speicherinduktivität L mit einer Versorgungsspannung Vm verbunden. connected load 4 is fed with an output voltage V out . A drain connection 5 of the low-side transistor LSS is connected to a supply voltage V m via a memory inductance L.

Ein Drain-Anschluss 6 des High-Side-Transistors HSS ist mit dem Lastanschluss 3 und ein Source-Anschluss 7 des High-Side-Transistors HSS ist über die A drain terminal 6 of the high-side transistor HSS is connected to the load terminal 3 and a source terminal 7 of the high-side transistor HSS is via the

Speicherinduktivität L mit der Versorgungsspannung V,n verbunden. Erfindungsgemäß umfasst der Low-Side-Transistor LSS nun mindestens zwei (hier drei) Transistor-Segmente LSS1 , LSS2, LSS3. Mindestens zwei der Transistor- Segmente LSS1 , LSS2, LSS3 weisen in der Verbindung zur Speicherinduktivität L einen anderen elektrischen Widerstand R1 , R2, R3 auf. Die Transistor-Segmente LSS1 , LSS2, LSS3 sind hier als parallelgeschaltete Leistungstransistoren mit separaten Bahnwiderständen R1 , R2, R3 dargestellt, sie sind aber tatsächlich in einem gemeinsamen Low-Side-Transistor LSS kombiniert. Alternativ können die Transistor- Segmente LSS1 , LSS2, LSS3 aber auch als diskrete Bauelemente parallelgeschaltet werden. Die Leistungsschalteranordnung 1 ist so eingerichtet, dass mindestens zwei der Transistor-Segmente LSS1 , LSS2, LSS3 während eines Schaltvorgangs der Leistungsschalteranordnung 1 zu einem anderen Zeitpunkt geschaltet werden. Memory inductance L connected to the supply voltage V, n . According to the invention, the low-side transistor LSS now comprises at least two (here three) transistor segments LSS1, LSS2, LSS3. At least two of the transistor segments LSS1, LSS2, LSS3 have a different electrical resistance R1, R2, R3 in connection with the memory inductance L. The transistor segments LSS1, LSS2, LSS3 are shown here as parallel-connected power transistors with separate track resistors R1, R2, R3, but they are actually combined in a common low-side transistor LSS. Alternatively, the transistor segments LSS1, LSS2, LSS3 can also be connected in parallel as discrete components. The circuit breaker arrangement 1 is set up such that at least two of the transistor segments LSS1, LSS2, LSS3 are switched at a different time during a switching operation of the circuit breaker arrangement 1.

Mindestens zwei der Transistor-Segmente LSS1 , LSS2, LSS3 können At least two of the transistor segments LSS1, LSS2, LSS3 can

unterschiedlich große Flächenanteile des Low-Side-Transistors LSS umfassen. include different sized areas of the low-side transistor LSS.

Bis auf ein wenig mehr Overhead bleibt die Fläche auf dem Chip des Low-Side- Transistors LSS gegenüber einem nicht-segmentierten Low-Side-Transistor konstant. Durch die unterschiedlich großen Flächenanteile resultieren Except for a little more overhead, the area on the chip of the low-side transistor LSS remains constant compared to a non-segmented low-side transistor. The result of the differently sized areas

unterschiedliche Bahnwiderstandswerte R1 , R2, R3 der Transistor-Segmente different path resistance values R1, R2, R3 of the transistor segments

LSS1 , LSS2, LSS3. Durch zeitlich gestaffeltes Einschalten der einzelnen LSS1, LSS2, LSS3. By staggered switching on of the individual

Transistor-Segmente LSS1 , LSS2, LSS3 innerhalb kurzer Zeit muss der Strom nicht schlagartig kommutieren. Überspannung und anschließendes Einschwingen wird verhindert, wodurch sich Verbesserungen im Spektrum ergeben. Die Transistor segments LSS1, LSS2, LSS3 do not have to commute suddenly in a short time. Overvoltage and subsequent settling is prevented, which results in improvements in the spectrum. The

Steilheit der Spannungsschaltflanke (beispielsweise der Drain-Spannung des Slope of the voltage switching edge (for example the drain voltage of the

Low-Side-Transistors LSS) wird hierbei im Idealfall nicht beeinflusst. Alternativ können die Transistor-Segmente LSS1 , LSS2, LSS3 aber auch gleich große Ideally, low-side transistor LSS) is not affected. Alternatively, the transistor segments LSS1, LSS2, LSS3 can also be of the same size

Flächenanteile umfassen, wobei stattdessen unterschiedlich dimensionierte Include areas, but instead differently dimensioned

Widerstände zur Speicherinduktivität L zwischengeschaltet werden können. In der Schaltung in Figur 1 sind die Widerstände R1 , R2, R3 dann als separate Resistors for memory inductance L can be interposed. In the circuit in FIG. 1, the resistors R1, R2, R3 are then separate

Schaltungselemente zu verstehen und nicht wie bevorzugt als Repräsentation der verschiedenen Bahnwiderstände der Transistor-Segmente LSS1 , LSS2, Understand circuit elements and not, as preferred, as a representation of the different rail resistances of the transistor segments LSS1, LSS2,

LSS3. LSS3.

Jedes der Transistor-Segmente kann einem eigenen Gate-Segment 8 des Gate- Anschlusses des Low-Side-Transistors LSS zugeordnet sein, wobei über ein Each of the transistor segments can be assigned to its own gate segment 8 of the gate connection of the low-side transistor LSS, with one

Schalten eines der Gate-Segmente 8 das zugehörige Transistor-Segment LSS1 , LSS2, LSS3 geschaltet wird. Der Gate-Anschluss ist dann entsprechend der Transistor-Segmente LSS1 , LSS2, LSS3 ebenfalls segmentiert, sodass durch ein Umschalten eines Gate-Segments 8 das Umschalten des zugehörigen Switching one of the gate segments 8 to the associated transistor segment LSS1, LSS2, LSS3 is switched. The gate connection is then also segmented in accordance with the transistor segments LSS1, LSS2, LSS3, so that by switching a gate segment 8 the associated one is switched

Transistor-Segments LSS1 , LSS2, LSS3 bewirkt wird. Transistor segments LSS1, LSS2, LSS3 is effected.

Die Figuren 2 und 3 verdeutlichen den Hintergrund der Erfindung. Es sind jeweils in einem vereinfachten Schaubild der Drain-Strom und die Drain-Spannung eines Low-Side-Transistors LSS gegen die Zeit t über zwei Schaltvorgänge dargestellt. Figures 2 and 3 illustrate the background of the invention. The drain current and the drain voltage of a low-side transistor LSS versus time t are each shown in a simplified diagram over two switching operations.

Figur 2 zeigt den Drain-Strom IDS und die Drain-Spannung VDS eines Low-Side- Transistors LSS im Stand der Technik. Schaltflanken 9 der Drainspannung VDS sind dabei verhältnismäßig scharf und führen zu Überspannungen (siehe auch Figur 4), wenn die Dauer des Schaltvorgangs zu kurz gewählt wird. Somit bleibt nur die Wahl, längere Schaltzeiten und größere Schaltverluste in Kauf zu nehmen, um eine ausreichende EMV-Verträglichkeit zu erreichen. FIG. 2 shows the drain current IDS and the drain voltage VDS of a low-side transistor LSS in the prior art. Switching edges 9 of the drain voltage VDS are relatively sharp and lead to overvoltages (see also FIG. 4) if the duration of the switching process is chosen too short. This leaves only the choice to accept longer switching times and larger switching losses in order to achieve sufficient EMC compatibility.

Figur 3 zeigt den Drain-Strom IDS und die Drain-Spannung VDS eines Low-Side Leistungsschalters LSS einer erfindungsgemäßen Leistungsschalteranordnung. Hier sind nun Schaltflanken 10 der Drain-Spannung VDS flacher und führen nicht mehr zu Überspannungen, selbst wenn die Dauer des Schaltvorgangs in der Mitte des Schaltvorgangs des Low-Side-Transistors LSS recht kurz gewählt wird. Die größere Steilheit der Schaltflanke in der Mitte des Schaltvorgangs und die kleinere Schaltzeit führen zu geringeren Schaltverlusten bei verbesserter EMV- Emission. FIG. 3 shows the drain current IDS and the drain voltage VDS of a low-side circuit breaker LSS of a circuit breaker arrangement according to the invention. Here, switching edges 10 of the drain voltage VDS are now flatter and no longer lead to overvoltages, even if the duration of the switching process in the middle of the switching process of the low-side transistor LSS is chosen to be quite short. The greater steepness of the switching edge in the middle of the switching process and the shorter switching time lead to lower switching losses with improved EMC emissions.

Die Figuren 4 und 5 verdeutlichen den Haupteffekt der Erfindung. Es ist im Vergleich zu den Figuren 2 und 3 jeweils ein etwas realistischerer Verlauf der Drain-Spannung VDS eines Low-Side-Leistungsschalters LSS gegen die Zeit t über zwei Schaltvorgänge dargestellt. Figures 4 and 5 illustrate the main effect of the invention. In comparison to FIGS. 2 and 3, a somewhat more realistic curve of the drain voltage VDS of a low-side circuit breaker LSS versus time t is shown over two switching operations.

Figur 4 zeigt dabei einen Low-Side-Leistungsschalter LSS des Standes der Technik (entsprechend Figur 2), der eine relativ kurze Schaltzeit, niedrige Schaltverluste und damit eine steile Schaltflanke aufweist. Leider führt ein derartiger Low-Side-Leistungsschalter LSS auch zu recht ausgeprägten Figure 4 shows a low-side circuit breaker LSS of the prior art (corresponding to Figure 2), which has a relatively short switching time, low switching losses and thus a steep switching edge. Unfortunately, such a low-side circuit breaker LSS also leads to quite pronounced ones

Schaltschwingungen 11 am Ende eines Ausschaltvorgangs oder eines Einschaltvorgangs. Diese können zu Überspannungen führen und verschlechtern die EMV-Verträglichkeit. Switching vibrations 11 at the end of a switch-off process or one Switch-on process. These can lead to overvoltages and worsen the EMC compatibility.

Figur 5 zeigt einen erfindungsgemäßen Low-Side-Leistungsschalter LSS FIG. 5 shows a low-side circuit breaker LSS according to the invention

(entsprechend Figur 3), der ebenfalls eine relativ kurze Schaltzeit, niedrige (corresponding to Figure 3), which also has a relatively short switching time, low

Schaltverluste und damit eine steile Schaltflanke aufweist. Dadurch, dass der Low- Side-Transistor LSS nun mindestens zwei Transistor-Segmente LSS1 , LSS2, LSS3 umfasst, die in der Verbindung zur Speicherinduktivität L einen anderen elektrischen Widerstand R1 , R2, R3 aufweisen, können durch eine gestaffelte Schaltung der Transistor-Segmente LSS1 , LSS2, LSS3 deutlich reduzierte Schaltschwingungen 12 am Ende eines Ausschaltvorgangs oder eines Einschaltvorgangs erreicht werden. Damit werden Überspannungen reduziert und die EMV-Verträglichkeit verbessert, ohne die Schaltverluste deutlich zu erhöhen. Switching losses and thus has a steep switching edge. Due to the fact that the low-side transistor LSS now comprises at least two transistor segments LSS1, LSS2, LSS3, which have a different electrical resistance R1, R2, R3 in connection with the memory inductance L, the transistor segments can be staggered LSS1, LSS2, LSS3 significantly reduced switching vibrations 12 can be achieved at the end of a switch-off process or a switch-on process. This reduces overvoltages and improves EMC compatibility without significantly increasing switching losses.

Claims

Ansprüche Expectations 1. Leistungsschalteranordnung (1 ) umfassend einen Low-Side-Transistor (LSS) und einen High-Side-Transistor (HSS), die so eingerichtet sind, dass sie in jeweils zueinander abwechselnden Zeitabschnitten einer Schaltperiode der Leistungsschalteranordnung (1 ) leitend geschaltet sind oder sperrend geschaltet sind, 1. Circuit breaker arrangement (1) comprising a low-side transistor (LSS) and a high-side transistor (HSS), which are set up in such a way that they are switched on in alternating periods of a switching period of the circuit breaker arrangement (1) or are blocked, wobei ein Source-Anschluss (2) des Low-Side-Transistors (LSS) mit einem Lastanschluss (3) verbunden ist und ein Drain-Anschluss (5) des Low-Side- Transistors (LSS) über eine Speicherinduktivität (L) mit einer wherein a source connection (2) of the low-side transistor (LSS) is connected to a load connection (3) and a drain connection (5) of the low-side transistor (LSS) via a memory inductance (L) to a Versorgungsspannung (Vn) verbunden ist und Supply voltage (V n ) is connected and wobei ein Drain-Anschluss (6) des High-Side-Transistors (HSS) mit dem Lastanschluss (3) verbunden ist und ein Source-Anschluss (7) des High- Side-Transistors (HSS) über die Speicherinduktivität (L) mit der wherein a drain connection (6) of the high-side transistor (HSS) is connected to the load connection (3) and a source connection (7) of the high-side transistor (HSS) via the memory inductance (L) to the Versorgungsspannung (Vn) verbunden ist, Supply voltage (V n ) is connected, dadurch gekennzeichnet, characterized, dass der Low-Side-Transistor (LSS) mindestens zwei Transistor-Segmente (LSS1 , LSS2, LSS3) umfasst, wobei mindestens zwei der Transistor- Segmente in der Verbindung zur Speicherinduktivität einen anderen elektrischen Widerstand (R1 , R2, R3) aufweisen, that the low-side transistor (LSS) comprises at least two transistor segments (LSS1, LSS2, LSS3), at least two of the transistor segments having a different electrical resistance (R1, R2, R3) in connection with the memory inductance, wobei die Leistungsschalteranordnung (1 ) so eingerichtet ist, dass mindestens zwei der Transistor-Segmente (LSS1 , LSS2, LSS3) während eines Schaltvorgangs der Leistungsschalteranordnung (1 ) zu einem anderen Zeitpunkt geschaltet werden. the circuit breaker arrangement (1) being set up in such a way that at least two of the transistor segments (LSS1, LSS2, LSS3) are switched at a different time during a switching operation of the circuit breaker arrangement (1). 2. Leistungsschalteranordnung (1 ) nach Anspruch 1 , wobei mindestens zwei der Transistor-Segmente (LSS1 , LSS2, LSS3) unterschiedlich große 2. Circuit breaker arrangement (1) according to claim 1, wherein at least two of the transistor segments (LSS1, LSS2, LSS3) of different sizes Flächenanteile des Low-Side-Transistors (LSS) umfassen. Include area portions of the low-side transistor (LSS). 3. Leistungsschalteranordnung (1 ) nach Anspruch 1 oder 2, wobei die 3. Circuit breaker arrangement (1) according to claim 1 or 2, wherein the Leistungsschalteranordnung (1 ) so eingerichtet ist, dass jedes der Transistor-Segmente (LSS1 , LSS2, LSS3) einem eigenen Gate-Segment (8) des Gate-Anschlusses des Low-Side-Transistors (LSS) zugeordnet ist, wobei über ein Schalten eines der Gate-Segmente (8) das zugehörige Transistor-Segment (LSS1 , LSS2, LSS3) geschaltet wird. Circuit breaker arrangement (1) is set up so that each of the Transistor segments (LSS1, LSS2, LSS3) are assigned to a separate gate segment (8) of the gate connection of the low-side transistor (LSS), with the associated transistor segment being switched by switching one of the gate segments Segment (LSS1, LSS2, LSS3) is switched. 4. Leistungsschalteranordnung (1 ) nach einem der vorstehenden Ansprüche, wobei die Leistungsschalteranordnung (1 ) so eingerichtet ist, dass der Zeitabstand während eines Schaltvorgangs zwischen dem Schalten zweier nacheinander geschalteter Transistor-Segmente (LSS1 , LSS2, LSS3) weniger als 100 ns beträgt, vorzugsweise weniger als 30 ns beträgt, vorzugsweise weniger als 5 ns beträgt. 4. Circuit breaker arrangement (1) according to one of the preceding claims, wherein the circuit breaker arrangement (1) is set up in such a way that the time interval during a switching process between the switching of two successively switched transistor segments (LSS1, LSS2, LSS3) is less than 100 ns, is preferably less than 30 ns, preferably less than 5 ns. 5. Leistungsschalteranordnung (1 ) nach einem der vorstehenden Ansprüche, wobei die Leistungsschalteranordnung (1 ) so eingerichtet ist, dass bei einem Schaltvorgang des Low-Side-Transistors (LSS) die Transistor-Segmente (LSS1 , LSS2, LSS3) nach ihrem elektrischen Widerstand (R1 , R2, R3) zur Speicherinduktivität sortiert geschaltet werden. 5. Circuit breaker arrangement (1) according to one of the preceding claims, wherein the circuit breaker arrangement (1) is set up in such a way that, when the low-side transistor (LSS) is switched, the transistor segments (LSS1, LSS2, LSS3) according to their electrical resistance (R1, R2, R3) can be switched sorted to memory inductance. 6. Leistungsschalteranordnung (1 ) nach Anspruch 5, wobei die 6. Circuit breaker arrangement (1) according to claim 5, wherein the Leistungsschalteranordnung (1 ) so eingerichtet ist, dass bei einem Circuit breaker arrangement (1) is set up so that one Einschaltvorgang des Low-Side-Transistors (LSS) die Transistor-Segmente (LSS1 , LSS2, LSS3) der Reihe nach vom höchsten Widerstand (R1 , R2, R3) zum niedrigsten Widerstand (R1 , R2, R3) zeitversetzt eingeschaltet werden. When the low-side transistor (LSS) is switched on, the transistor segments (LSS1, LSS2, LSS3) are switched on in succession from the highest resistance (R1, R2, R3) to the lowest resistance (R1, R2, R3). 7. Leistungsschalteranordnung (1 ) nach Anspruch 5 oder 6, wobei die 7. Circuit breaker arrangement (1) according to claim 5 or 6, wherein the Leistungsschalteranordnung (1 ) so eingerichtet ist, dass bei einem Circuit breaker arrangement (1) is set up so that one Abschaltvorgang des Low-Side-Transistors (LSS) die Transistor-Segmente (LSS1 , LSS2, LSS3) der Reihe nach vom niedrigsten Widerstand (R1 , R2, R3) zum höchsten Widerstand (R1 , R2, R3) zeitversetzt abgeschaltet werden. Switching off the low-side transistor (LSS), the transistor segments (LSS1, LSS2, LSS3) are switched off in sequence from the lowest resistor (R1, R2, R3) to the highest resistor (R1, R2, R3).
EP19809807.1A 2018-11-26 2019-11-26 Power switch arrangement Pending EP3888244A1 (en)

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DE102018220247.8A DE102018220247A1 (en) 2018-11-26 2018-11-26 Circuit breaker arrangement
PCT/EP2019/082543 WO2020109291A1 (en) 2018-11-26 2019-11-26 Power switch arrangement

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EP3888244A1 true EP3888244A1 (en) 2021-10-06

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US20200169252A1 (en) 2020-05-28
WO2020109291A1 (en) 2020-06-04

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