[go: up one dir, main page]

EP3413342A1 - Electronic assembly and method for producing an electronic assembly - Google Patents

Electronic assembly and method for producing an electronic assembly Download PDF

Info

Publication number
EP3413342A1
EP3413342A1 EP17174971.6A EP17174971A EP3413342A1 EP 3413342 A1 EP3413342 A1 EP 3413342A1 EP 17174971 A EP17174971 A EP 17174971A EP 3413342 A1 EP3413342 A1 EP 3413342A1
Authority
EP
European Patent Office
Prior art keywords
substrate surface
circuit substrate
electronic assembly
components
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP17174971.6A
Other languages
German (de)
French (fr)
Inventor
Marc Hauer
Eckardt Bihler
Jochen Held
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dyconex AG
Original Assignee
Dyconex AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dyconex AG filed Critical Dyconex AG
Priority to EP17174971.6A priority Critical patent/EP3413342A1/en
Priority to EP18174093.7A priority patent/EP3413343A3/en
Priority to US15/993,935 priority patent/US10932386B2/en
Publication of EP3413342A1 publication Critical patent/EP3413342A1/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/375—Constructional arrangements, e.g. casings
    • A61N1/3752—Details of casing-lead connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00—Casings, cabinets or drawers for electric apparatus
    • H05K5/06—Hermetically-sealed casings
    • H05K5/065—Hermetically-sealed casings sealed by encapsulation, e.g. waterproof resin forming an integral casing, injection moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/285—Permanent coating compositions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/375—Constructional arrangements, e.g. casings
    • A61N1/3752—Details of casing-lead connections
    • A61N1/3754—Feedthroughs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81897—Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H01L2224/81898—Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8212—Aligning
    • H01L2224/82136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/82138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/822—Applying energy for connecting
    • H01L2224/82201—Compression bonding
    • H01L2224/82203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8236—Bonding interfaces of the semiconductor or solid state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/828—Bonding techniques
    • H01L2224/82895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0141—Liquid crystal polymer [LCP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1327—Moulding over PCB locally or completely
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration

Definitions

  • the invention relates to an electronic assembly on a flexible planar circuit substrate having a conductor configuration on a first substrate surface and a plurality of electronic components on the opposite second substrate surface, wherein the components comprise component contacts which are selectively electrically connected via vias in the circuit substrate and the conductor configuration. It further relates to a method for producing such an assembly.
  • thermoplastic polymers have advantageous properties, in particular with regard to low diffusion rates of oxygen, water and ions; However, such polymers are not very stable in thermal lamination in the xy plane. Therefore, those skilled in the art usually do not consider such circuit substrate materials in view of the high stability requirements of the substrate in positioning many microelectronic circuits or other electronic devices on a single substrate.
  • the object of the invention is to provide an improved electronic assembly, which can be manufactured in particular with a high position accuracy of the components used and is optimized for use in implantable devices and in equipment suitable for aggressive environments, and to provide a method for their production.
  • thermoplastic polymers are unsuitable as a substrate material of the circuit substrate of electronic assemblies for mechanical reasons, and further includes structural as well as technological aspects with which an electronic package using such a circuit substrate may be incorporated Fulfillment of all requirements can be realized.
  • a conductor configuration may also be disposed on the second substrate surface, and this may also be configured in the manner just mentioned.
  • at least on the second surface of the circuit substrate arranged components can also be placed on the first substrate surface components.
  • a multilayer design of the assembly with a plurality of circuit substrates and associated first and second surfaces and correspondingly positioned conductor configurations and component groups is to be understood as being within the scope of the invention.
  • the vias comprise metallizations implemented in openings of the circuit substrate.
  • the breakthroughs are hereinafter referred to as "holes", even if they are not produced by means of a drilling tool, and although they are not necessarily designed circular cylindrical.
  • a prefabricated pattern of openings or "holes” can be provided in embodiments of the invention, according to the assembly plan of the circuit substrate, only a predetermined subset with a metallization.
  • Such embodiments can be realized with a selective metallization technique (such as by means of a metallization mask).
  • all the holes of the hole pattern can be provided with an inner wall metallization, which simplifies the associated metallization process and makes less prone to error.
  • the conductor configuration is formed of a first metallization layer and the plated-through holes are formed of a second metallization layer.
  • the plated-through holes have a metallization deposited in bores of the circuit substrate. If necessary, in this case the deposited metallization is galvanically reinforced. In further embodiments of these embodiments, the plated-through holes have at least one metal from the group copper, gold, titanium, tungsten, palladium, chromium, nickel.
  • the electronic assembly is provided with at least one of the components encapsulating thermoplastic protective film at least on the second substrate surface.
  • This may consist of the same material as the circuit substrate, but depending on the application situation, it is also possible to use another thermoplastic material.
  • the or a thermoplastic material comprises at least one material from the group of liquid-crystalline polymer, LCP; Polyether ketone, PEEK; fluorinated polymers, or polyurethanes.
  • the circuit substrate has a thickness in the range between 10 .mu.m and 500 .mu.m, in particular between 10 .mu.m and 100 .mu.m. Depending on the size and complexity of the electronic assembly and the application situation, however, thinner or thicker substrates may also be considered.
  • the electronic assembly is designed as an implantable electromedical implant or assembly of such.
  • it can also be a device or an assembly of a device which is to be used under "harsh” environmental conditions, in particular in chemically aggressive environments.
  • heating of the circuit substrate as such or a combination of heating both the components and the circuit substrate with suitable means is basically possible instead of heating the components.
  • the components are heated to a setting temperature in the range between 100 ° C and 400 ° C, in particular between 250 ° C and 350 ° C, and / or the contact pressure is in the range between 0.05N and 50N, in particular between 0.1N and 30N.
  • the metal deposition into the bore pattern after the melting or thermal pressing of the components in particular by means of an electrochemical or physical thin-film process, CVD or PVD executed.
  • CVD chemical vapor deposition
  • PVD physical thin-film process
  • a galvanic reinforcement of the deposited thin film is carried out after the metal deposition.
  • the need to carry out such another (and not uncritical in terms of environmental and occupational safety aspects of the process) process step is a decision to make because of the required conductivity and ruggedness of the conductor configuration or vias.
  • thermoplastic protective film is laminated on at least areas of the second substrate surface.
  • This lamination can be performed in the same step as the mounting of the circuit substrate with the components, so to speak, in that the components are pressed into the circuit substrate during lamination of the protective film. In principle, however, a separation of both steps is possible.
  • the first substrate surface ie the one with the conductor configuration, can also be covered with a protective film so that, in particular, a double-sided seal for optimal protection of the electronic assembly against environmental influences is realized.
  • Fig. 1 1 schematically shows a circuit substrate 3 of an (unfinished) electronic package 1, which consists of an LCP (liquid crystal polymer) film 3a with a single-sided conductor configuration 3b, together with a microchip 5 carrying component contacts 5a on a main surface.
  • the microchip 5 is placed on the surface of the flexible planar circuit substrate 3 opposite to the conductor configuration 3b in such a way that the component contacts 5a are aligned with a pattern of holes 3c in the circuit substrate 3.
  • the alignment between the hole pattern in the circuit substrate 3 and the microchip 5 is carried out by an optical alignment method which is indicated by an arrow with the reference O.A. is symbolized. Industry-typical mounting systems such as image acquisition can be used for this step.
  • the holes 3c in the circuit substrate (the LCP film) are optically picked up and the components are positioned on the circuit substrate with a small positional tolerance (about 5-25 ⁇ m).
  • the microchip 5 is set at a temperature near the Tg of the LCP film 3a, e.g. a value in the range between 250 ° C and 350 ° C, heated and pressed with a predetermined force, for example in the range between 0.1N and 30N, in the adjacent surface of the LCP film. This is locally heated and thus softened, so that the component contacts 5a press into the adjacent environment of the holes 3c and the component adheres gap-free flush to the adjacent surface of the circuit substrate 3.
  • a temperature near the Tg of the LCP film 3a e.g. a value in the range between 250 ° C and 350 ° C
  • a predetermined force for example in the range between 0.1N and 30N
  • Fig. 2 shows the completion state of the assembly 1, in which the mentioned adhesion of the microchip 5 on the circuit substrate given in the surface penetrated component contacts 5a and can be seen in the figure. Furthermore, in this state, a metallization with the surface of the circuit substrate 3 opposite the microchip 5 is selectively effected in those bores 3c in which component contacts 5a are seated. As a result, plated-through holes 7 are formed, which extend as inner-wall metallization of the corresponding bores 3c from the component contacts 5 to the conductor configuration 3b and thus electrically connect the component contacts to the conductor configuration.
  • This inner wall metallization may be produced by a thin-film electrochemical or physical process, or a combination of such techniques.
  • the protective films 9.1, 9.2 are made of a thermoplastic material, for example a LCP film similar to the LCP film 3a. This encapsulates the electronic module 1 largely diffusion-tight with respect to the environment and thus enables use in medical implants or devices for use in harsh environments.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Biomedical Technology (AREA)
  • Radiology & Medical Imaging (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Animal Behavior & Ethology (AREA)
  • General Health & Medical Sciences (AREA)
  • Public Health (AREA)
  • Veterinary Medicine (AREA)
  • Nuclear Medicine, Radiotherapy & Molecular Imaging (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

Elektronische Baugruppe auf einem flexiblen flächigen Schaltungssubstrat mit einer Leiterkonfiguration auf einer ersten Substratoberfläche und mehreren elektronischen Bauelementen auf der gegenüberliegenden zweiten Substratoberfläche, wobei die Bauelemente Bauelementkontakte aufweisen, die über Durchkontaktierungen in dem Schaltungssubstrat und die Leiterkonfiguration selektiv elektrisch angeschlossen sind, wobei das Schaltungssubstrat ein thermoplastisches Polymer aufweist und die Bauelementkontakte im Bereich der Durchkontaktierungen in die zweite Substratoberfläche eingeschmolzen bzw. thermisch eingepresst sind.

Figure imgaf001
An electronic assembly on a flexible planar circuit substrate having a conductor configuration on a first substrate surface and a plurality of electronic components on the opposing second substrate surface, the devices having device contacts selectively connected via vias in the circuit substrate and the conductor configuration, the circuit substrate being a thermoplastic polymer and the component contacts are fused or thermally pressed in the region of the plated-through holes into the second substrate surface.
Figure imgaf001

Description

Die Erfindung betrifft eine elektronische Baugruppe auf einem flexiblen flächigen Schaltungssubstrat mit einer Leiterkonfiguration auf einer ersten Substratoberfläche und mehreren elektronischen Bauelementen auf der gegenüberliegenden zweiten Substratoberfläche, wobei die Bauelemente Bauelementkontakte aufweisen, die über Durchkontaktierungen in dem Schaltungssubstrat und die Leiterkonfiguration selektiv elektrisch angeschlossen sind. Sie betrifft des Weiteren ein Verfahren zur Herstellung einer solchen Baugruppe.The invention relates to an electronic assembly on a flexible planar circuit substrate having a conductor configuration on a first substrate surface and a plurality of electronic components on the opposite second substrate surface, wherein the components comprise component contacts which are selectively electrically connected via vias in the circuit substrate and the conductor configuration. It further relates to a method for producing such an assembly.

Elektronische Baugruppen, die auf flächigen Schaltungssubstraten mir vorgefertigter Leiterkonfiguration, sog. Leiterplatten, aufgebaut sind, sind seit Jahrzehnten aus der Elektronik und Elektrotechnik nicht mehr wegzudenken und sind Gegenstand ständiger Weiterentwicklung.Electronic assemblies, which are built on flat circuit substrates with prefabricated conductor configuration, so-called printed circuit boards, have been indispensable for decades in electronics and electrical engineering and are the subject of constant further development.

Von vielen Weiterentwicklungen haben in den letzten Jahren die sog. System-In-Package(SIP)-Lösungen und unter diesen speziell die Embedded Chips oder Chip-In-Polymer-Anordnungen besondere Aufmerksamkeit gefunden. Zum Stand der Technik auf diesem speziellen Gebiet verweisen wir auf L. Boettcher et al. "Embedding of Chips for System in Package realization - Technology and Applications", www.izm.fraunhofer.de , mit weiteren Literaturhinweisen. Bei dieser Technologie können, wie in der genannten Veröffentlichung angegeben, Standard-Leiterplattenaufbauten genutzt werden; bekannt ist auch der Einsatz von Schaltungssubstraten, die im Wesentlichen aus einem duroplastischen Polymer bestehen.
Es hat sich gezeigt, dass Standard-Leiterplattensubstrate speziell in aggressiven Umgebungen (etwa aggressiven atmosphärischen Umgebungen oder dem Körper von Lebewesen) chemisch nicht inert genug sind und/oder zu hohe Diffusionsraten für Sauerstoff bzw. Wasser haben. Die Anwendungsbereiche der genannten Technologie in Verbindung mit Standard-Leiterplatten sind daher in dieser Hinsicht begrenzt, und es wird nach alternativen Materialien gesucht. Bekannt ist hierbei, dass bestimmte thermoplastische Polymere insbesondere hinsichtlich niedriger Diffusionsraten von Sauerstoff, Wasser und Ionen vorteilhafte Eigenschaften haben; derartige Polymere sind aber beim thermischen Laminieren in der xy-Ebene nicht sehr stabil. Deshalb zieht der Fachmann derartige Schaltungssubstrat-Materialien im Hinblick auf die hohen Stabilitätsanforderungen des Substrats bei der Positionierung vieler mikroelektronischer Schaltkreise oder anderer elektronischer Bauelemente auf einem einzelnen Substrat üblicherweise nicht in Betracht.Of many developments in recent years, the so-called system-in-package (SIP) solutions and especially the embedded chips or chip-in-polymer arrangements have received special attention. We refer to the state of the art in this particular field L. Boettcher et al. "Embedding of Chips for Systems in Package Realization - Technology and Applications", www.izm.fraunhofer.de , with further references. In this technology, as stated in said publication, standard printed circuit board assemblies can be used; Also known is the use of circuit substrates, which consist essentially of a thermosetting polymer.
It has been found that standard circuit board substrates, especially in aggressive environments (such as aggressive atmospheric environments or the living body), are not chemically inert enough and / or have too high a diffusion rate for oxygen or water. The areas of application of said technology in connection with Standard printed circuit boards are therefore limited in this regard, and looking for alternative materials. It is known here that certain thermoplastic polymers have advantageous properties, in particular with regard to low diffusion rates of oxygen, water and ions; However, such polymers are not very stable in thermal lamination in the xy plane. Therefore, those skilled in the art usually do not consider such circuit substrate materials in view of the high stability requirements of the substrate in positioning many microelectronic circuits or other electronic devices on a single substrate.

Aufgabe der Erfindung ist es, eine verbesserte elektronische Baugruppe, die insbesondere mit einer hohen Positionsgenauigkeit der eingesetzten Bauelemente gefertigt werden kann und für den Einsatz in implantierbaren Geräten sowie in für aggressive Umgebungen geeigneten Geräten optimiert ist, sowie ein Verfahren zu deren Herstellung anzugeben.The object of the invention is to provide an improved electronic assembly, which can be manufactured in particular with a high position accuracy of the components used and is optimized for use in implantable devices and in equipment suitable for aggressive environments, and to provide a method for their production.

Diese Aufgabe wird in ihrem Vorrichtungsaspekt durch eine elektronische Baugruppe mit den Merkmalen des Anspruchs 1 und in ihrem Verfahrensaspekt durch ein Verfahren mit den Merkmalen des Anspruchs 10 gelöst. Zweckmäßige Fortbildungen des Erfindungsgedankens sind Gegenstand der jeweiligen abhängigen Ansprüche.This object is achieved in its device aspect by an electronic assembly having the features of claim 1 and in its method aspect by a method having the features of claim 10. Advantageous further developments of the inventive concept are the subject of the respective dependent claims.

Die Erfindung beinhaltet eine bewusste Abkehr von der allgemein geltenden Einschätzung, dass thermoplastische Polymere als Substratmaterial des Schaltungssubstrat elektronischer Baugruppen aus mechanischen Gründen nicht geeignet sind, und sie schließt weiterhin strukturelle wie auch technologische Aspekte ein, mit denen eine elektronische Baugruppe unter Einsatz eines derartigen Schaltungssubstrats unter Erfüllung aller Anforderungen realisiert werden kann.The invention includes a deliberate departure from the generally accepted view that thermoplastic polymers are unsuitable as a substrate material of the circuit substrate of electronic assemblies for mechanical reasons, and further includes structural as well as technological aspects with which an electronic package using such a circuit substrate may be incorporated Fulfillment of all requirements can be realized.

Die Merkmale der erfindungsgemäßen Baugruppe sind im Sinne des weit aufgefächerten Standes der Technik mit dem breitestmöglichen Bedeutungsgehalt zu verstehen. Obgleich das Vorliegen einer solchen Leiterkonfiguration auf der ersten Substratoberfläche wesentlich ist, kann auch auf der zweiten Substratoberfläche eine Leiterkonfiguration angeordnet sein, und auch diese kann in der soeben genannten Weise ausgestaltet sein. Ähnlich können neben den erfindungsgemäß zumindest auf der zweiten Oberfläche des Schaltungssubstrats angeordneten Bauelementen auch auf der ersten Substratoberfläche Bauelemente platziert sein. Grundsätzlich ist auch eine mehrschichtige Ausführung der Baugruppe mit mehreren Schaltungssubstraten und jeweils zugeordneten ersten und zweiten Oberflächen und entsprechend positionierten Leiterkonfigurationen und Bauelementgruppen als im Rahmen der Erfindung liegend zu verstehen.The features of the assembly according to the invention are to be understood in terms of the widely fanned out prior art with the broadest possible meaning. Although the presence of such a conductor configuration on the first substrate surface is essential, a conductor configuration may also be disposed on the second substrate surface, and this may also be configured in the manner just mentioned. Similarly, in addition to the invention, at least on the second surface of the circuit substrate arranged components can also be placed on the first substrate surface components. In principle, a multilayer design of the assembly with a plurality of circuit substrates and associated first and second surfaces and correspondingly positioned conductor configurations and component groups is to be understood as being within the scope of the invention.

Die Durchkontaktierungen (Vias) umfassen in Durchbrüchen des Schaltungssubstrats realisierte Metallisierungen. Die Durchbrüche werden im Folgenden als "Bohrungen" bezeichnet, auch wenn sie nicht mittels eines Bohrwerkzeuges erzeugt werden, und obwohl sie nicht notwendigerweise kreiszylindrisch ausgeführt sind. In einem vorgefertigten Muster von Durchbrüchen bzw. "Bohrungen" kann in Ausführungen der Erfindung, entsprechend dem Bestückungsplan des Schaltungssubstrats nur eine vorbestimmte Teilmenge mit einer Metallisierung versehen sein. Solche Ausführungen sind mit einer selektiven Metallisierungstechnik (etwa mittels einer Metallisierungs-Maske) realisierbar. Alternativ können auch sämtliche Bohrungen des Bohrungsmusters mit einer Innenwand-Metallisierung versehen sein, was den zugehörigen Metallisierungsprozess vereinfacht und weniger fehleranfällig macht.The vias comprise metallizations implemented in openings of the circuit substrate. The breakthroughs are hereinafter referred to as "holes", even if they are not produced by means of a drilling tool, and although they are not necessarily designed circular cylindrical. In a prefabricated pattern of openings or "holes" can be provided in embodiments of the invention, according to the assembly plan of the circuit substrate, only a predetermined subset with a metallization. Such embodiments can be realized with a selective metallization technique (such as by means of a metallization mask). Alternatively, all the holes of the hole pattern can be provided with an inner wall metallization, which simplifies the associated metallization process and makes less prone to error.

In einer Ausführung der Erfindung sind die Leiterkonfiguration aus einer ersten Metallisierungsschicht und die Durchkontaktierungen aus einer zweiten Metallisierungsschicht gebildet. Dies bedeutet, dass die Grund-Verbindungsstruktur auf dem Schaltungssubstrat vorgefertigt und die Verbindung zwischen den eingesetzten Bauelementen und jener Grundstruktur nach dem Anfügen bzw. Einfügen der Bauelemente an/in das Schaltungssubstrat in einem späteren getrennten Schritt erzeugt werden kann.In one embodiment of the invention, the conductor configuration is formed of a first metallization layer and the plated-through holes are formed of a second metallization layer. This means that the basic connection structure can be prefabricated on the circuit substrate and the connection between the components used and that basic structure can be generated after the components have been added to the circuit substrate in a later separate step.

In bevorzugten Ausführungen weisen die Durchkontaktierungen eine in Bohrungen des Schaltungssubstrats abgeschiedene Metallisierung auf. Bedarfsweise ist hierbei die abgeschiedene Metallisierung galvanisch verstärkt. In weiteren Ausgestaltungen dieser Ausführungen weisen die Durchkontaktierungen mindestens ein Metall aus der Gruppe Kupfer, Gold, Titan, Wolfram, Palladium Chrom, Nickel auf.In preferred embodiments, the plated-through holes have a metallization deposited in bores of the circuit substrate. If necessary, in this case the deposited metallization is galvanically reinforced. In further embodiments of these embodiments, the plated-through holes have at least one metal from the group copper, gold, titanium, tungsten, palladium, chromium, nickel.

In einer weiteren vorteilhaften Ausführung ist die elektronische Baugruppe mit einer mindestens eines der Bauelemente einkapselnden thermoplastischen Schutzfolie mindestens auf der zweiten Substratoberfläche versehen. Diese kann aus dem gleichen Material wie das Schaltungssubstrat bestehen, je nach Anwendungssituation ist aber auch der Einsatz eines anderen thermoplastischen Materials möglich. In aus derzeitiger Sicht vorteilhaften Ausführungen weist das oder ein thermoplastisches Material mindestens ein Material aus der Gruppe flüssigkristallines Polymer, LCP; Polyetherketon, PEEK; fluorierte Polymere, oder Polyurethane auf.In a further advantageous embodiment, the electronic assembly is provided with at least one of the components encapsulating thermoplastic protective film at least on the second substrate surface. This may consist of the same material as the circuit substrate, but depending on the application situation, it is also possible to use another thermoplastic material. In embodiments which are advantageous from the current point of view, the or a thermoplastic material comprises at least one material from the group of liquid-crystalline polymer, LCP; Polyether ketone, PEEK; fluorinated polymers, or polyurethanes.

In weiteren Ausführungen weist das Schaltungssubstrat eine Dicke im Bereich zwischen 10 µm und 500 µm, insbesondere zwischen 10 µm und 100 µm, auf. Je nach Größe und Komplexität der elektronischen Baugruppe und der Anwendungssituation kommen grundsätzlich aber auch dünnere oder dickere Substrate in Betracht.In further embodiments, the circuit substrate has a thickness in the range between 10 .mu.m and 500 .mu.m, in particular between 10 .mu.m and 100 .mu.m. Depending on the size and complexity of the electronic assembly and the application situation, however, thinner or thicker substrates may also be considered.

In aus derzeitiger Sicht besonders vorteilhaften Funktionen/Anwendungen ist die elektronische Baugruppe ausgebildet als implantierbares elektromedizinisches Implantat oder Baugruppe eines solchen. Es kann sich aber auch speziell um ein Gerät oder eine Baugruppe eines Gerätes handeln, das/die unter "rauen" Umgebungsbedingungen, insbesondere in chemisch aggressiven Umgebungen, einzusetzen ist.In the current view particularly advantageous functions / applications, the electronic assembly is designed as an implantable electromedical implant or assembly of such. However, it can also be a device or an assembly of a device which is to be used under "harsh" environmental conditions, in particular in chemically aggressive environments.

Das erfindungsgemäße Verfahren zur Herstellung der vorab erläuterten Baugruppe umfasst zumindest die folgenden Schritte:

  • Bereitstellen des ein thermoplastisches Polymer aufweisenden flexiblen flächigen Schaltungssubstrats,
  • Erzeugen der Leiterkonfiguration auf der ersten Substratoberfläche,
  • Erzeugen eines Bohrungsmusters entsprechend der Geometrie der Leiterkonfiguration,
  • Erhitzen der auf die zweite Substratoberfläche aufzusetzenden Bauelemente,
  • mit dem Bohrungsmuster im Schaltungssubstrat ausgerichtetes Aufsetzen der Bauelemente auf die zweite Substratoberfläche mit vorbestimmtem Anpressdruck und hierdurch bewirktes Einschmelzen bzw. thermisches Einpressen der Bauelementkontakte in die zweite Substratoberfläche im Bereich der Bohrung,
  • selektive Metallabscheidung in das Bohrungsmuster und auf die Umgebung der Bohrungen von der ersten Substratoberfläche aus zur Erzeugung der Durchkontaktierungen.
Diese Schritte werden bevorzugt, aber nicht für jeden Schritt notwendigerweise, auch in der genannten Reihenfolge ausgeführt. Unter einer Leiterkonfiguration ist im allgemeinen Sinne ein geometrisches Muster mit im Wesentlichen linearen, möglicherweise aber auch flächigen leitfähigen Beschichtungsabschnitten zu verstehen, in das auch passive Funktionselemente, wie Widerstände, Induktivitäten und Kapazitäten, eingefügt sein können.The method according to the invention for producing the previously explained assembly comprises at least the following steps:
  • Providing the flexible sheet-like circuit substrate comprising a thermoplastic polymer,
  • Generating the conductor configuration on the first substrate surface,
  • Generating a hole pattern according to the geometry of the conductor configuration,
  • Heating the components to be placed on the second substrate surface,
  • Placing the components aligned with the bore pattern in the circuit substrate onto the second substrate surface with a predetermined contact pressure and thereby melting or thermally pressing the component contacts into the second substrate surface in the region of the bore;
  • selectively depositing metal into the bore pattern and surrounding the bores from the first substrate surface to create the vias.
These steps are preferred but not necessarily performed for each step, also in the order named. A conductor configuration is to be understood in a general sense as a geometrical pattern with essentially linear, but possibly also planar, conductive coating sections into which passive functional elements, such as resistors, inductances and capacitances, may also be inserted.

Weiterhin ist im Schritt, der dem Fixieren der Bauelemente im Schaltungssubstrat dient, statt eines Erwärmens der Bauelemente grundsätzlich auch eine Erwärmung des Schaltungssubstrats als solchen oder eine Kombination der Erwärmung sowohl der Bauelemente als auch des Schaltungssubstrats mit jeweils geeigneten Mitteln möglich.Furthermore, in the step which serves to fix the components in the circuit substrate, heating of the circuit substrate as such or a combination of heating both the components and the circuit substrate with suitable means is basically possible instead of heating the components.

In einer Ausführung der Erfindung werden die Bauelemente auf eine Aufsetztemperatur im Bereich zwischen 100°C und 400°C, insbesondere zwischen 250°C und 350°C erwärmt, und/oder der Anpressdruck liegt im Bereich zwischen 0,05N und 50N, insbesondere zwischen 0,1N und 30N.In one embodiment of the invention, the components are heated to a setting temperature in the range between 100 ° C and 400 ° C, in particular between 250 ° C and 350 ° C, and / or the contact pressure is in the range between 0.05N and 50N, in particular between 0.1N and 30N.

In vorteilhaften Ausführungen des Verfahrens wird die Metallabscheidung in das Bohrungsmuster nach dem Einschmelzen bzw. thermischen Einpressen der Bauelemente, insbesondere mittels eines elektrochemischen oder physikalischen Dünnschichtverfahrens, CVD bzw. PVD, ausgeführt. Es können hier herkömmliche, etablierte Abschaltungsverfahren eingesetzt werden, soweit nicht mit Blick auf das thermoplastische Substratmaterial bestimmte Einschränkungen erforderlich sind.In advantageous embodiments of the method, the metal deposition into the bore pattern after the melting or thermal pressing of the components, in particular by means of an electrochemical or physical thin-film process, CVD or PVD executed. Conventional, established shutdown methods can be used here, unless certain restrictions are required with regard to the thermoplastic substrate material.

Optional wird nach der Metallabscheidung eine galvanische Verstärkung der abgeschiedenen Dünnschicht ausgeführt. Die Notwendigkeit des Ausführens eines solchen weiteren (und hinsichtlich der Prozessbedingungen unter Umweltschutz- und Arbeitsschutzaspekten nicht unkritischen) Verfahrensschrittes ist eine Entscheidung aufgrund der erforderlichen Leitfähigkeit und Robustheit der Leiterkonfiguration bzw. Durchkontaktierungen zu treffen.Optionally, a galvanic reinforcement of the deposited thin film is carried out after the metal deposition. The need to carry out such another (and not uncritical in terms of environmental and occupational safety aspects of the process) process step is a decision to make because of the required conductivity and ruggedness of the conductor configuration or vias.

In einer aus derzeitiger Sicht bevorzugten Ausführung wird mindestens auf Bereiche der zweiten Substratoberfläche eine thermoplastische Schutzfolie auflaminiert. Dieses Auflaminieren kann im gleichen Schritt wie das Bestücken des Schaltungssubstrats mit den Bauelementen erfolgen, also gewissermaßen indem die Bauelemente beim Auflaminieren der Schutzfolie in das Schaltungssubstrat gepresst werden. Grundsätzlich ist aber auch eine Trennung beider Schritte möglich. Neben der zweiten Substratoberfläche kann auch die erste Substratoberfläche, also diejenige mit der Leiterkonfiguration, mit einer Schutzfolie bedeckt werden, so dass insbesondere eine beidseitige Versiegelung zum optimalen Schutz der elektronischen Baugruppe vor Umgebungseinflüssen realisiert wird.In a preferred embodiment from the present point of view, a thermoplastic protective film is laminated on at least areas of the second substrate surface. This lamination can be performed in the same step as the mounting of the circuit substrate with the components, so to speak, in that the components are pressed into the circuit substrate during lamination of the protective film. In principle, however, a separation of both steps is possible. In addition to the second substrate surface, the first substrate surface, ie the one with the conductor configuration, can also be covered with a protective film so that, in particular, a double-sided seal for optimal protection of the electronic assembly against environmental influences is realized.

Hinsichtlich der Verfahrensbedingungen, speziell Temperatur- und Anpressdruck, gelten die obigen Feststellungen für den Schritt des Bestückens des Schaltungssubstrats mit den Bauelementen normalerweise analog; beim Einsatz spezieller Laminierungsfolien sind aber ggfs. auch andere Verfahrensparameter einzustellen.With regard to the process conditions, especially temperature and contact pressure, the above findings for the step of mounting the circuit substrate to the devices are usually analog; if special lamination films are used, however, other process parameters may also need to be adjusted.

Vorteile und Zweckmäßigkeiten der Erfindung ergeben sich im Übrigen aus der nachfolgenden Beschreibung eines Ausführungsbeispiels anhand der Figuren. Von diesen zeigen:

Fig. 1
eine schematische Querschnittsdarstellung eines Ausführungsbeispiels der erfindungsgemäßen elektronischen Baugruppe während des Herstellungsprozesses und
Fig. 2
eine schematische Darstellung der Baugruppe nach Fig. 1 nach Fertigstellung.
Incidentally, advantages and expediencies of the invention emerge from the following description of an exemplary embodiment with reference to the figures. From these show:
Fig. 1
a schematic cross-sectional view of an embodiment of the electronic assembly according to the invention during the manufacturing process and
Fig. 2
a schematic representation of the module according to Fig. 1 after completion.

Fig. 1 zeigt schematisch ein Schaltungssubstrat 3 einer (unfertigen) elektronischen Baugruppe 1, das aus einer LCP(flüssigkristallinen Polymer)-Folie 3a mit einer einseitig aufgeschichteten Leiterkonfiguration 3b besteht, zusammen mit einem Mikrochip 5, der auf einer Hauptoberfläche Bauelementkontakte 5a trägt. Der Mikrochip 5 ist auf der der Leiterkonfiguration 3b gegenüberliegenden Oberfläche des flexiblen flächigen Schaltungssubstrats 3 derart aufgesetzt, dass die Bauelementkontakte 5a mit einem Muster von Bohrungen 3c im Schaltungssubstrat 3 ausgerichtet sind. Fig. 1 1 schematically shows a circuit substrate 3 of an (unfinished) electronic package 1, which consists of an LCP (liquid crystal polymer) film 3a with a single-sided conductor configuration 3b, together with a microchip 5 carrying component contacts 5a on a main surface. The microchip 5 is placed on the surface of the flexible planar circuit substrate 3 opposite to the conductor configuration 3b in such a way that the component contacts 5a are aligned with a pattern of holes 3c in the circuit substrate 3.

Die Ausrichtung zwischen dem Bohrungsmuster im Schaltungssubstrat 3 und dem Mikrochip 5 wird mittels eines optischen Ausrichtungsverfahrens (Optical Alignement) ausgeführt, welches in der Figur durch einen Pfeil mit dem Bezugszeichen O.A. symbolisiert ist. Für diesen Schritt können branchentypische Montagesysteme wie Bilderfassung verwendet werden. Dabei werden die Bohrungen 3c im Schaltungssubstrat (der LCP-Folie) optisch aufgenommen und die Bauelemente mit geringer Lagetoleranz (ca. 5-25 µm) auf dem Schaltungssubstrat positioniert.The alignment between the hole pattern in the circuit substrate 3 and the microchip 5 is carried out by an optical alignment method which is indicated by an arrow with the reference O.A. is symbolized. Industry-typical mounting systems such as image acquisition can be used for this step. The holes 3c in the circuit substrate (the LCP film) are optically picked up and the components are positioned on the circuit substrate with a small positional tolerance (about 5-25 μm).

Bei der Positionierung wird der Mikrochip 5 auf eine Temperatur in der Nähe des Tg der LCP-Folie 3a, z.B. einen Wert im Bereich zwischen 250°C und 350°C, erwärmt und mit vorbestimmter Kraft, beispielsweise im Bereich zwischen 0,1N und 30N, in die benachbarte Oberfläche der LCP-Folie gedrückt. Diese wird dabei lokal erwärmt und damit erweicht, so dass die Bauelementkontakte 5a sich in die benachbarte Umgebung der Bohrungen 3c eindrücken und das Bauelement spaltfrei bündig an der benachbarten Oberfläche des Schaltungssubstrats 3 haftet.In positioning, the microchip 5 is set at a temperature near the Tg of the LCP film 3a, e.g. a value in the range between 250 ° C and 350 ° C, heated and pressed with a predetermined force, for example in the range between 0.1N and 30N, in the adjacent surface of the LCP film. This is locally heated and thus softened, so that the component contacts 5a press into the adjacent environment of the holes 3c and the component adheres gap-free flush to the adjacent surface of the circuit substrate 3.

Fig. 2 zeigt den Fertigstellungszustand der Baugruppe 1, in dem das erwähnte Anhaften des Mikrochips 5 am Schaltungssubstrat bei in die Oberfläche eingedrungenen Bauelementkontakten 5a gegeben und in der Figur zu erkennen ist. Des Weiteren ist in diesem Zustand eine Metallisierung mit der dem Mikrochip 5 gegenüberliegenden Oberfläche des Schaltungssubstrats 3 selektiv in denjenigen Bohrungen 3c erfolgt, in denen Bauelementkontakte 5a sitzen. Hierdurch sind Durchkontaktierungen 7 gebildet, die sich als Innenwand-Metallisierung der entsprechenden Bohrungen 3c von den Bauelementkontakten 5 bis auf die Leiterkonfiguration 3b erstrecken und so die Bauelementkontakte mit der Leiterkonfiguration elektrisch verbinden. Diese Innenwand-Metallisierung kann durch ein elektrochemisches oder physikalisches Dünnfilmverfahren oder auch eine Kombination solcher Verfahren erzeugt werden. Fig. 2 shows the completion state of the assembly 1, in which the mentioned adhesion of the microchip 5 on the circuit substrate given in the surface penetrated component contacts 5a and can be seen in the figure. Furthermore, in this state, a metallization with the surface of the circuit substrate 3 opposite the microchip 5 is selectively effected in those bores 3c in which component contacts 5a are seated. As a result, plated-through holes 7 are formed, which extend as inner-wall metallization of the corresponding bores 3c from the component contacts 5 to the conductor configuration 3b and thus electrically connect the component contacts to the conductor configuration. This inner wall metallization may be produced by a thin-film electrochemical or physical process, or a combination of such techniques.

Anschließend wurde auf beide Oberflächen des Schaltungssubstrats 3 jeweils eine Schutzfolie 9.1 bzw. 9.2 auflaminiert. Auch die Schutzfolien 9.1, 9.2 bestehen aus einem thermoplastischen Material, beispielsweise einer mit der LCP-Folie 3a gleichartigen LCP-Folie. Diese verkapselt die elektronische Baugruppe 1 weitgehend diffusionsdicht gegenüber der Umgebung und ermöglicht so den Einsatz in medizinischen Implantaten oder Geräten zum Einsatz in rauen Umgebungen.Subsequently, in each case a protective film 9.1 or 9.2 was laminated on both surfaces of the circuit substrate 3. The protective films 9.1, 9.2 are made of a thermoplastic material, for example a LCP film similar to the LCP film 3a. This encapsulates the electronic module 1 largely diffusion-tight with respect to the environment and thus enables use in medical implants or devices for use in harsh environments.

Im Übrigen ist die Ausführung der Erfindung auch in einer Vielzahl von Abwandlungen der hier gezeigten Beispiele und weiter oben hervorgehobenen Aspekte der Erfindung möglich.Incidentally, the embodiment of the invention is also possible in a variety of modifications of the examples shown here and aspects of the invention highlighted above.

Claims (15)

Elektronische Baugruppe (1) auf einem flexiblen flächigen Schaltungssubstrat (3) mit einer Leiterkonfiguration (3b) auf einer ersten Substratoberfläche und mehreren elektronischen Bauelementen (5) auf der gegenüberliegenden zweiten Substratoberfläche, wobei die Bauelemente Bauelementkontakte (5a) aufweisen, die über Durchkontaktierungen (7) in dem Schaltungssubstrat (3) und die Leiterkonfiguration (3b) selektiv elektrisch angeschlossen sind,
wobei das Schaltungssubstrat (3) ein thermoplastisches Polymer aufweist und die Bauelementkontakte (5a) im Bereich der Durchkontaktierungen (7) in die zweite Substratoberfläche eingeschmolzen bzw. thermisch eingepresst sind.Electronic assembly (1) on a flexible planar circuit substrate (3) having a conductor configuration (3b) on a first substrate surface and a plurality of electronic components (5) on the opposite second substrate surface, wherein the components comprise component contacts (5a) which are connected via plated-through holes (7 ) in the circuit substrate (3) and the conductor configuration (3b) are selectively electrically connected,
wherein the circuit substrate (3) comprises a thermoplastic polymer and the component contacts (5a) in the region of the plated-through holes (7) are fused or thermally pressed into the second substrate surface. Elektronische Baugruppe (1) nach Anspruch 1, wobei die Leiterkonfiguration (3b) aus einer ersten Metallisierungsschicht und die Durchkontaktierungen (7) aus einer zweiten Metallisierungsschicht gebildet sind.The electronic package (1) of claim 1, wherein the conductor configuration (3b) is formed of a first metallization layer and the vias (7) are formed of a second metallization layer. Elektronische Baugruppe (1) nach einem der vorangehenden Ansprüche, wobei die Durchkontaktierungen (7) eine in Bohrungen (3c) des Schaltungssubstrats (3) abgeschiedene Metallisierung aufweisen.Electronic assembly (1) according to one of the preceding claims, wherein the plated-through holes (7) have a metallization deposited in bores (3c) of the circuit substrate (3). Elektronische Baugruppe (1) nach Anspruch 3, wobei die abgeschiedene Metallisierung galvanisch verstärkt ist.The electronic package (1) of claim 3, wherein the deposited metallization is galvanically reinforced. Elektronische Baugruppe (1) nach Anspruch 3 oder 4, wobei die Durchkontaktierungen (7) mindestens ein Metall aus der Gruppe Kupfer, Gold, Titan, Wolfram, Palladium Chrom, Nickel aufweisen.Electronic assembly (1) according to claim 3 or 4, wherein the plated-through holes (7) comprise at least one metal selected from the group copper, gold, titanium, tungsten, palladium, chromium, nickel. Elektronische Baugruppe (1) nach einem der vorangehenden Ansprüche, mit einer mindestens eines der Bauelemente (5) einkapselnden thermoplastischen Schutzfolie (9.1, 9.2) mindestens auf der zweiten Substratoberfläche.Electronic assembly (1) according to one of the preceding claims, comprising at least one of the components (5) encapsulating thermoplastic protective film (9.1, 9.2) at least on the second substrate surface. Elektronische Baugruppe (1) nach einem der vorangehenden Ansprüche, wobei das oder ein thermoplastisches Material mindestens ein Material aus der Gruppe flüssigkristallines Polymer, LCP; Polyetherketon, PEEK; fluoriertes Polymer oder Polyurethan aufweist.An electronic assembly (1) according to any one of the preceding claims, wherein the or a thermoplastic material comprises at least one of liquid crystalline polymer, LCP; Polyether ketone, PEEK; fluorinated polymer or polyurethane. Elektronische Baugruppe (1) nach einem der vorangehenden Ansprüche, wobei das Schaltungssubstrat (3) eine Dicke im Bereich zwischen 10 µm und 500 µm, insbesondere zwischen 10 µm und 100 µm, aufweist.Electronic assembly (1) according to one of the preceding claims, wherein the circuit substrate (3) has a thickness in the range between 10 .mu.m and 500 .mu.m, in particular between 10 .mu.m and 100 .mu.m. Elektronische Baugruppe (1) nach einem der vorangehenden Ansprüche, ausgebildet als implantierbares elektromedizinisches Implantat oder Baugruppe eines solchen.Electronic assembly (1) according to one of the preceding claims, designed as an implantable electromedical implant or assembly of such. Verfahren zur Herstellung einer elektronischen Baugruppe nach einem der vorangehenden Ansprüche, mit den Schritten: - Bereitstellen des ein thermoplastisches Polymer aufweisenden flexiblen flächigen Schaltungssubstrats (3), - Erzeugen der Leiterkonfiguration (3b) auf der ersten Substratoberfläche, - Erzeugen eines Bohrungsmusters entsprechend der Geometrie der Leiterkonfiguration (3b), - Erhitzen der auf die zweite Substratoberfläche aufzusetzenden Bauelemente (5), - mit dem Bohrungsmuster im Schaltungssubstrat (3) ausgerichtetes Aufsetzen der Bauelemente (5) auf die zweite Substratoberfläche mit vorbestimmtem Anpressdruck und hierdurch bewirktes Einschmelzen bzw. thermisches Einpressen der Bauelementkontakte in die zweite Substratoberfläche im Bereich der Bohrung (3c), - selektive Metallabscheidung in das Bohrungsmuster und auf die Umgebung der Bohrungen (3c) von der ersten Substratoberfläche aus zur Erzeugung der Durchkontaktierungen (7). Method for producing an electronic assembly according to one of the preceding claims, with the steps: Providing the flexible sheet-like circuit substrate (3) comprising a thermoplastic polymer, Generating the conductor configuration (3b) on the first substrate surface, Generating a hole pattern corresponding to the geometry of the conductor configuration (3b), Heating the components (5) to be placed on the second substrate surface, - placing the components (5) aligned with the hole pattern in the circuit substrate (3) on the second substrate surface with a predetermined contact pressure and thereby melting or thermal pressing of the component contacts in the second substrate surface in the region of the bore (3c), selective metal deposition into the bore pattern and to the surroundings of the bores (3c) from the first substrate surface to produce the plated-through holes (7). Verfahren nach Anspruch 10, wobei die Bauelemente (5) auf eine Aufsetztemperatur im Bereich zwischen 100°C und 400°C, insbesondere zwischen 250°C und 350°C erwärmt werden und/oder der Anpressdruck im Bereich zwischen 0,05N und 50N, insbesondere zwischen 0,1N und 30N liegt.A method according to claim 10, wherein the components (5) are heated to a setting temperature in the range between 100 ° C and 400 ° C, in particular between 250 ° C and 350 ° C and / or the contact pressure in the range between 0.05N and 50N, in particular between 0.1N and 30N. Verfahren nach Anspruch 10 oder 11, wobei die Metallabscheidung in das Bohrungsmuster nach dem Einschmelzen bzw. thermischen Einpressen der Bauelemente (5), insbesondere mittels eines elektrochemischen oder physikalischen Dünnschichtverfahrens, CVD bzw. PVD, ausgeführt wird.The method of claim 10 or 11, wherein the metal deposition in the bore pattern after the melting or thermal pressing of the components (5), in particular by means of an electrochemical or physical thin-film method, CVD or PVD, is performed. Verfahren nach Anspruch 12, wobei nach der Metallabscheidung eine galvanische Verstärkung der abgeschiedenen Dünnschicht ausgeführt wird.The method of claim 12, wherein after the metal deposition, a galvanic reinforcement of the deposited thin film is carried out. Verfahren nach einem der Ansprüche 10 bis 13, wobei mindestens auf Bereiche der zweiten Substratoberfläche eine thermoplastische Schutzfolie (9.1, 9.2) auflaminiert wird.Method according to one of claims 10 to 13, wherein at least on regions of the second substrate surface, a thermoplastic protective film (9.1, 9.2) is laminated. Verfahren nach Anspruch 14, wobei das Auflaminieren der Schutzfolie (9.1, 9.2) bei einer Temperatur im Bereich zwischen 100°C und 400°C, insbesondere zwischen 250°C und 350°C erfolgt und/oder der Anpressdruck im Bereich zwischen 0,05N und 50N, insbesondere zwischen 0,1N und 30N liegt.The method of claim 14, wherein the lamination of the protective film (9.1, 9.2) at a temperature in the range between 100 ° C and 400 ° C, in particular between 250 ° C and 350 ° C takes place and / or the contact pressure in the range between 0.05N and 50N, in particular between 0.1N and 30N.
EP17174971.6A 2017-06-08 2017-06-08 Electronic assembly and method for producing an electronic assembly Withdrawn EP3413342A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP17174971.6A EP3413342A1 (en) 2017-06-08 2017-06-08 Electronic assembly and method for producing an electronic assembly
EP18174093.7A EP3413343A3 (en) 2017-06-08 2018-05-24 Electronic module and method for producing same
US15/993,935 US10932386B2 (en) 2017-06-08 2018-05-31 Electronic module and method for producing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP17174971.6A EP3413342A1 (en) 2017-06-08 2017-06-08 Electronic assembly and method for producing an electronic assembly

Publications (1)

Publication Number Publication Date
EP3413342A1 true EP3413342A1 (en) 2018-12-12

Family

ID=59067495

Family Applications (2)

Application Number Title Priority Date Filing Date
EP17174971.6A Withdrawn EP3413342A1 (en) 2017-06-08 2017-06-08 Electronic assembly and method for producing an electronic assembly
EP18174093.7A Pending EP3413343A3 (en) 2017-06-08 2018-05-24 Electronic module and method for producing same

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP18174093.7A Pending EP3413343A3 (en) 2017-06-08 2018-05-24 Electronic module and method for producing same

Country Status (2)

Country Link
US (1) US10932386B2 (en)
EP (2) EP3413342A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3799114A1 (en) 2019-09-27 2021-03-31 Dyconex AG Thermal compression bonding of electronic components
EP3797828A1 (en) * 2019-09-27 2021-03-31 Dyconex AG Releasable seal for medical implants

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030111742A1 (en) * 2001-12-18 2003-06-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20040084769A1 (en) * 2002-10-30 2004-05-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US20060049495A1 (en) * 2002-11-20 2006-03-09 Nec Corporation Semiconductor package and laminated semiconductor package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US8049338B2 (en) * 2006-04-07 2011-11-01 General Electric Company Power semiconductor module and fabrication method
KR101003585B1 (en) * 2008-06-25 2010-12-22 삼성전기주식회사 Electronic component embedded printed circuit board and manufacturing method
JP2010147331A (en) * 2008-12-19 2010-07-01 Seiko Instruments Inc Electronic device and method for manufacturing the same
US8114712B1 (en) * 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package
JP6285638B2 (en) * 2013-04-25 2018-02-28 日本メクトロン株式会社 Printed wiring board and printed wiring board manufacturing method
US10872879B2 (en) * 2015-11-12 2020-12-22 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor package and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030111742A1 (en) * 2001-12-18 2003-06-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US20040084769A1 (en) * 2002-10-30 2004-05-06 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing the same
US20060049495A1 (en) * 2002-11-20 2006-03-09 Nec Corporation Semiconductor package and laminated semiconductor package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
L. BOETTCHER ET AL., EMBEDDING OF CHIPS FOR SYSTEM IN PACKAGE REALIZATION - TECHNOLOGY AND APPLICATIONS, Retrieved from the Internet <URL:www.izm.fraunhofer.de, mit weiteren Literaturhinweisen>

Also Published As

Publication number Publication date
US20180359874A1 (en) 2018-12-13
US10932386B2 (en) 2021-02-23
EP3413343A2 (en) 2018-12-12
EP3413343A3 (en) 2018-12-19

Similar Documents

Publication Publication Date Title
DE102008017454B4 (en) Power semiconductor module with hermetically sealed circuit arrangement and manufacturing method for this purpose
DE3020196C2 (en) Multilevel printed circuit board and process for its manufacture
EP2524394B1 (en) Electronic device, method for producing the latter, and printed circuit board comprising electronic device
EP2668835B1 (en) Method for integrating an electronic component into a printed circuit board or a printed circuit board intermediate product
DE19961842B4 (en) Multilayer circuit board
EP1394855B1 (en) Method of manufacturing a universal housing for an electronic semiconductor device
EP2973671B1 (en) Method for the production of an electronic sub-assembly
DE2736055B2 (en) Multilayer printed circuit board and method of making the multilayer printed circuit board
DE112015006047B4 (en) MANUFACTURING PROCESS FOR A SPATIAL PCB, ROOMED PCB AND SUBSTRATE FOR A SPATIAL PCB
WO2009143550A1 (en) Method for integrating at least one electronic component into a printed circuit board, and printed circuit board
EP3231261A1 (en) Circuit board having an asymmetric layer structure
EP2973687B1 (en) Electronic sub-assembly, method for the production thereof and printed circuit board having an electronic sub-assembly
WO2016091995A1 (en) Semiflexible printed circuit board with embedded component
EP3413342A1 (en) Electronic assembly and method for producing an electronic assembly
EP2982226B1 (en) Method for producing a circuit board element
WO2013029074A1 (en) Method for integrating a component into a printed circuit board or a printed circuit board intermediate product, and printed circuit board or printed circuit board intermediate product
EP2018666A2 (en) Method for fixing an electronic component on a printed circuit board and system comprising a printed circuit board and at least one electronic component
DE102014222818A1 (en) Electronic sandwich structure with two joining partners sintered together by means of a sintered layer
DE102020103487B4 (en) Process for producing a glass-ceramic composite substrate
DE102016219733A1 (en) Method for producing a multilayer printed circuit board
DE102009027470A1 (en) Forming a contact surface on a circuit board
DE102020208591B4 (en) Modular wiring semi-finished product, wiring module and wiring component and method for manufacturing the same
WO2011042197A1 (en) Method for producing a printed circuit board, in particular a multilayer printed circuit board
DE102007036046A1 (en) Planar electronic module, has contact conductor structure connecting component contact surface with contact surface and/or multiple contact or component contact surfaces with one another, and exhibiting electric strength of specific range
DE102016003121B4 (en) Printed circuit board assembly

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20190613