EP3230873A1 - Computing method and apparatus with persistent memory - Google Patents
Computing method and apparatus with persistent memoryInfo
- Publication number
- EP3230873A1 EP3230873A1 EP15868489.4A EP15868489A EP3230873A1 EP 3230873 A1 EP3230873 A1 EP 3230873A1 EP 15868489 A EP15868489 A EP 15868489A EP 3230873 A1 EP3230873 A1 EP 3230873A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- type
- persistent
- page
- volatile
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0622—Securing storage systems in relation to access
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/22—Employing cache memory using specific memory technology
- G06F2212/225—Hybrid cache memory, e.g. having both volatile and non-volatile portions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/601—Reconfiguration of cache memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
Definitions
- the 2LM configuration may include a first level of memory represented by software transparent near memory cache 104 and a second level of memory represented by persistent memory 106, which may also be referred to in such a configuration as main memory.
- persistent memory may refer to media having properties of both conventional volatile memory (e.g., dynamic random access memory (DRAM)) and conventional persistent storage devices (e.g., magnetic disk). Like volatile memory, persistent memory may be byte-addressable, which is not possible with conventional persistent storage devices. In addition, persistent memory may be capable of achieving data read and write speeds that are closer to that of volatile memory than conventional storage devices. However, as with conventional persistent storage devices, data stored in persistent memory may be persistent, or non-volatile. As used herein persistent and nonvolatile may be treated as synonymous unless the context clearly indicates otherwise. As such, even though the underlying media of persistent memory may be persistent, persistent memory may also be utilized in place of volatile memory to store volatile data in addition to persistent data.
- DRAM dynamic random access memory
- magnetic disk e.g., magnetic disk.
- persistent memory may be byte-addressable, which is not possible with conventional persistent storage devices.
- persistent memory may be capable of achieving data read and write speeds that are closer to that of volatile memory than conventional storage devices
- System software 202 may be configured to receive volatile and persistent memory allocation requests from applications 1 and 2. In response to the memory allocation requests, system software 202 may dynamically allocate memory pages of persistent memory modules 212 as either volatile type memory pages or persistent type memory pages. As such, the system software may be able to dynamically grow or shrink the amount of volatile type memory available to the one or more applications.
- Example 7 may include the subject matter of any one of Examples 2-6, wherein the system software is further to: initialize at least a subset of the memory pages of the plurality of persistent memory modules as persistent type memory pages, and wherein to dynamically allocate memory pages of the persistent memory modules as volatile type memory pages involves conversion of persistent type memory pages to volatile type memory pages.
- Example 17 may include the subject matter of any one of Examples 1 1-16, further comprising: releasing, by the system software, volatile type memory pages for reallocation in response to a reset procedure or shut-down procedure of the apparatus.
- Example 20 may include the subject matter of Example 19, wherein the system software is further to: receive a conversion request to change a memory page allocated from one type of memory page to another type of memory page; and convert, in response to the conversion request, the memory page allocated from the one type of memory page to the another type of memory page.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/567,662 US9715453B2 (en) | 2014-12-11 | 2014-12-11 | Computing method and apparatus with persistent memory |
| PCT/US2015/059739 WO2016094003A1 (en) | 2014-12-11 | 2015-11-09 | Computing method and apparatus with persistent memory |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP3230873A1 true EP3230873A1 (en) | 2017-10-18 |
| EP3230873A4 EP3230873A4 (en) | 2018-07-18 |
| EP3230873B1 EP3230873B1 (en) | 2021-01-13 |
Family
ID=56107913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP15868489.4A Active EP3230873B1 (en) | 2014-12-11 | 2015-11-09 | Computing method and apparatus with persistent memory |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9715453B2 (en) |
| EP (1) | EP3230873B1 (en) |
| CN (1) | CN107111454B (en) |
| WO (1) | WO2016094003A1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10409603B2 (en) * | 2016-12-30 | 2019-09-10 | Intel Corporation | Processors, methods, systems, and instructions to check and store indications of whether memory addresses are in persistent memory |
| US10606513B2 (en) | 2017-12-06 | 2020-03-31 | Western Digital Technologies, Inc. | Volatility management for non-volatile memory device |
| US11579770B2 (en) | 2018-03-15 | 2023-02-14 | Western Digital Technologies, Inc. | Volatility management for memory device |
| CN108763105B (en) * | 2018-05-28 | 2020-12-01 | 深圳忆联信息系统有限公司 | Method and device for improving writing performance of solid-state storage equipment and computer equipment |
| US11157319B2 (en) | 2018-06-06 | 2021-10-26 | Western Digital Technologies, Inc. | Processor with processor memory pairs for improved process switching and methods thereof |
| US10481817B2 (en) * | 2018-06-28 | 2019-11-19 | Intel Corporation | Methods and apparatus to optimize dynamic memory assignments in multi-tiered memory systems |
| US11789870B2 (en) * | 2019-05-24 | 2023-10-17 | Microsoft Technology Licensing, Llc | Runtime allocation and utilization of persistent memory as volatile memory |
| US11392428B2 (en) | 2019-07-17 | 2022-07-19 | Memverge, Inc. | Fork handling in application operations mapped to direct access persistent memory |
| US11526433B2 (en) | 2020-03-12 | 2022-12-13 | International Business Machines Corporation | Data structure allocation into storage class memory during compilation |
| CN112434025B (en) * | 2020-10-29 | 2022-08-12 | 苏州浪潮智能科技有限公司 | A method, system, device and medium for optimizing index persistence |
| US11704029B2 (en) | 2021-04-16 | 2023-07-18 | Micron Technology, Inc. | Elastic persistent memory regions |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7716411B2 (en) * | 2006-06-07 | 2010-05-11 | Microsoft Corporation | Hybrid memory device with single interface |
| WO2008055271A2 (en) * | 2006-11-04 | 2008-05-08 | Virident Systems, Inc. | Seamless application access to hybrid main memory |
| US8874831B2 (en) | 2007-06-01 | 2014-10-28 | Netlist, Inc. | Flash-DRAM hybrid memory module |
| US20100241815A1 (en) | 2009-03-20 | 2010-09-23 | Google Inc. | Hybrid Storage Device |
| WO2011019216A2 (en) | 2009-08-13 | 2011-02-17 | Lg Electronics Inc. | Hybrid storage device, and control method |
| KR101713051B1 (en) * | 2010-11-29 | 2017-03-07 | 삼성전자주식회사 | Hybrid Memory System and Management Method there-of |
| US9164923B2 (en) * | 2011-07-01 | 2015-10-20 | Intel Corporation | Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform |
| CN102231138B (en) * | 2011-07-08 | 2013-07-03 | 上海交通大学 | Accurate memory data acquisition system and method for computer |
| CN103890737B (en) * | 2011-10-07 | 2016-09-21 | 慧与发展有限责任合伙企业 | mapped persistent storage |
| US9158700B2 (en) | 2012-01-20 | 2015-10-13 | Seagate Technology Llc | Storing cached data in over-provisioned memory in response to power loss |
| US20130198453A1 (en) | 2012-01-26 | 2013-08-01 | Korea Electronics Technology Institute | Hybrid storage device inclucing non-volatile memory cache having ring structure |
| US20130238851A1 (en) * | 2012-03-07 | 2013-09-12 | Netapp, Inc. | Hybrid storage aggregate block tracking |
| CN103176752A (en) * | 2012-07-02 | 2013-06-26 | 晶天电子(深圳)有限公司 | Super-endurance solid-state drive with Endurance Translation Layer (ETL) and diversion of temp files for reduced Flash wear |
| US9552231B2 (en) * | 2012-09-27 | 2017-01-24 | Adobe Systems Incorporated | Client classification-based dynamic allocation of computing infrastructure resources |
| US9128824B2 (en) * | 2012-12-24 | 2015-09-08 | Intel Corporation | In-place change between transient and persistent state for data structures on non-volatile memory |
| US20150279463A1 (en) * | 2014-03-31 | 2015-10-01 | Dell Products, L.P. | Adjustable non-volatile memory regions of dram-based memory module |
-
2014
- 2014-12-11 US US14/567,662 patent/US9715453B2/en active Active
-
2015
- 2015-11-09 EP EP15868489.4A patent/EP3230873B1/en active Active
- 2015-11-09 CN CN201580061783.7A patent/CN107111454B/en active Active
- 2015-11-09 WO PCT/US2015/059739 patent/WO2016094003A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP3230873B1 (en) | 2021-01-13 |
| US20160170645A1 (en) | 2016-06-16 |
| CN107111454A (en) | 2017-08-29 |
| WO2016094003A1 (en) | 2016-06-16 |
| CN107111454B (en) | 2020-07-14 |
| EP3230873A4 (en) | 2018-07-18 |
| US9715453B2 (en) | 2017-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9715453B2 (en) | Computing method and apparatus with persistent memory | |
| US10229065B2 (en) | Unified hardware and software two-level memory | |
| US9218343B2 (en) | Partition file system for virtual machine memory management | |
| US9396009B2 (en) | Optimized global capacity management in a virtualized computing environment | |
| US8578370B2 (en) | Managing memory in multiple virtual machines | |
| US10025503B2 (en) | Autonomous dynamic optimization of platform resources | |
| US10310974B2 (en) | Systems and methods for input/output computing resource control | |
| US8365169B1 (en) | Migrating a virtual machine across processing cells connected to an interconnect that provides data communication without cache coherency support | |
| US20160266923A1 (en) | Information processing system and method for controlling information processing system | |
| US9529616B2 (en) | Migrating processes between source host and destination host using a shared virtual file system | |
| TWI524185B (en) | Execution using multiple page tables | |
| WO2016041118A1 (en) | Memory management in virtualized computing | |
| WO2016112713A1 (en) | Processing method and device for memory page in memory | |
| US9298460B2 (en) | Register management in an extended processor architecture | |
| US10976934B2 (en) | Prioritizing pages to transfer for memory sharing | |
| CN107209720B (en) | System and method for page caching and storage medium | |
| US12086622B2 (en) | Optimizing virtual machine scheduling on non-uniform cache access (NUCA) systems | |
| US20230027307A1 (en) | Hypervisor-assisted transient cache for virtual machines | |
| US10776021B2 (en) | Exit-less host page table switching and virtual machine function detection with memory pages storing an identification value that are mapped at the same guest physical addresses | |
| US9753670B2 (en) | Prioritizing memory pages to copy for memory migration | |
| US10579392B2 (en) | System and method for mapping physical memory with mixed storage class memories | |
| TWI506436B (en) | Substitute virtualized-memory page tables |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
| 17P | Request for examination filed |
Effective date: 20170519 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
| AX | Request for extension of the european patent |
Extension state: BA ME |
|
| DAV | Request for validation of the european patent (deleted) | ||
| DAX | Request for extension of the european patent (deleted) | ||
| A4 | Supplementary search report drawn up and despatched |
Effective date: 20180618 |
|
| RIC1 | Information provided on ipc code assigned before grant |
Ipc: G06F 3/06 20060101ALI20180612BHEP Ipc: G06F 12/02 20060101AFI20180612BHEP Ipc: G06F 12/06 20060101ALI20180612BHEP |
|
| GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
| INTG | Intention to grant announced |
Effective date: 20200803 |
|
| GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
| AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
| REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602015064850 Country of ref document: DE |
|
| REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
| REG | Reference to a national code |
Ref country code: AT Ref legal event code: REF Ref document number: 1355077 Country of ref document: AT Kind code of ref document: T Effective date: 20210215 |
|
| REG | Reference to a national code |
Ref country code: NL Ref legal event code: FP |
|
| REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1355077 Country of ref document: AT Kind code of ref document: T Effective date: 20210113 |
|
| REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG9D |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210513 Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210413 Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210413 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210414 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: LT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210513 |
|
| REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602015064850 Country of ref document: DE |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| 26N | No opposition filed |
Effective date: 20211014 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210513 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20211109 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211109 Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211130 |
|
| REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20211130 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211130 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211130 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211109 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211109 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20211130 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: HU Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO Effective date: 20151109 |
|
| P01 | Opt-out of the competence of the unified patent court (upc) registered |
Effective date: 20230518 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20210113 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20240925 Year of fee payment: 10 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: NL Payment date: 20251024 Year of fee payment: 11 |