EP3223589B1 - Optoelectronic circuit comprising light-emitting diodes - Google Patents

Description

Field

The present description relates to an optoelectronic circuit, in particular an optoelectronic circuit comprising light-emitting diodes.

Presentation of the prior art

It is desirable to be able to supply an optoelectronic circuit comprising light-emitting diodes with a variable voltage, for example an alternating voltage, in particular a sinusoidal voltage, for example the mains voltage. The optoelectronic circuit may include light emitting diodes connected in series. The voltage applied to the set of light-emitting diodes must then be greater than the sum of the threshold voltages of the light-emitting diodes so that they emit light. In operation, the optoelectronic circuit may therefore have phases of absence of light emission between two light-emitting phases when the voltage applied to all the light-emitting diodes is less than the sum of the threshold voltages of the light-emitting diodes. . An observer may perceive this absence of light emission, especially as a flicker or flicker, when the duration of each phase absence of light emission between two light emission phases is too important.

To reduce the duration of the phases of absence of light emission, it is known to use a switching circuit of the light emitting diodes to reduce the number of light emitting diodes connected in series when the voltage applied to these light emitting diodes decreases. However, this does not completely eliminate the phases of absence of light emission.

A circuit for driving a plurality of light-emitting diodes is described in US2013 / 0313984 A1 .

summary

An object of an embodiment is to overcome all or part of the disadvantages of the optoelectronic circuits described above.

Another object of an embodiment is to further reduce the duration of the phases of absence of light emission by the optoelectronic circuit, or even to eliminate the phases of absence of light emission by the optoelectronic circuit even in case using a dimmer.

Another object of an embodiment is that the current supplying the light-emitting diodes varies substantially continuously.

• une pluralité de diodes électroluminescentes montées en série entre le premier noeud et un troisième noeud ;
• un premier circuit de limitation/régulation du courant monté entre le troisième noeud et le deuxième noeud ;
• un circuit de commutation reliant le troisième noeud à au moins certaines diodes électroluminescentes de la pluralité de diodes électroluminescentes ;
• un condensateur comprenant des première et deuxième armatures ;
• une première diode dont la cathode est connectée à la deuxième armature et dont l'anode est reliée au deuxième noeud ;
• une deuxième diode dont l'anode est connectée à la deuxième armature et dont la cathode est reliée au troisième noeud ou à un deuxième circuit de limitation/régulation du courant ;
• lorsque la cathode de la deuxième diode est reliée au troisième noeud, une troisième diode dont l'anode est connectée à l'une des diodes électroluminescentes et dont la cathode est connectée à la première armature ; et
• lorsque la cathode de la deuxième diode est reliée au troisième noeud, une quatrième diode dont l'anode est connectée à la première armature et dont la cathode est reliée au premier noeud.

Thus, an embodiment provides an optoelectronic circuit intended to receive, between a first node and a second node, a variable voltage containing an alternation of increasing positive phases and decreasing positive phase phases, the optoelectronic circuit comprising:

• a plurality of light emitting diodes connected in series between the first node and a third node;
• a first current limiting / regulating circuit mounted between the third node and the second node;
• a switching circuit connecting the third node to at least some light emitting diodes of the plurality of light emitting diodes;
• a capacitor comprising first and second armatures;
• a first diode whose cathode is connected to the second armature and whose anode is connected to the second node;
• a second diode whose anode is connected to the second armature and whose cathode is connected to the third node or to a second circuit for limiting / regulating the current;
• when the cathode of the second diode is connected to the third node, a third diode whose anode is connected to one of the electroluminescent diodes and whose cathode is connected to the first armature; and
• when the cathode of the second diode is connected to the third node, a fourth diode whose anode is connected to the first armature and whose cathode is connected to the first node.

According to one embodiment, the plurality of serially mounted LEDs comprise a first light emitting diode whose anode is connected to the first node, the anode of the third diode being connected to the cathode of the first light emitting diode.

According to one embodiment, the switching circuit comprises, for each light emitting diode among at least some light-emitting diodes of the plurality of light-emitting diodes, a circuit for conduction of the current connecting the third node to the cathode of the light-emitting diode and adapted to take at least first and second states, the conduction circuit in the first state being less electrically conductive than in the second state.

According to one embodiment, the switching circuit further comprises a conduction circuit of the current connecting the third node to the cathode of the second diode.

According to one embodiment, the first current limiting / regulation circuit comprises a first current source adapted to supply a current whose intensity depends on a setpoint.

According to one embodiment, the optoelectronic circuit comprises a first circuit adapted to receive said variable voltage and provide a pulse width modulated binary signal.

According to one embodiment, the optoelectronic circuit comprises a modulation and filtering circuit adapted to receive the binary signal and to supply the setpoint whose average value depends on the duty cycle of the binary signal.

According to one embodiment, the optoelectronic circuit further comprises a device for reducing the impedance seen between the first node and the second node.

According to one embodiment, the impedance reduction device comprises a third current limiting / regulating circuit and a transistor in series with the third current limiting / regulating circuit.

According to one embodiment, the impedance reduction device comprises a module adapted to control the transistor from the voltage across the third current limitation / regulation circuit.

Brief description of the drawings

• la figure 1 est un schéma électrique d'un exemple d'un circuit optoélectronique comprenant des diodes électroluminescentes ;
• la figure 2 est un chronogramme de puissances électriques du circuit optoélectronique de la figure 1 ;
• la figure 3 représente un schéma électrique d'un mode de réalisation d'un circuit optoélectronique comprenant des diodes électroluminescentes ;
• la figure 4 représente un diagramme de fonctionnement du circuit optoélectronique représenté en figure 3 ;
• la figure 5 est une figure analogue à la figure 3 dans un cas particulier et la figure 6 est un chronogramme de courants et de tensions du circuit optoélectronique de la figure 5 ;
• la figure 7 est une figure analogue à la figure 3 dans un autre cas particulier et la figure 8 est un chronogramme de courants et de tensions du circuit optoélectronique de la figure 7 ;
• la figure 9 est une figure analogue à la figure 3 dans un autre cas particulier et la figure 10 est un chronogramme de courants et de tensions du circuit optoélectronique de la figure 9 ;
• les figures 11, 12 et 13 représentent des schémas électriques d'autres modes de réalisation d'un circuit optoélectronique comprenant des diodes électroluminescentes ;
• la figure 14 représente un schéma électrique d'un mode de réalisation plus détaillé du circuit optoélectronique représenté en figure 3 ;
• la figure 15 représente un diagramme de fonctionnement d'un mode de réalisation d'un procédé de commande du circuit optoélectronique représenté en figure 14 ;
• la figure 16 représente un mode de réalisation plus détaillé d'un élément du circuit optoélectronique représenté en figure 14 ;
• la figure 17 représente un schéma électrique d'un autre mode de réalisation d'un circuit optoélectronique comprenant des diodes électroluminescentes ;
• la figure 18 représente un schéma électrique du circuit optoélectronique représenté en figure 3 et équipé d'un gradateur ;
• les figures 19 et 20 sont des chronogrammes de courants et de tensions du circuit optoélectronique de la figure 18 pour deux valeurs d'angle d'ouverture du gradateur ;
• les figures 21 et 22 représentent des schémas électriques de modes de réalisation d'un circuit optoélectronique adapté à fonctionner avec un gradateur ;
• la figure 23 est un chronogramme de tensions d'un mode de réalisation d'un module du circuit optoélectronique de la figure 21 ou 22 ;
• la figure 24 représente un schéma électrique d'un mode de réalisation d'un module du circuit optoélectronique de la figure 21 ou 22 fournissant les signaux du chronogramme de la figure 23 ;
• la figure 25 est un chronogramme de tensions d'un mode de réalisation d'un module du circuit optoélectronique de la figure 21 ou 22 ;
• la figure 26 représente un schéma électrique d'un mode de réalisation d'un module du circuit optoélectronique de la figure 21 ou 22 fournissant les signaux du chronogramme de la figure 25 ; et
• la figure 27 représente un schéma électrique d'un autre mode de réalisation d'un module du circuit optoélectronique de la figure 21 ou 22.

These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings in which:

• the figure 1 is an electrical diagram of an example of an optoelectronic circuit comprising light-emitting diodes;
• the figure 2 is a chronogram of electrical powers of the optoelectronic circuit of the figure 1 ;
• the figure 3 represents a circuit diagram of an embodiment of an optoelectronic circuit comprising light-emitting diodes;
• the figure 4 represents an operating diagram of the optoelectronic circuit represented in figure 3 ;
• the figure 5 is a figure similar to the figure 3 in a particular case and the figure 6 is a chronogram of currents and voltages of the optoelectronic circuit of the figure 5 ;
• the figure 7 is a figure similar to the figure 3 in another particular case and the figure 8 is a chronogram of currents and voltages of the optoelectronic circuit of the figure 7 ;
• the figure 9 is a figure similar to the figure 3 in another particular case and the figure 10 is a chronogram of currents and voltages of the optoelectronic circuit of the figure 9 ;
• the Figures 11, 12 and 13 show electrical diagrams of other embodiments of an optoelectronic circuit including light-emitting diodes;
• the figure 14 represents a circuit diagram of a more detailed embodiment of the optoelectronic circuit represented in figure 3 ;
• the figure 15 represents an operating diagram of an embodiment of a control method of the optoelectronic circuit represented in figure 14 ;
• the figure 16 represents a more detailed embodiment of an element of the optoelectronic circuit represented in figure 14 ;
• the figure 17 represents a circuit diagram of another embodiment of an optoelectronic circuit comprising light-emitting diodes;
• the figure 18 represents an electrical diagram of the optoelectronic circuit represented in figure 3 and equipped with a dimmer;
• the Figures 19 and 20 are chronograms of currents and voltages of the optoelectronic circuit of the figure 18 for two values of opening angle of the dimmer;
• the Figures 21 and 22 represent electrical diagrams of embodiments of an optoelectronic circuit adapted to operate with a dimmer;
• the figure 23 is a timing diagram of voltages of an embodiment of a module of the optoelectronic circuit of the figure 21 or 22 ;
• the figure 24 represents a circuit diagram of an embodiment of a module of the optoelectronic circuit of the figure 21 or 22 providing the timing diagram signals of the figure 23 ;
• the figure 25 is a timing diagram of voltages of an embodiment of a module of the optoelectronic circuit of the figure 21 or 22 ;
• the figure 26 represents a circuit diagram of an embodiment of a module of the optoelectronic circuit of the figure 21 or 22 providing the timing diagram signals of the figure 25 ; and
• the figure 27 represents a circuit diagram of another embodiment of a module of the optoelectronic circuit of the figure 21 or 22 .

detailed description

For the sake of clarity, the same elements have been designated by the same references in the various figures and, in addition, the various figures are not drawn to scale. Unless otherwise specified, the terms "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. In addition, a "signal binary" is a signal that alternates between a first constant state, for example a low state, denoted "0", and a second constant state, for example a high state, denoted "1". The high and low states of different binary signals of the same electronic circuit can be different. In practice, the binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state. Furthermore, in the present description, the term "connected" is used to denote a direct electrical connection, without intermediate electronic component, for example by means of a conductive track, and the term "coupled" or the term "connected", to designate either a direct electrical connection (meaning "connected") or a connection via one or more intermediate components (resistor, capacitor, etc.).

The figure 1 represents an example of an optoelectronic circuit 10 comprising input terminals IN ₁ and IN ₂ between which is applied an AC voltage V _IN supplied by a source of an alternating voltage 11. For example, the AC voltage V is considered _IN of the sector in the following description. The optoelectronic circuit 10 further comprises a rectifying circuit 12 comprising a diode bridge, receiving the voltage V _IN and providing a voltage V _RECT rectified between nodes A ₁ and A ₂ . Alternatively, the circuit 10 can directly receive a rectified voltage, the rectifier circuit 12 may not be present. The potential at the node A ₂ may correspond to the low reference potential, for example 0 V, with respect to which the voltages of the optoelectronic circuit 10 are referenced. In the rest of the description, the voltage supplied by the circuit is called V _ABS. Rectifier 12. The voltage V _ABS is therefore substantially equal to the absolute value of the AC voltage V _IN .

The optoelectronic circuit 10 comprises N series sets of elementary light-emitting diodes, called global electroluminescent diodes D _i in the remainder of the description, where i is an integer ranging from 1 to N and where N is an integer between 2 and 200 The threshold voltage of the light-emitting diode D _i is referred to as V _THi . Each global light-emitting diode D ₁ to D _N comprises at least one elementary light-emitting diode. Each global electroluminescent diode may be composed of the series and / or parallel connection of at least two elementary light-emitting diodes. In the present example, the N global light-emitting diodes D _i are connected in series, the cathode of the global light-emitting diode D _i being connected to the anode of the global light-emitting diode D _{i + 1} , for i ranging from 1 to N- 1. The anode of the global light-emitting diode D ₁ is connected to the node A ₁ . The global light-emitting diodes D _i , i ranging from 1 to N, may comprise the same number of diodes elemental electroluminescent or different numbers of elementary light-emitting diodes.

The circuit 10 comprises a current regulating / limiting circuit 14, mounted between the node A ₂ and a node A ₃ . Called V _CS terminal voltage of the _CS circuit 14 and I the current flowing between the nodes A ₃ and A _2. The circuit 14 corresponds, for example, to a resistor or a current source. The circuit 14 is adapted to limit and / or regulate the current I _CS .

The circuit 10 comprises a switching circuit 16 (AC-LED Driver) of global light emitting diodes D _i , i ranging from 1 to N adapted to short-circuit a larger or smaller number of global light-emitting diodes according to the evolution of the voltage V _RECT . The document US 2012/0056559 describes an example of a switching circuit. By way of example, the switching circuit 16 is connected to the node A ₃ and comprises N inputs E _i , i varying from 1 to N, each input E _i being connected to the cathode of the global light-emitting diode D _i . As a variant, the current regulation / limitation circuit 14 may be part of the switching circuit 16. For example, the switching circuit 16 comprises, for each input E _i , a conduction circuit, not shown, connecting the input E _i to the node A ₃ . Each conduction circuit can operate in K different conduction states, where K is an integer greater than or equal to 2. A conduction state is a state in which the circuit does not let the current pass or let the current flow with a resistance that may be different depending on the state considered. The number of global light-emitting diodes emitting light can thus increase gradually during a growth phase of the voltage V _RECT and gradually decreases during a phase of decreasing voltage V _RECT . As a variant, the number M of inputs E _i may be strictly less than N and the cathodes of some of the global light-emitting diodes D _i may not be connected to the switching circuit 16.

The optoelectronic circuit 10 may comprise a circuit, not shown, which provides a reference voltage for the supply of the limitation / regulation circuit 14, possibly obtained from the voltage V _RECT . When the circuit 14 corresponds to a current source, it can be controlled continuously by a circuit external to the optoelectronic circuit 10.

The figure 2 represents timing diagrams obtained by simulation for an optoelectronic circuit 10 having the structure represented in FIG. figure 1 and comprising 8 global light-emitting diodes D ₁ to D ₈ , electrical power P _ALIM supplied by the rectifier circuit 12, electrical power P _LED used by the global light-emitting diodes D ₁ to Dg, electrical power P _LOST not consumed. by the global light-emitting diodes D ₁ to Dg, and electrical powers P ₁ to P ₈ respectively consumed by the global light-emitting diodes D ₁ to D ₈ in the case where the AC voltage V _IN corresponds to a sinusoidal voltage. As it appears on the figure 2 , the global light emitting diodes D ₁ to D ₈ turn on successively during each increasing phase of the voltage V _RECT and turn off successively during each decreasing phase of the voltage V _RECT .

This makes it possible to reduce the duration of each phase of absence of light emission (OFF phase in figure 2 ). However, these phases of absence of light emission can not be totally removed. An observer can perceive this absence of light emission when the duration of each phase of absence of light emission between two light emission phases is too great. It would therefore be desirable to further reduce or even completely eliminate the phases of absence of light emission.

The figure 3 represents an embodiment of an optoelectronic circuit 20 making it possible to further reduce, or even completely eliminate, the phases of absence of emission of light. The optoelectronic circuit 20 comprises all the elements of the optoelectronic circuit 10 represented in FIG. figure 1 and further comprises a capacitor Cap and four diodes D _0A , D _0B , D _0C and D _0D . In the present embodiment, the anode of the diode D _0A is connected to the cathode of the global light-emitting diode D ₁ and the cathode of the diode D _0A is connected to a first armature of the capacitor Cap. The cathode of the diode D _0B is connected to the node A ₁ and the anode of the diode D _0B is connected to the first armature of the capacitor Cap. The cathode of the diode D _0C is connected to an input E _{N + 1} of the switching circuit 16 and the anode of the diode D _0C is connected to a second armature of the capacitor Cap. The anode of the diode D _0D is connected to the node A ₂ and the cathode of the diode D _0D is connected to the second armature of the capacitor Cap. The voltage V _CAP is the voltage between the first armature and the second armature of the capacitor Cap and the current I _CAP is the current flowing through the capacitor Cap. The switching circuit 16 comprises a conduction circuit, not shown, connecting the input E _{N + 1} to the node A ₃ and able to operate in K different conduction states, where K is an integer greater than or equal to 2. As a alternatively, the node E _{N + 1} is directly connected to the node A ₃ . The threshold voltages of the diodes D _0A , D _0B , D _0C and D _0D respectively are called V _THD0A , V _THD0B , V _THD0C and V _THD0D .

By way of example, the capacity of the Cap capacitor is between 100 nF and 100 μF. The threshold voltage of the diodes D _0A , D _0B , D _0C and D _0D is, for example, of the order of one volt, for example 0.7 V.

The figure 4 represents an operating diagram of the optoelectronic circuit 20 shown in FIG. figure 3 . The operation starts at block 21 which corresponds to the beginning of a cycle of variation of the voltage V _IN when the voltage V _IN is equal to 0 V.

In operation, when the absolute value of the voltage V _IN is greater than the sum of the voltages V _CAP and V _TH1 (test 22), the global light-emitting diode D ₁ is passing. and the capacitor Cap is charged (block 23) by the current flowing between the nodes A ₁ and A ₃ by successively passing through the global light emitting diode D ₁ , the diode D _0A , the capacitor Cap and the diode D _0C .

In operation, when the absolute value of the voltage V _IN is between the sum of the voltages V _CAP , V _THD0A and V _THD0C and the sum of the voltages V _CAP , V _THD0A and V _THD0C and V _TH1 (tests 22 and 24), the value of the rectified voltage V _RECT is imposed by the power source of the optoelectronic circuit 20 and is equal to the absolute value of the voltage V _IN minus the threshold voltages of the diodes of the rectifier bridge 12 (block 25). The number of global light-emitting diodes that can emit light then depends on the absolute value of the voltage V _IN . If the absolute value of the voltage V _IN is greater than the sum of the threshold voltages V _TH1 to V _THN (test 26), the global light-emitting diodes D ₁ to D _N can emit light (block 27). In general, if the absolute value of the voltage V _IN is greater than the sum of the threshold voltages V _TH1 to V _THi but less than the sum of the threshold voltages V _TH1 to V _{THi + 1} (tests 26 and 28), only the global light-emitting diodes D ₁ to D _i can emit light (block 29). Furthermore, if the absolute value of the voltage V _IN is only greater than the threshold voltage V _TH1 (test 30), only the light-emitting diode D ₁ can emit light (block 31). The selection of the number of global light-emitting diodes that will actually emit light from the global light-emitting diodes that can emit light is performed by the switching circuit 16. According to one embodiment, the switching circuit 16 selects the largest number of global light emitting diodes that can emit light.

In operation, when the absolute value of the voltage V _IN is lower than the voltage V _CAP minus the sum of the voltages V _THD0B and V _THD0D (test 24), the rectified voltage V _RECT is imposed by the capacitor Cap and is equal to voltage V _CAP minus the voltages across the diodes D _0B and D _0D (block 31). The current then circulates by successively passing through the diode D _0B , one or more global light emitting diodes, the circuit 14, the diode D _0D and the Cap capacitor. The number of light-emitting diodes that can emit light depends on the value of the voltage V _CAP minus the sum of the voltages V _THD0B and V _THD0D . If the voltage V _CAP minus the sum of the voltages V _THD0B and V _THD0D is greater than the sum of the threshold voltages V _TH1 to V _THN (test 32), the light-emitting diodes D ₁ to D _N can emit light (block 33). In general, if the voltage V _CAP minus the sum of the voltages V _THD0B and V _THD0D is greater than the sum of the threshold voltages V _TH1 to V _THi but less than the sum of the threshold voltages V _TH1 to V _{THi + 1} (test 34), only the light-emitting diodes D ₁ to D _i can emit light (block 35). In addition, if the voltage V _CAP minus the sum of the voltages V _THD0B and V _THD0D is only greater than the threshold voltage V _TH1 (test 36), only the light emitting diode D ₁ can emit light (block 37). The selection of the number of global light-emitting diodes that will actually emit light from the global light-emitting diodes that can emit light is performed by the switching circuit 16. According to one embodiment, the switching circuit 16 selects the largest number of global light emitting diodes that can emit light knowing that the Cap capacitor charge remains a priority.

The present embodiment makes it possible to limit the phase difference between the current supplied by the source 11 of the AC voltage V _IN and the voltage V _IN , thus to keep a high power factor, unlike an embodiment in which the capacitor Cap would be provided directly between the nodes A ₁ and A ₂ , which would phase the current supplied by the source 11 of the AC voltage V _IN and the voltage V _IN .

In the case where N is greater than or equal to 2, the fact that the optoelectronic circuit comprises the diodes overall electroluminescent D ₂ to D _N in series after the global light emitting diode D ₁ increases the light output of the optoelectronic circuit. Indeed, on the rising edge of V _ABS , between the moment when the global light-emitting diode D ₁ is supplied by the sector and the moment during which the Cap capacitor begins to be charged, the electric energy would be lost in the absence of the global light emitting diodes D ₂ to D _N. Similarly, electrical energy would be lost on a falling edge of V _ABS , between the moment when the Cap capacitor charge is terminated and the moment when the capacitor Cap discharges into the overall light emitting diode D ₁ in the absence of global light emitting diodes D ₂ to D _N.

The operation of the optoelectronic circuit 20 comprises an initialization phase during which the voltage V _CAP increases during successive cycles of variation of the voltage V _RECT until it stabilizes at an average value for which the charging and discharging of the capacitance Cap are equivalent.

The general operating principle of the optoelectronic circuit 20 shown in FIG. figure 3 described above will now be described in particular embodiments. In the embodiments which will be described later, I _{LED is} the current flowing through the global light emitting diode D ₁ and I _CAP the current flowing through the Cap capacitance.

The figure 5 is a figure similar to the figure 3 in the case where N is equal to 1 and the figure 6 is a chronogram of currents I _CAP and I _LED and voltages V _ABS , V _RECT and V _CAP of the optoelectronic circuit of the figure 5 . In figure 5 terminals IN ₁ and IN ₂ and source 11 are not shown. On the figure 6 , the threshold voltages of the diodes D _0A , D _0B , D _0C and D _0D are neglected. Each phase P _ch corresponds to a charging phase of capacitor Cap and each phase P _dech corresponds to a capacitor discharge phase Cap.

The Figures 7 and 8 are figures similar respectively to Figures 5 and 6 in the case where the number N of global light-emitting diodes is equal to 2 and in the case where only the cathode of the global light-emitting diode D ₂ is connected to the switching circuit 16.

The Figures 9 and 10 are figures similar respectively to Figures 5 and 6 in the case where the number N of global electroluminescent diodes is equal to 2 and in the case where the cathodes of the global light-emitting diodes D ₁ and D ₂ are connected to the switching circuit 16.

The fact that the diode D _0A is connected to the cathode of the global light emitting diode D ₁ and that the diode D _0C is connected to the node E _{N + 1} makes it possible to apply to the capacitor Cap a maximum charge voltage as close as possible to V _RECT reduced only by the threshold voltage of the global light emitting diode D ₁ and the threshold voltages of the diodes D _0A and D _0C and dependent on the current imposed by the current regulating / limiting circuit 14.

According to another embodiment, the charging and discharging currents of the capacitor Cap are different, in order to modify the charging and discharging times of the Cap capacitor and thus to optimize the electrical efficiency and / or the flashing performance of the optoelectronic circuit. .

The figure 11 is a figure similar to the figure 5 with the difference that the diodes D _0A and D _0B are not present, that the switching circuit 16 comprises the current source 14 which is connected to the global light-emitting diode D ₁ and that the switching circuit 16 further comprises an additional current source 38 connected to the cathode of the diode D _0C . This embodiment advantageously makes it possible for the charging current of the capacitor Cap to be different from the discharge current of the capacitor Cap.

The figure 12 is a figure similar to the figure 3 with the difference that the anode of the diode D _0A is connected to the cathode of the global light-emitting diode D _i . This can be advantageous in the case where the voltage V _RECT does not correspond to a rectified sinusoidal voltage but corresponds, for example, to the voltage supplied by a dimmer, in particular a timed closing dimmer and a timed opening dimmer. In this case, the voltage across the capacitance Cap is less important. The Cap capacitance may no longer be able to discharge into the first group of light emitting diodes. Subdivision this first group into several with lower threshold voltages allows the device to remain lit even for a low V _CAP value.

The figure 13 is a figure similar to the figure 9 with the difference that the diodes D _0A and diode D _0B are not present and that the capacitor electrode Cap which, in figure 9 , is connected to the cathode of the diode D _0A and to the anode of the diode D _0B , is in figure 13 connected to the cathode of the global light emitting diode D ₁ . This embodiment advantageously makes it possible to dispense with two diodes with respect to the embodiment represented in FIG. figure 1 .

The figure 14 represents a more detailed embodiment of certain elements of the optoelectronic circuit 20 shown in FIG. figure 3 and which is described in the French patent application FR 15/59617 not yet published.

In this embodiment, the switching circuit 16 comprises N + 1 conduction circuits SW ₁ to SW _{N + 1} . Each conduction circuit SW _i , i ranging from 1 to N, is mounted between the node A ₃ and the cathode of the global light emitting diode D _i . The conduction circuit SW _{N + 1} is mounted between the node A ₃ and the cathode of the diode D _0C .

Each circuit SW _i , i varying from 1 to N + 1, is controlled by a signal S _i supplied by a control module 40. For i varying from 1 to N + 1, the current flowing in the circuit SW is called _{i i i} . Alternatively, the circuit SW _{N + 1} , which protects the current source 30 from overvoltages, may not be controlled by the control module and may still be on or may not be present and the cathode of the diode D _0C can be connected directly to the node A ₃ . The control module 16 may, in whole or in part, be realized by a dedicated circuit or may comprise a microprocessor or a microcontroller adapted to execute a sequence of instructions stored in a memory.

According to one embodiment, each circuit SW _i can operate in K different conduction states, where K is an integer greater than or equal to 2. A conduction state is a state in which the circuit does not let the current pass or passes the current with a resistance that may be different depending on the state considered. Among the K conduction states of the circuit SW _i , there is a state in which the circuit SW _i is the least electrically conductive, for example a state in which the circuit SW _i prevents the passage of current and a state in which the circuit SW _i is the most electrically conductive. When K is equal to 2, the circuit SW _i is, for example, a switch which is either open or closed. The signal S _i can then be a binary signal and the switch SW _i is open when the signal S _i is at a first level, for example S _{i, 1} or "0", and the switch SW _i is closed when the signal S _i is at a second level, for example S _{i, 2} or "1". By way of example, when K is greater than or equal to 3, the circuit SW _i can operate in a state in which it prevents the passage of current and in at least two states in which the circuit SW _i allows the passage of current with different resistances according to the signal S _i . The signal S _i can then be a signal that can take several discrete values S _{i, 1} to S _{i, K} , each value of the signal S _i controlling one of the states of the switch SW _i . By way of example, the state of the circuit SW _i associated with the signal S _{i, 1} corresponds to the off state in which the circuit SW _i prevents the current flow and the states of the circuit SW _i respectively associated with the signals S _{i , 2} to S _{i, K} correspond to the states in which the circuit SW _i has a lower and lower resistance. As a variant, different values of the signal S _i can control the same conduction state of the circuit SW _i .

The optoelectronic circuit 20 comprises a first comparator 42, for example an operational amplifier mounted as a comparator, providing a DOWN signal to the control module 40, whose non-inverting input (+) is connected to the node A ₃ and whose inverting input (-) receives a voltage threshold V _DOWN supplied by a circuit 43. According to one embodiment, the comparator 42 provides the DOWN signal in two states. The signal DOWN is set to the first state, for example "0", when the voltage V _CS is lower than the voltage threshold V _DOWN . The signal DOWN is set to the second state, for example "1", when the voltage V _CS is greater than the voltage threshold V _DOWN .

The optoelectronic circuit 20 comprises a second comparator 44, for example an operational amplifier mounted as a comparator, supplying a signal UP to the control module 40, whose inverting input (-) is connected to the node A ₃ and whose non-inverting input (+) receives a voltage threshold V _UP supplied by a circuit 45. According to one embodiment, the comparator 44 provides the signal UP in two states. The signal UP is set to the first state, for example "0", when the voltage V _CS is greater than the voltage threshold V _UP . The signal UP is set to the second state, for example "1", when the voltage V _CS is lower than the voltage threshold V _UP , the voltage V _UP being lower than the voltage V _DOWN .

According to one embodiment, each circuit SW _i is, for example, based on at least one transistor, in particular a metal oxide oxide or MOS transistor field effect transistor, enriched or depleted.

According to one embodiment, each conduction circuit SW _i corresponds to a MOS transistor, for example an N-channel transistor, the drain of which is connected to the cathode of the global light-emitting diode D _i for the conduction circuits SW ₁ to SW _N and at the cathode of the diode D _0C for the conduction circuit SW _{N + 1} , the source of which is connected to the node A ₃ and whose gate receives the signal S _i . When the signal S _i is binary, it can take two values S _{i, 1} (or "0") and S _{i, 2} (or "1"). The transistor SW _i can operate in two states, an on state and a locked state, the passing state being for example obtained for the value "1", and the off state being for example obtained for the value "0". When the signal S _i can take more than two values, the transistor SW _i can operate in more than two states including a locked state and at least two different conduction states. According to another embodiment, the conduction circuit SW _i comprises two MOS transistors, for example N-channel between the cathode of the overall light-emitting diode D _i (or the diode D _0C) and node _A3, the connected transistor the global light emitting diode D _i (or diode D _0C ) being a high voltage transistor mounted in cascode and the transistor connected to the node A ₃ being a low voltage transistor controlled by the signal S _i . This advantageously makes it possible to increase the switching speed of the conduction circuit SW _i .

The figure 15 represents, in the form of an operating diagram, an embodiment of a method for controlling the conduction circuits SW _i by the control module 40. The method starts in step 50.

Step 50 corresponds to an initialization step, for example at the start of the optoelectronic circuit 20, that is to say when the optoelectronic circuit 20 is turned on. By way of example, in step 50, the control module 40 provides the signals S _i in the state S _{i, 1} , that is to say that all the conduction circuits SW _i are in the state where their resistance is the strongest. When the conduction circuits SW _i are switches, all the switches SW _i are open in step 50. The method continues in step 52.

In step 52, the control module 40 maintains the supply of the signals S _i to the last determined value as long as the control module 40 receives the signals DOWN and UP at "0". At the initialization step, no current flowing in the global light emitting diodes D ₁ to D _N , the voltage V _CS is naturally pulled towards 0 V, and is therefore lower than the voltage V _UP , so that the signal UP goes to "1".

In step 54, the control module 40 receives a signal UP at "1". This means that the voltage V _CS has decreased below V _UP . The process continues at step 56.

In step 56, the control module 40 modifies the values of the signals S _i so as to increase the voltage V _CS . According to one embodiment, when each conduction circuit SW _i corresponds to a switch, when the switches SW ₁ to SW _i-1 are open and the switches SW _i to SW _{N + 1} are closed, an increase in the voltage V _CS can be obtained by closing the switch SW _i-1 . According to another embodiment, when each conduction circuit SW _i has several conduction states, that the conduction circuits SW ₁ to SW _i-1 are in the off state, that the conduction circuits SW _{i + 1} at SW _{N + 1} are in the most conductive conduction state and that the conduction circuit SW _i is in one of the passing states, an increase of the voltage V _CS can be obtained, in the case where the state conduction circuit SW _i is not the most passing state, by changing the conduction state of the conduction circuit SW _i to increase the conduction thereof, or, if the conduction state of the circuit SW _i is the the most happening state, by changing the state of the circuit SW _i-1 to put it in its conduction least conductive state.

In step 58, the control module 40 receives a DOWN signal at "1". This means that the V _CS voltage has increased above V _DOWN . The process continues in step 60.

In step 60, the control module 40 modifies the values of the signals S _i so as to decrease the voltage V _CS . According to one embodiment, when each conduction circuit SW _i corresponds to a switch, that the switches SW ₁ to SW _i-1 are open and that the switches SW _i to SW _{N + 1} are closed, a decrease in the voltage V _CS can be obtained by opening the switch SW _i . According to another embodiment, when each conduction circuit SW _i is more than two conduction states, that the conduction circuits SW ₁ to SW _i-1 are in the off state, that the conduction circuits SW _{i +1} to SW _{N + 1} are in the most conductive conduction state and that the circuit of conduction SW _i is in one of the passing states, a decrease of the voltage V _CS can be obtained by changing the conduction state of the conduction circuit SW _i to reduce the conduction. If the conduction circuit SW _i is in the off state, the state of the conduction circuit SW _{i + 1} is modified to make the latter less conductive. The process then continues at step 52.

Thus, a regulation of the voltage V _CS is obtained which remains between the voltage thresholds V _UP and V _DOWN regardless of the variations of V _RECT .

An embodiment of the control method of the optoelectronic circuit 20 will now be described in the case where the conduction circuits SW _i correspond to switches. At the beginning of an ascending phase of the voltage V _RECT , that is to say, in the case where the voltage V _RECT is obtained from a sinusoidal V _IN voltage, when V _RECT increases from 0 V, the Switches SW _i , i ranging from 1 to N, are closed, that is to say, passers electrically.

In an ascending phase of the supply voltage V _RECT , for i varying from 1 to N, while the global light emitting diodes D ₁ to D _i-1 are on and the global light emitting diodes D _i to D _N are off, when the voltage across the global light-emitting diode D _i becomes greater than the threshold voltage of the global light emitting diode D _i , it becomes conductive and a current begins to flow in the global light emitting diode D _i . This causes an increase in the voltage V _CS . If the latter goes beyond the voltage threshold V _DOWN , the module 40 then controls the opening of the lower index switch among the closed switches.

At the beginning of a downward phase of the supply voltage V _RECT , that is to say, in the case where the voltage V _RECT is obtained from a sinusoidal V _IN voltage, when V _RECT decreases from a maximum positive value, greater than the sum of the threshold voltages of the light-emitting diodes D ₁ at D _N , the switches SW _i , i varying from 1 to N, are open. In a downward phase, the global light-emitting diodes D ₁ to D _i being conducting and the global light-emitting diodes D _{i + 1} to D _N being blocked, when the voltage V _CS decreases below the voltage V _UP , this means that the voltage at the terminals of the current source 30 may become too weak for it to function properly and deliver its rated current. This therefore means that it is necessary to reduce the number of diodes in conduction to increase the voltage across the current source 30. The module 40 then controls the closing of the switch of the strongest index among the open switches. In the case where each switch SW _i is produced by an N-channel MOS transistor whose drain is connected to the cathode of the global light-emitting diode D _i and whose source is connected to the node A ₃ , when the supply voltage V _RECT drops, the voltage between the drain of the switch SW _i and the node A ₃ decreases until the operation of the transistor SW _i goes from the saturation regime to the linear regime. This causes an increase in the voltage between the gate and the source of the transistor SW _i and therefore a decrease in the voltage V _CS .

Advantageously, the embodiment of the switch control method SW _i described above does not depend on the number of elementary light-emitting diodes that make up each global light-emitting diode D _i and therefore does not depend on the threshold voltage of each global light-emitting diode. .

An embodiment of the control method of the optoelectronic circuit will now be described in the case where each conduction circuit SW _i has a number of conduction states greater than or equal to 3. At the beginning of an ascending phase of the voltage V _RECT , that is to say, in the case where the voltage V _RECT is obtained from a sinusoidal voltage V _IN , when V _RECT increases from 0 V, the conduction circuits SW _i , i varying from 1 to N + 1 are in the most conductive conduction state. In ascending phase of the supply voltage V _RECT , for i ranging from 1 to N, while the global light emitting diodes D ₁ to D _i-1 are on and the global light emitting diodes D _i to D _N are blocked, when the The voltage at the terminals of the global light-emitting diode D _i becomes greater than the threshold voltage of the global light-emitting diode D _i , it becomes conductive and a current begins to flow in the global light-emitting diode D _i . This causes an increase in the voltage V _CS . If the latter passes beyond the voltage threshold V _DOWN , the module 40 then controls the passage of the conduction circuit of the lowest index among the conduction circuits passing to a state of less and less passing each time the voltage V _CS increases beyond the voltage V _DOWN until it reaches the off state.

At the beginning of a downward phase of the supply voltage V _RECT , that is to say, in the case where the voltage V _RECT is obtained from a sinusoidal V _IN voltage, when V _RECT decreases from a maximum positive value, greater than the sum of the threshold voltages of the light-emitting diodes D ₁ to D _N , the conduction circuits SW _i , i ranging from 1 to N-1, are in the off state. In a downward phase, the global light-emitting diodes D ₁ to D _i-1 being conducting and the global light-emitting diodes D _i to D _N being blocked, when the voltage V _CS decreases below the voltage threshold V _UP , the module 40 controls then the passage of the strongest index conduction circuit among the conduction circuits which are not in the most passing state to a state of increasing passing each time that the voltage V _CS decreases below the threshold voltage V _UP until reaching the most conductive conduction state.

The figure 16 represents a more detailed embodiment of the control module 40 in the case where the number of conduction states K of each conduction circuit SW _i is greater than or equal to 3. In the present embodiment, the module of control 40 comprises a state finite number machine (FSM), also called finite state machine, at K * (N + 1) states receiving the DOWN and UP signals and providing a digital signal Q _i for each conduction circuit SW _i . For example, the state machine 70 can operate on UP and DOWN edges. Each value of the digital signal Q _i codes for one of the K states of the conduction circuit SW _i . The control module 40 furthermore comprises a decoder 72 _i (decoder) for each conduction circuit SW _i , i varying from 1 to (N + 1), each decoder 72 _i receiving the digital signal Q _i and supplying a signal digital Q ' _i . The control module 40 furthermore comprises a digital-to-analog converter 74 _i (DAC) for each conduction circuit SW _i , i varying from 1 to N + 1, for example of the PWM type or a network which subdivides a voltage into several intermediate voltages, each digital-to-analog converter 74 _i receiving the digital signal Q ' _i and supplying the signal S _i . The decoder 72 _i is used to provide a digital signal Q _'i suitable for operation of the converter 74 digital _i / associated analog. The number of bits of the digital signals Q _i and Q ' _i depends on the type of coding used and on the accuracy of the digital-to-analog converter 74 _i .

In the case where the number of conduction states K is equal to 2, the embodiment of the control module 40 represented in FIG. figure 16 can be simplified, the control module 40 may not include the decoders 72 _i and the digital to analog converter 74 _i can be replaced by a level adjustment circuit.

According to one embodiment, the state machine 70 uses a counter COMPT comprising (N + 1) * (K-1) bits and equal to the concatenation of the signals Q ₁ to Q _{N + 1} and each digital signal Q _i comprises K-1) bits. At the initialization of the optoelectronic circuit, all the bits of the counter are set to "0". In operation, the state machine 70 increments the counter COMPT upon receipt of a signal UP at "1"; if all the bits are set to "1", the counter remains in its state. The finished automaton 70 decrement the counter COMPT upon receipt of a DOWN signal at "1"; if all the bits are set to "0", the counter remains in its state.

Advantageously, the maximum voltages applied to the electronic components, in particular the MOS transistors, comparators 42, 40 remain small compared to the maximum value that can take the voltage V _RECT . It is then not necessary to provide, for the comparators 42, 40, electronic components that can withstand the maximum value that can take the voltage V _RECT .

According to another embodiment, as soon as the voltage at the drain of the switch SW _N becomes insufficient to pass the maximum current in the global light-emitting diode D _N , the switch SW _N is in its most moving state, the node A ₃ has the same potential as the node A ₂ and no current flows. Detection of this state, which is the most current of the switch SW _N, makes it possible to carry out a filtered feedback (for example of the low-pass type) on the value of the current flowing in the global light-emitting diode D _N until the switch SW _{N is} no longer in its most conducting state for an entire period of the voltage V _RECT and therefore that the node A _{3 is} no longer at the potential A ₂ and the current source 14 operates. The current in the global light emitting diodes will reach the value for which the global light emitting diodes will be constantly lit throughout a period of V _RECT . There is therefore a regulation of the current in the global light emitting diodes as a function of the voltage V _RECT .

The figure 17 represents a circuit diagram of another embodiment of an optoelectronic circuit 75 comprising all the elements of the optoelectronic circuit 20 with the exception of the comparator 44 and the circuit 45 for supplying the voltage threshold V _UP, which are not present. The optoelectronic circuit 75 further comprises an inverter 76 receiving the signal DOWN and supplying the control module 40 with the signal DOWNb which is complementary to the DOWN signal. The signal DOWNb is equivalent to the signal UP described above for the optoelectronic circuit 20 and can be supplied to the input of the control module 40 which, for the optoelectronic circuit 20, receives the signal UP. The control module 40 may have the structure described above in relation to the figure 16 . In particular, the control module 40 may comprise a state machine 70 operating as has been previously described in connection with the figure 16 . Alternatively, the comparator 42 may be a hysteresis comparator. According to another embodiment, the comparator 42 of the optoelectronic circuit 75 is replaced by a Schmitt flip-flop, having two intrinsic threshold voltages V _L and V _H , receiving the voltage V _CS and supplying the signal DOWN. By way of example, when the voltage V _CS increases from 0 V, the signal DOWN remains in the "0" state until the voltage V _CS exceeds the voltage threshold V _H. At this time, the signal DOWN goes to state "1". The signal DOWN remains in the state "1" until the voltage V _CS becomes lower than the voltage threshold V _L. At this moment, the signal DOWN goes to the state "0". The signal DOWN remains in the "0" state until the voltage V _CS goes back above the voltage threshold V _H.

To modify the light output provided by the lighting circuit, it is known to place a dimmer between the source of the rectified voltage and the optoelectronic circuit. There are several types of dimmers, including timed-close dimmers and timed-open dimmers.

The figure 18 is a view similar to the figure 3 an embodiment of an optoelectronic circuit 80 in which a dimmer 82 is arranged in series with the source 11 between the terminals IN ₁ and IN ₂ . The dimmer 82 may be a phase-cut dimmer comprising an electronic switch whose conduction time is limited to a fraction of the period T of the voltage V _IN .

A disadvantage is that the dimmers have generally been designed to operate with incandescent lamp lighting circuits and may not function properly when connected to a light emitting diode optoelectronic circuit, since their power is often too low in comparison with light emitting diodes. at the minimum power required by the dimmer.

The Figures 19 and 20 each represent an example of evolution curves of currents I _LED and I _CAP and voltages V _ABS , V _RECT and V _CAP when the AC voltage V _IN is sinusoidal of period T and when the dimmer 82 is a delayed closing dimmer ( in English leading edge dimmer). The voltage V _ABS follows the signal that would be obtained in the absence of a dimmer except for a duration T 'at the beginning of each sinusoidal arc during which the voltage V _ABS is substantially zero. For a trailing edge dimmer, the voltage V _ABS follows the signal that would be obtained in the absence of a dimmer except for a time at the end of each sinusoidal arc during which the voltage V _ABS is substantially zero. The ratio between the duration T 'and the half-period T of the non-rectified sinusoidal signal is called the opening angle of the dimmer.

To be sure that there is no extinction of the global light emitting diode D ₁ , it is necessary that the Cap capacitor charge is always greater than the threshold voltage V _TH1 . If the voltage is chopped by the dimmer 82, the capacitor Cap has less time to recharge while the discharge time in the global light emitting diode D ₁ is elongated.

The figure 19 represents a configuration in which the current flowing in the light-emitting diode D ₁ is not modified by the presence of the dimmer 82 while the figure 20 represents a configuration with a larger opening angle in which the current flowing in the light-emitting diode D ₁ decreases due to the presence of the dimmer 82.

• premièrement, il faut assurer un niveau de variation de luminosité au cours d'une période de V_RECT tolérable ; et
• deuxièmement, il faut assurer le fonctionnement du gradateur 82 en imposant une impédance à ses bornes similaire à celle pour laquelle il a été conçu, c'est-à-dire une impédance en générale faible.

There are two points to take into account to allow the use of a dimmer 82 while maintaining a level of flicker / flicker tolerable:

• firstly, it is necessary to ensure a level of brightness variation during a tolerable V _RECT period; and
• secondly, it is necessary to ensure the operation of the dimmer 82 by imposing an impedance at its terminals similar to that for which it was designed, that is to say an impedance generally low.

For the first point, to be sure that there is no extinction of the global light emitting diode D ₁ , it is necessary that the Cap capacitor charge is always greater than the threshold voltage V _TH1 . Or if the voltage V _IN of the sector is chopped by the dimmer 82, Cap capacitor has less time to recharge while the discharge time in the global light emitting diode D ₁ is elongated. In order to maintain an acceptable level of charge and to avoid the brightness variation by extinction of the global light emitting diode D ₁ , one embodiment provides for modulating, in particular decreasing, the charging and discharging currents in the capacitor Cap so that the average voltage at cap capacitor terminals is always sufficient to maintain at least the global light emitting diode D ₁ on and thus limit the brightness variations during a period of V _RECT .

For the second point, the problem arises when the voltage V _RECT is lower than the voltage V _CAP , because the current in the light-emitting diodes is drawn on the capacitor Cap and not on the source 11. An embodiment provides for adding a device for detecting whether the current is pulled on the sector and compensate for its absence or its low value by an additional current.

The Figures 21 and 22 represent embodiments of optoelectronic circuits 90 and 100 adapted to the use of a dimmer 82. The optoelectronic circuit 90 comprises all the elements of the optoelectronic circuit 20 represented in figure 3 while the optoelectronic circuit 100 comprises all the elements of the optoelectronic circuit 20 shown in FIG. figure 11 . Each circuit 90 and 100 further comprises a diode D 'whose cathode is connected to the node A ₁ and whose anode is connected to a node A ₄ connected to an output terminal of the rectifier bridge 12. A ₅ a node connected to the other output terminal of the rectifier bridge 12. Each opto-electronic circuit 90 and 100 further comprises a module 92 (for dimmer boot block) for initiating operation of the controller 82. the module 92 is connected in parallel with the rectifier bridge 12, between the node A ₄ and the node A ₅ . The potential at the node A ₅ can correspond to the low reference potential of the rectifier bridge 12. The module 92 is, in addition, connected to the anode of the diode D _0D .

In the present embodiment, the current source 14 is a current source controllable by a signal V _DIM . By way of example, the intensity of the current supplied by the current source 14 is proportional to the signal V _DIM . According to one embodiment, the signal V _DIM is a voltage which is obtained from the voltage V _RECT , measured between the nodes A ₄ and A ₅ . According to one embodiment, each circuit 90 and 100 comprises a threshold detection module 94 which receives the voltage V _RECT and which is adapted to provide a pulse width modulated PWM binary signal whose frequency corresponds to the frequency of the signal V _RECT and whose duty cycle is determined by comparing the voltage V _RECT to at least one threshold. The circuit 90 further comprises a modulator 95 with a reference voltage V _REF receiving the PWM signal and providing a modulated signal PWM 'a filter 96 receiving the modulated signal PWM' and providing the filtered signal V _DIM . The modulator 95 makes it possible to adapt the average value of the signal V _DIM as a function of the voltage V _REF and the duty cycle of the PWM signal.

The figure 23 represents a timing diagram of the voltage V _RECT and the voltage PWM in the case where the module 94 compares the voltage V _RECT with a single threshold V _TH . The PWM signal is at '1' when the voltage V _RECT is greater than or equal to the threshold V _TH and the PWM signal is at '0' when the voltage V _RECT is strictly lower than the threshold V _TH .

The figure 24 represents an embodiment of the module 94 making it possible to obtain the chronogram represented in figure 23 . The module 94 comprises an N-channel MOS transistor M0 whose drain receives the voltage V _RECT , the source of which is connected to a terminal of a resistor R _A and whose gate is connected to the other terminal of the resistor R _A . Two Zener diodes D _Z0 and D _Z1 are connected in series between the resistor R _A and a current mirror, the cathodes of the diodes D _Z0 and D _Z1 being oriented _towards the resistor R _A. The current mirror comprises two N-channel MOS M _1A and M _1B transistors. The transistor M _1A is diode-mounted. The sources of transistors M _1A and M _1B are connected to node A ₂ . The drain of the transistor M _1A is connected to the gates of the transistors M _1A and M _1B and to the anode of the Zener diode _Z0 . The drain of the transistor M _1B provides the PWM signal _B , which is complementary to the PWM signal, and is connected to a source of a high reference potential VCC by a resistor R _A. The high reference potential VCC can be obtained from the voltage V _RECT . Called V _dz0 the voltage between the cathode and the anode of the Zener diode D _{Z 0,} V _DZ1 voltage between the cathode and the anode of the Zener diode D _Z1, and V _THM1 the threshold voltage of the transistors M _1A and M _1B .

The transistor M ₀ is a depleted transistor, that is to say with a threshold voltage V _T negative. When the voltage V _RECT is strictly greater than the sum of voltages V _dz0, V _DZ1 and _THM1 V, a current flows in the transistor M _1A and is copied in transistor M _1B. The PWM signal _B is then in the low state, pulled at the low reference potential by the transistor M _1B . If the voltage V _RECT is strictly less than the sum of voltages V _dz0, V and V _{THM1 DZ1,} no current flows in transistor M _1B. The PWM signal _B is then in the high state, drawn to the high reference potential V _CC by the resistor R _B. The threshold voltage V _TH of the module 94 is determined by the threshold voltages of the Zener diodes D _Z0 and D _Z1 and the threshold voltage V _THM1 of the transistor M _1A .

In another example, the module 94 compares the voltage V _RECT with two thresholds according to a hysteresis cycle.

The figure 25 represents a timing diagram of the voltage V _DIM and the voltage PWM.

The figure 26 is a circuit diagram of an embodiment of the modulation module 95 in which the voltage V _REF corresponds to the high reference potential VCC and the integration module 96 making it possible to obtain the signals of the chronogram represented in FIG. figure 25 . In this embodiment, the voltages V _DIM and PWM 'are merged.

According to one embodiment, the modulation modules 95 and integration modules 96 comprise a resistor R ₁ and a switch T ₁ in series between the source of the high reference potential V _CC and a node B. The switch T ₁ is controlled by the PWM signal. The modulation modules 95 and integration modules 96 further comprise a resistor R ₂ and a switch T ₂ in series between the node B and the node A ₂ . The switch T ₂ is controlled by the PWM signal _B. The integration module 96 further comprises a capacitor C _INTEG mounted between the node B and the node A ₂ . The voltage V _DIM corresponds to the voltage across the capacitor C _INTEG .

The ratio between the resistors R ₁ and R ₂ makes it possible to adjust the modulation ratio and therefore the average value of the modulated and filtered V _DIM signal.

The figure 27 is a circuit diagram of an embodiment of the module 92. The module 92 comprises a MOS transistor T, for example N-channel, whose source is connected to the node A ₂ and whose drain is connected to the node A ₄ . The module 92 further comprises a capacitor C _COMP and a resistor R _COMP in parallel arranged between the node A ₂ and the node A ₅ . The module 92 further comprises a differential amplifier 98 whose non-inverting input (+) is connected to the node A ₅ , whose inverting input (-) is connected to the node A ₂ and whose output controls the gate of the transistor T. The V _offset voltage is the voltage between the inputs (+) and (-) of the amplifier 98. The current I _COMP is the current at the drain of the transistor T.

The module 92 makes it possible to draw a minimum current on the mains by placing a resistor R _COMP between the ground of the switching circuit 16 (potential GNDA at the node A ₂ ) and the ground of the rectifier bridge 12 (potential GND at the node A ₅ ). Thus, if no current is drawn on the sector by the switching circuit 16, a current I _COMP of value Voffset / R _COMP is drawn on the sector. A current peak I _COMP makes it possible to prime the dimmer 82 by charging the capacitor C _COMP at the beginning of the rising edge to the voltage V _RECT . A constant current I _COMP in the resistor R _COMP makes it possible to maintain the state of the dimmer by pulling a holding current I _COMP , adjustable thanks to the resistor R _COMP . When the mains supplies the light-emitting diodes, a current at least equal to V _offset / R _COMP is drawn on the mains.

Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. Although detailed embodiments have been described comprising a single Cap capacitor, one or more additional capacitors may be provided. For example, an additional capacitor may be added in parallel with a set of successive global light emitting diodes. Furthermore, although detailed embodiments have been described in which the least electrically conductive conduction state of each conduction circuit SW _i corresponds to a non-conducting state, it is clear that these embodiments can also be implemented. implemented with a conduction circuit SW _i for which the least electrically conductive state nevertheless corresponds to a state in which current flows through the circuit SW _i , for example a current whose intensity is less than or equal to the limit theoretical which is the maximum intensity inducing a power in the conduction circuit SW _i can be dissipated without causing malfunction thereof. Furthermore, although in the embodiments described above, the switches SW ₁ to SW _N are connected to a As the sole source of current, it is clear that several sources of current can be provided. For example, a current source can be provided by switch SW _i or a current source can be provided by switch pair SW _i , etc.

Claims (10)

1. An optoelectronic circuit (20) intended to receive, between a first node (A₁, A₄) and a second node (A₂, A₅), a variable voltage (V_RECT) containing an alternation of increasing positive phases and of decreasing positive phases, the optoelectronic circuit comprising:

   a plurality of light-emitting diodes (D_i) mounted in series between the first node and a third node;

   a first circuit for limiting/regulating (14) the current mounted between the third node and the second node;

   a switching circuit (16) linking the third node to at least some light-emitting diodes of the plurality of light-emitting diodes;

   a capacitor (Cap) comprising first and second plates;

   and characterized in that the optoelectronic circuit comprises:

   a first diode (D_0D) whose cathode is connected to the second plate and whose anode is linked to the second node;

   a second diode (Doc) whose anode is connected to the second plate and whose cathode is linked to the third node;

   a third diode (D_0A) whose anode is connected to one of the light-emitting diodes and whose cathode is connected to the first plate; and

   a fourth diode (D_0B) whose anode is connected to the first plate and whose cathode is linked to the first node.
2. The optoelectronic circuit according to claim 1, wherein the plurality of light-emitting diodes (D_i) mounted in series comprises a first light-emitting diode (D_i) whose anode is connected to the first node (A₁), the anode of the third diode (D_0A) being connected to the cathode of the first light-emitting diode.
3. The optoelectronic circuit according to claim 1 or 2, wherein the switching circuit (16) comprises, for each light-emitting diode (D_i) among the light-emitting diodes linked to the switching circuit (16), a circuit for conducting (SW_i) the current linking the third node (A3) to the cathode of the light-emitting diode and adapted to assume at least first and second states, the conduction circuit in the first state being less electrically conductive than in the second state.
4. The optoelectronic circuit according to claim 3, wherein the switching circuit (16) further comprises a conduction circuit (SW_i) of the current linking the third node (A3) to the cathode of the second diode (Doc).
5. The optoelectronic circuit according to any one of claims 1 to 4, wherein the first circuit for limiting/regulating (14) the current comprises a first current source adapted to provide a current whose intensity depends on a setpoint (V_DIM).
6. The optoelectronic circuit according to claim 5, comprising a first circuit (94) adapted to receive said variable voltage (V_RECT) and to provide a pulse width modulated (PWM) binary signal.
7. The optoelectronic circuit according to claim 6, comprising a modulation and filtering circuit (95, 96) adapted to receive the binary signal (PWM) and to provide the setpoint (V_DIM) whose average value depends on the duty cycle of the binary signal.
8. The optoelectronic circuit according to any one of claims 1 to 7, further comprising a device (92) for reducing the impedance viewed between the first node (A₄) and the second node (A₅).
9. The optoelectronic circuit according to claim 8, wherein the impedance reduction device (92) comprises a second circuit for limiting/regulating (R_COMP, C_COMP) the current and a transistor (T) in series with the third circuit for limiting/regulating the current.
10. The optoelectronic circuit according to claim 9, wherein the impedance reduction device (92) comprises a module (98) adapted to control the transistor (T) from the voltage across the second circuit for limiting/regulating the current (R_COMP, C_COMP).

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