EP2676373A1

EP2676373A1 - Turbo decoder with qpp or arp interleaver

Info

Publication number: EP2676373A1
Application number: EP12707938.2A
Authority: EP
Inventors: Tomoyoshi Kobori; Steffen Kunze; Emil Matus; Gerhard Fettweis
Original assignee: Technische Universitaet Dresden; NEC Corp
Current assignee: Technische Universitaet Dresden; NEC Corp
Priority date: 2011-02-18
Filing date: 2012-02-15
Publication date: 2013-12-25
Also published as: JP2014506022A; WO2012111846A1

Abstract

An interleave address generating circuit of a multicore type turbo decode processing apparatus of the present invention includes intermediate value generating blocks whose arithmetic portions are modified so as to generate not only an interleave address corresponding to the forward direction but also an interleave address corresponding to the backward direction. By using initial parameters which are preliminarily decomposed into parameters for a memory bank and physical addresses, the intermediate value generating blocks having a restricted bit width in two parallel are disposed in two parallel and the two intermediate value generating blocks are connected to each other through signal lines for exchanging carry signals.

Description

DESCRIPTION

TURBO DECODER WITH QPP OR ARP INTERLEAVER

Technical Field:

The present invention relates to a field of error correction processing using a multicore processor in wireless communication, and more particularly to technology of turbo decoding.

Background Art:

A high throughput and a high resistance to error have been required for recent wireless communication systems. In order to meet such demands, various techniques including error correction processes such as turbo coding, LDPC (Low Density Parity Check) coding, and convolutional coding have been used in a variety of wireless communication systems, such as LTE (Long Term Evolution) and WiMax (Worldwide Interoperability for Microwave Access). In order to achieve high throughput required, the error correction processing in the next generation of communications standards of the LTE and the WiMax, particularly turbo decoding, has an advantage that this has interleaving processing different from that in the third-generation communications such as WCDMA (Wideband Code Division Multiple Access).

The interleaving processing in the LTE and WiMax is referred to as an ARP (Almost Regular Permutation) interleaver and a QPP (Quadratic Permutation Polynomial) interleaver, respectively. These interleavers have a characteristic where addressing becomes possible with no conflict of memories although a plurality of interleave addresses are simultaneously generated using interleave address generators which are arranged in parallel.

It is therefore possible to perform the turbo decode processing in parallel as shown in Fig. 7, by dividing a code length of a data string into a plurality of windows and it is possible to benefit from high speed by the number of the windows.

Fig. 7 is a view showing a parallel processing method of the turbo decode processing related to this invention. A code number N of the data string is divided into m windows (a first window #0, a second window #1, and an m-th window #m-l). Each of the first through the m-th windows #0 to #m-l is divided into p sub- windows (a first sub- window #0 to a p-th sub- window). At each of the first through the m-th windows #0 to #m-l, forward computation (a computation) is performed toward the p-th sub-window #p-l from the first sub-window #0. In addition, at each of the first sub-window #0 to the p-th sub-window #p-l, backward computation (β computation) is performed. Specifically, in a case of a QPP interleave method, an interleave address is computed in adherence to Equation 1 as follows:

f_(x) = (f2x² + fix) mod N, (0 < x, fl , f2 < N),

where fl, f2 represent coefficients determined by the code length N.

In addition, in a case of an ARP interleave method, an interleave address is computed in adherence to Equation 2 as follows:

f_(x) = (POx + Qx) mod N, as x mod 4 = 0, 1 , 2, 3,

Q_x = 1, 1+N/2+P1, 1+P2, 1+N/2+P3,

where P0, PI, P2, and P3 represent coefficients determined by the code length N.

By using this interleave method, parallelism of the turbo decode processing is allowed and it is possible to realize high throughput by a multicore type turbo decode processing apparatus 40 as shown in Fig. 8.

Fig. 8 is a block diagram showing the multicore type turbo decode processing apparatus 40 related to this invention. The illustrated multicore type turbo decode processing apparatus 40 comprises fist through n-th memory bank sections 41-1, 41-2, and 41-n (n represents an integer which is not less than two), an interconnect section 42, first through n-th turbo decode processing sections 43-1, 43-2, and 43-n, and an address generating section 44, where a bank number n is not more than the above-mentioned window number m (n < m).

The first through the n-th memory bank sections 41-1 to 41-n are used for storing turbo decode target data (hereinafter, which is called "input data") and decoded results. The interconnect section 42 is connected to the first through the n-th memory bank sections 41-1 to 41-n and the first through the n-th turbo decode processing sections 43-1 to 43-n. By switching internal connection configuration in the interconnect section 42, connection configuration between the first through the n-th memory bank sections 41-1 to 41-n and the first through the n- th turbo decode processing sections 43-1 to 43-n is controlled. The first through the n-th turbo decode processing sections 43-1 to 43-n carry out actual turbo decode processing. The address generating section 44 generates a physical address for the first through the n-th memory bank sections 41-1 to 41-n and a parameter carrying out connection change for the interconnect section 42.

Furthermore, in also internal processing of the turbo decode processing apparatus 40, there are forward processing and backward processing for one window in a BCJR (Bahl-Cocke- Jelinek-Raviv) algorithm used in turbo decoding, as shown in Fig. 7.

Herein, the BCJR algorithm is a decoding algorithm for maximization of a post- probability of an error detection correction (mainly, a convolution code). In other words, the BCJR algorithm is an algorithm for calculating new confidence information based on received information and confidence information and a soft-input and soft-output algorithm.

As shown in Fig. 7, in the BCJR algorithm, it is possible to scheme further speed-up by dividing the one window into small regions (sub-windows) and by performing the forward processing and the backward processing thereof in pipeline or in parallel.

Non-Patent Document 1 suggests an interleave address generator for the sake of carrying out the above-mentioned interleave address generation processing in a unified architecture. Non-Patent Document 1 makes the interleave methods for the QPP and the ARP common processing by converting the above-mentioned computation formulas into recurrence formulas as follows.

In a case of the QPP interleave method, it is converted into a recurrence formula represented by Equation 3 as follows:

n_(x+i₎ = (Π_(Χ) + Γ_(χ)) mod N, Γ_{(Χ+ 1)} = (Γ_(χ) + g) mod N, where g - 2f2.

In a case of the ARP interleave method, it is converted into a recurrence formula represented by Equation 4 as follows:

Π_(Χ) = (λ _Χ) + Q_x) mod N, λ_(Χ+ΐ) = (X _x) + P0) mod N,

where, as x mode 4 = 0, 1, 2, and 3,

Qx = 1, 1+N/2+P1, 1+P2, 1+N/2+P3.

On the basis of the above-mentioned recurrence formulas, Non-Patent Document 1 suggests an interleave address generator 30 related to this invention, as shown in Fig. 9.

The illustrated interleave address generator 30 comprises first and second common arithmetic units 30a and 30b. The first and the second common arithmetic units 30a and 30b comprise first and second adders 32a and 32b, first and second subtracters 33a and 33b, first and second comparison selectors 34a and 34b, and first and second registers 35a and 35b, respectively.

The first common arithmetic unit 30a has an input end which is connected to a selection circuit 36a. The selection circuit 36a selects one of a first initial parameter and an output signal of the first common arithmetic unit 30a to supply a selected signal to a first input terminal of the first adder 32a. The first adder 32a has a second input terminal which is supplied with a second initial parameter. An output signal of the first adder 32a is supplied to a first input terminal of the first subtracter 33a and to a first input terminal of the first comparison selector 34a. The first subtracter 33a has a second input terminal which is supplied with a third initial parameter. An output signal of the first subtracter 33a is supplied to a second input terminal of the first comparison selector 34a. The output signal of the first subtracter 33a has a sign bit which is supplied to a selection terminal of the first comparison selector 34a. An output signal of the first comparison selector 34a is held in the first register 35a. A signal held in the first comparison selector 35a is produced as the output signal of the first common arithmetic unit 30a.

The second common arithmetic unit 30b has input ends which are connected to two selection circuits 36b 1 and 36b2. The selection circuit 36b 1 selects one of a first initial parameter and an output signal of the second common arithmetic unit 30b to supply a selected signal to a first input terminal of the second adder 32b. The selector circuit 36b2 selects one of a second initial parameter and the output signal of the first common arithmetic unit 30a to supply a selected signal to a second input terminal of the second adder 32b. An output signal of the second adder 32a is supplied to a first input terminal of the second subtracter 33b and to a first input terminal of the second comparison selector 34b. The second subtracter 33b has a second input terminal which is supplied with a third initial parameter. An output signal of the second subtracter 33b is supplied to a second input terminal of the second comparison selector 34b. The output signal of the second subtracter 33b has a sign bit which is supplied to a selection terminal of the second comparison selector 34b. An output signal of the second comparison selector 34b is held in the second register 35b. A signal held in the second register 35b is produced as the output signal of the second common arithmetic unit 30b.

The interleave address generator 30 illustrated in Fig. 9 generates an interleave address corresponding to the forward direction by a signal arithmetic circuit using these common arithmetic units 30a and 30b (which will be hereinafter called "intermediate value generating sections") and by appropriately supplying suitable parameters of the QPP interleave method and of the ARP interleave method.

Prior Art Documents

Non-Patent Documents

Non-Patent Document 1 : "Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," Yang Sun, ASPP' 08, 2008.

Summary of Invention:

Problem(s) to be Solved by the Invention

Problems to be solved by the present invention are that the size of circuitry for actualizing the interleave processing corresponding to the forward direction and the backward direction of the turbo coder increases in the above-mentioned multicore type turbo decode processing apparatus 40. This is because a function enable to realize the interleave processing corresponding to the backward direction is required in a case where the turbo decode processing, namely, processing carrying out the forward direction and backward direction processing in parallel for the plurality of windows using the multicore type turbo decode processing apparatus 40 including the interleave address generator 30 disclosed in Non-Patent Document 1. It is impossible to generate the interleave address corresponding to the backward direction in configuration of the interleave address generator 30 described in Non-Patent Document 1. It is therefore necessary to read addresses in inverse order out of a memory after the interleave addresses corresponding to the forward direction are generated and the generated interleave addresses are temporarily stored in the memory. As a result, the size of the memory increases by the memory storing the interleave addresses and it results in the increase of the size of circuitry.

In addition, in a case of carrying out the turbo decode processing in parallel using a plurality of turbo decode processing sections, the turbo decode processing apparatus has configuration shown in Fig. 8. Inasmuch as the input/output memories become bank configuration, it is necessary to decompose the interleave address generated by using the interleave address generator 30 disclosed in Non-Patent Document 1 into a parameter for the memory banks and a physical memory address. Inasmuch as the code length serving as turbo decode target is not limited to a value obtained by raising two to integral power, a separator 37 implementing division and modulo operation as shown in Fig. 9 is required for decomposition and it further results in decrease of the size of circuitry.

The present invention has been made in order to solve the above problems. It is, therefore, an object of the present invention to provide a turbo decode processing apparatus which is capable of generating an interleave address corresponding to a forward direction and to a backward direction for turbo decode processing with increase of a smaller size of circuitry.

Means to Solve the Problem

A multicore type turbo decode processing apparatus according to a first aspect of the present invention comprises: a plurality of data storage units; a data string conversion unit for receiving data from the plurality of data storage units to convert an order of data in a data string; a plurality of turbo decode processing units for receiving data from the data string conversion unit to carry out a turbo decode processing on them; and an address generating unit for generating an address supplied to the plurality of date storage units and a parameter supplied to the data string conversion unit, characterized in that the address generating unit comprises first through fourth intermediate value generating units, the first intermediate value generating unit generating an intermediate value required to generate the address supplied to the plurality of data storage units, the second intermediate value generating unit generating the address supplied to the plurality of data storage units from the value obtained by the first intermediate value generating unit, the third intermediate value generating unit generating an intermediate value required to generate the parameter supplied to the data string conversion unit, and the fourth intermediate value generating unit generating the parameter supplied to the data string conversion unit from the value obtained by the third intermediate value generating unit, wherein the first through the fourth intermediate value generating units are configured to enable to generate an interleave address corresponding to a forward direction and to a backward direction.

A multicore type turbo decode processing apparatus according to a second aspect of the present invention comprises: a plurality of data storage units; a data string conversion unit for receiving data from the plurality of data storage units to convert an order of data in a data string; a plurality of turbo decode processing units for receiving data from the data string conversion unit to carry out a turbo decode processing on them; and an address generating unit for generating an address supplied to the plurality of date storage units and a parameter supplied to the data string conversion unit, characterized in that the address generating unit comprises first and second intermediate value generating units and an address/parameter separation unit, the first intermediate value generating unit generating an intermediate value required to generate input data of the address/parameter separation unit, the second intermediate generating unit generating the input data of the address/parameter separation unit from the value obtained by the first intermediate generating unit, wherein the first and the second intermediate value generating units are configured to enable to generate an interleave address corresponding to a forward direction and to a backward direction, the address/parameter separation unit generates the address supplied to the plurality of data storage units and the parameter supplied to the data string conversion unit on the basis of value obtained by the second intermediate value generating unit.

Effect(s) of the Invention

With the above configuration, the following advantageous effects can be attained.

The advantageous effects of the present invention reside in that it is possible to generate the interleave address corresponding to the forward direction and to the backward direction by a single address generating device composed in the turbo decode processing apparatus.

Brief Description of the Drawings: Fig. 1 is a block diagram showing a configuration of an interleave address generating circuit for use in a multicore type turbo decode processing apparatus according to a first exemplary embodiment of the present invention;

Fig. 2 is a flowchart showing an interleave address generating method of a QPP method in the first exemplary embodiment of the present invention;

Fig. 3 is a flowchart showing an interleave address generating method of an APR method in the first exemplary embodiment of the present invention;

Fig. 4 is a block diagram showing a configuration of an interleave address generating circuit for use in a multicore type turbo decode processing apparatus according to a second exemplary embodiment of the present invention;

Fig. 5 is a flowchart showing an interleave address generating method of a QPP method in the second exemplary embodiment of the present invention;

Fig. 6 is a flowchart showing an interleave address generating method of an APR method in the second exemplary embodiment of the present invention;

Fig. 7 is a view showing a parallel processing method of a turbo decode processing related to the present invention;

Fig. 8 is a block diagram showing a multicore type turbo decode processing apparatus related to the present invention; and

Fig. 9 is a block diagram showing a configuration of an interleave address generator related to the present invention.

Embodiment(s) for carrying out the Invention:

Next, some exemplary embodiments of the present invention will be described in detail with reference to the drawings.

[First Exemplary Embodiment]

Now, as a precondition, an interleave address generating circuit according to a first exemplary embodiment of the present invention is implemented as the address generating section 44 of the multicore type turbo decode processing apparatus 40 as shown in Fig. 8.

The multicore type turbo decode processing apparatus illustrated in Fig. 8 comprises first through n-th memory bank section 41-1, 41-2, ..., and 41-n (where n represents an integer which is not less than two), an interconnect section 42, first through n-th turbo decode processing sections 43-1, 43-2, and 43-n, and the address generating section 44.

The first through the n-th memory bank sections 41-1 to 41-n are used for storing turbo decode target data (which will later be called "input data") and decoded results. The interconnect section 42 is connected to the first through the n-th memory bank sections 41-1 to 41-n and to the first through the n-th turbo decode processing sections 43-1 to 43-n. By switching internal connection configuration of the interconnect section 42, connection configuration between the first through the n-th memory bank sections 41-1 to 41-n and the first through the n-th turbo decode processing sections 43-1 to 43-n is controlled. The first through the n-th turbo decode processing sections 43-1 to 43-n carry out actual turbo decode processing. The address generating section 43 generates a physical address for the first through the n-th memory bank sections 41-1 to 41-n and a parameter carrying out connection switching for the interconnect section 42.

In other words, in the multicore type turbo decode processing apparatus 40, the firs through the n-th memory bank sections 41-1 to 41-n serve as a plurality of data storage units (41- 1 to 41-n). The interconnect section 42 is operable as a data string conversion unit (42) for receiving data from the plurality of data storage units (41-1 to 41-n) to convert an order of data in a data string. The first through the n-th turbo decode processing sections 43-1 to 43-n serve as a plurality of turbo decode processing units (43-1 to 43-n) for receiving data from the data string converting unit (42) to carry out turbo decode processing on them. And, the address generating section 44 is operable as an address generating unit (44) generating the address supplied to the plurality of data storage units (41-1 to 41-n) and the parameter supplied to the data string conversion unit (42).

Referring to Fig. 1, the description will proceed to the interleave address generating circuit 10 according to the first exemplary embodiment of the present invention that is used as the above-mentioned address generating section 44.

As shown in Fig. 1, the interleave address generating circuit 10 comprises first through fourth intermediate value generating sections 10a, 10b, 10c, and lOd. The first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd have input ends which are connected to first through fourth parameter input sections 11a, l ib, 11c, and l id, respectively, through selection circuits which will later be described.

The first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd include first through fourth main addition and subtraction selection circuits 12a, 12b, 12b, and 12d, first through fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d, first through fourth comparison and selection circuits 14a, 14b, 14c, and 14d, and first through fourth registers 15a, 15b, 15c, and 15d, respectively.

A selection circuit 16a is disposed between an output end of the first parameter input section 11a and an input end of the first intermediate value generating section 10a. The selection circuit 16a selects one of a first initial parameter produced by the first parameter input section 11a and an output signal of the first intermediate value generating section 10a to supply a selected signal to a first input terminal of the first main addition and subtraction selection circuit 12a. The first main addition and subtraction selection circuit 12a has a second input terminal which is supplied with a second initial parameter from the first parameter input section 11a. An output signal of the first main addition and subtraction selection circuit 12a is supplied to a first input terminal of the first subsidiary addition and subtraction selection circuit 13a and to a first input terminal of the first comparison and selection circuit 14a. A carry signal of the first main addition and subtraction selection circuit 12a is supplied to the second main addition and subtraction selection circuit 12b. The first subsidiary addition and subtraction selection circuit 13a has a second input terminal which is supplied with a third initial parameter from the first parameter input section 11a. An output signal of the first subsidiary addition and subtraction selection circuit 13a is supplied to a second input terminal of the first comparison and selection circuit 14a. An output signal of the first comparison and selection circuit 14a is held in the first register 15a. A signal held in the first register 15a is produced as the output signal of the first intermediate value generating section 10a.

Likewise, a selection circuit 16b is disposed between an output end of the second parameter input section 1 lb and an input end of the second intermediate generating section 10b. The selection circuit 16b selects one of a first initial parameter produced by the second parameter input section l ib and an output signal of the second intermediate value generating section 10b to supply a selected signal to a first input terminal of the second main addition and subtraction selection circuit 12b. The second main addition and subtraction selection circuit 12b has a second input terminal which is supplied with a second initial parameter from the second parameter input section l ib. An output signal of the second main addition and subtraction selection circuit 12b is supplied to a first input terminal of the second subsidiary addition and subtraction selection circuit 13b and to a first input terminal of the second comparison and selection circuit 14b. The second subsidiary addition and subtraction selection circuit 13b has a second input terminal which is supplied with a third initial parameter from the second parameter input section 1 lb. An output signal of the second subsidiary addition and subtraction selection circuit 13b is supplied to a second input terminal of the second comparison and selection circuit 14b. An output signal of the second comparison and selection circuit 14b is held in the second register 15b. A signal held in the second register 15a is produced as the output signal of the second intermediate value generating section 10b.

Two selection circuits 16cl and 16c2 are disposed between output ends of the third parameter input section 11c and input ends of the third intermediate generating section 10c. The selection circuit 16cl selects one of a first initial parameter produced by the third parameter input section 11c and an output signal of the third intermediate value generating section 10c to supply a selected signal to a first input terminal of the third main addition and subtraction selection circuit 12c. The selection circuit 16c2 selects one of a second initial parameter produced by the third parameter input section 1 lc and the output signal of the first intermediate value generating section 10a to supply a selected signal to a second input terminal of the third main addition and subtraction selection circuit 12c. An output signal of the third main addition and subtraction selection circuit 12c is supplied to a first input terminal of the third subsidiary addition and subtraction selection circuit 13c and to a first input terminal of the third comparison and selection circuit 14c. A carry signal of the third main addition and subtraction selection circuit 12c is supplied to the fourth main addition and subtraction selection circuit 12d. The third subsidiary addition and subtraction selection circuit 13c has a second input terminal which is supplied with the third initial parameter from the first parameter input section 11a. An output signal of the third subsidiary addition and subtraction selection circuit 13c is supplied to a second input terminal of the third comparison and selection circuit 14c. An output signal of the third comparison and selection circuit 14c is held in the third register 15c. A signal held in the third register 15c is produced as the output signal of the third intermediate value generating section 10c.

Two selection circuits 16dl and 16d2 are disposed between output ends of the fourth parameter input section l id and input ends of the fourth intermediate generating section lOd. The selection circuit 16dl selects one of a first initial parameter produced by the fourth parameter input section l id and an output signal of the fourth intermediate value generating section lOd to supply a selected signal to a first input terminal of the fourth main addition and subtraction selection circuit 12d. The selection circuit 16d2 selects one of a second initial parameter produced by the fourth parameter input section l id and the output signal of the second intermediate value generating section 10b to supply a selected signal to a second input terminal of the fourth main addition and subtraction selection circuit 12d. An output signal of the fourth main addition and subtraction selection circuit 12d is supplied to a first input terminal of the fourth subsidiary addition and subtraction selection circuit 13d and to a first input terminal of the fourth comparison and selection circuit 14d. The fourth subsidiary addition and subtraction selection circuit 13d has a second input terminal which is supplied with the third initial parameter from the second parameter input section l ib. An output signal of the fourth subsidiary addition and subtraction selection circuit 13d is supplied to a second input terminal of the fourth comparison and selection circuit 14d. An output signal of the fourth comparison and selection circuit 14d is held in the fourth register 15d. A signal held in the fourth register 15d is produced as the output signal of the fourth intermediate value generating section lOd.

In the manner which is described above, the interleave address generating circuit 10 comprises intermediate value generating blocks (10a, 10b, 10c, lOd) whose arithmetic portions are modified to enable to generate not only an interleave address corresponding to the forward direction but also an interleave address corresponding to the backward direction. In addition, the interleave address generating circuit 10 disposes in two parallel the intermediate value generating blocks (10a, 10b, 10c, lOd) having two parallel limited bit width using the initial parameters which are preliminarily decomposed to memory bank parameters and physical addresses and couples two devices through signal lines for exchange the carry signals.

They operate as follows, respectively.

In order to facilitate the description, as a precondition, it is assumed that the interleave address generating circuit 10 according to the first exemplary embodiment of the present invention is connected to one memory bank section in the first through the n-th memory bank sections 41-1 to 41 -n and to the interconnect section 42 which are included in the aforementioned multicore type turbo decode processing apparatus 40. That is, it is assumed that the interleave address generating circuit 10 according to the first exemplary embodiment of the present invention supplies a physical address for the one memory bank section and a connection parameter for the interconnect section 42 that indicates connection between the one memory bank section and the turbo decode processing sections.

Firstly, the description will proceed to operation in a case of carrying out the interleave address generation processing corresponding to the forward direction of the QPP interleave method.

Before generating the interleave address, initial parameters for interleave are supplied to the first through the fourth parameter input sections 11a, l ib, 11c, and 1 Id. The supplied interleave parameters comprise a code length N and interleave initial parameters 2*f2. In this event, the code length N and the interleave initial parameters 2*f2 are preliminarily separated in accordance with a sub-window number p into parameters (N_i, 2*f2_i) for the interleave and physical addresses (N_a, 2*f2_a) for the plurality of memory banks. The physical addresses (N_a, 2*f2_a) for the plurality of memory banks are supplied to the first and the second parameter input sections 1 la and 1 lb while the parameters (N_i, 2*f2_i) for the interleave are supplied to the third and the fourth parameter input sections 11c and l id.

Upon generating the interleave address corresponding to the forward direction of the QPP interleave method, the arithmetic blocks included in the first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd carry out the processing as follows,

respectively.

The first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d carry out addition processing. On carrying out the addition processing, the first main addition and subtraction selection circuit 12a and the second main addition and subtraction selection circuit 12b, and the third main addition and subtraction selection circuit 12c and the fourth main addition and subtraction selection circuit 12d are connected to each other with carry chains as shown in Fig. 1. When an arithmetic result of the first main addition and subtraction selection circuit 12a is larger than a predetermined value N_a, the carry signal thereof is delivered to the second main addition and subtraction selection circuit 12b. Similarly, when the an arithmetic result of the third main addition and subtraction selection circuit 12c is larger than the predetermined value N_a, the carry signal thereof is delivered to the fourth main addition and subtraction selection circuit 12d.

The first through the fourth subsidiary addition and subtraction selection circuit 13 a,

13b, 13c, and 13d carry out subtraction processing. The first through the fourth comparison and selection circuits 14a, 14b, 14c, and 14d carry out processing so as to select results of the first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d when the results of the first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d are positive and so as to select results of the first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d when they are negative.

The first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd are calcified by twos into a group for generating Γ values and another group for producing the interleave addresses. In each group, the second and the fourth intermediate value generating sections 10b and lOd of the upper stage serve to generate the interconnect parameter while the first and the third intermediate value generating sections 10a and 10c of the lower stage carry out generation of the physical address for the memory bank.

Each group is connected in a pipeline fashion and operates at timings as shown in Fig. 2. In other words, first, the first and the second intermediate value generating sections 10a and 10b for generating the Γ value operate, and the third and the fourth intermediate value generating sections 10c and lOd for producing the interleave address receive the obtained results to generate the interleave address. By operating in the above-mentioned manner, it is possible to obtain the interconnect parameter and the physical address for the memory bank. Now, the description will proceed to operation in a case of carry out the interleave address generation processing corresponding to the backward direction of the QPP interleave method.

Before generating the interleave address, parameters for interleave are supplied to the first through the fourth parameter input sections 11a, l ib, 11c, and l id. The supplied parameters for the interleave comprise a code length N and interleave initial parameters 2*2f. In this event, the code length N and the interleave initial parameters 2*2f are preliminarily separated in accordance with the sub-window number p into parameters (N_i, 2*2f_i) for interleave and physical addresses (N_a, 2*f2_a) for the plurality of memory banks. The physical addresses (N_a, 2*f2_a) for the plurality of memory banks are supplied to the first and the second parameter input sections 11a and 1 lb while the parameters (N_i, 2*2f_i) for the interleave are supplied to the third and the fourth parameter input sections 1 lc and l id.

Upon generating the interleave address corresponding to the backward direction of the QPP interleave method, the arithmetic blocks included in the first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd carry out the processing as follows,

respectively.

The first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d carry out subtraction processing. On carry out the subtraction processing, the first and the second main addition and subtraction selection circuits 12a and 12b, and the third and the fourth main addition and subtraction selection circuits 12c and 12d are connected to each other with carry chains as shown in Fig. 1. When an arithmetic result of the first main addition and subtraction selection circuit 12a is less than zero, the carry signal thereof is delivered to the second main addition and subtraction selection circuit 12b. Likewise, when an arithmetic result of the third main addition and subtraction selection circuit 12c is less than zero, the carry signal thereof is delivered to the fourth main addition and subtraction selection circuit 12d.

The first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d carry out addition processing. The first through the fourth comparison and selection circuits 14a, 14b, 14c, and 14d produce results of the first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d when the results of the first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, 12d are positive and produce results of the first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d when they are negative.

The first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd are classified into two groups in the manner similar to operation on the forward direction. The respective groups are connected in pipeline fashion and carry out operation at timings of Fig. 2.

In other words, first, the first and the second intermediate value generating sections 10a and 10b for generating the Γ value operate, and the third and the fourth intermediate value generating sections 10c and lOd belonging to the group for producing the interleave address receive the obtained results to generate the interleave address. By operating in the above- mentioned manner, it is possible to obtain the interconnect parameter and the physical address for the memory bank.

The description will proceed to operation in a case of carrying out the interleave address generation processing corresponding to the forward direction of the ARP interleave method.

Before and during generating the interleave address, parameters for interleave are supplied to the first through the fourth parameter input sections 11a, l ib, 11c, and l id. The supplied parameters for the interleave comprise a code length N, and interleave initial parameters P0, Q0, Ql, Q2, Q2, and Q3. In this event, the code length N and the interleave initial parameters P0, Q0, Ql, Q2, and Q3 are preliminarily separated in accordance with the sub- window number p into interleave parameters (N_i, PO i, QO i, Ql_i, Q2_i, Q3_i) and physical addresses (N_a, PO a, Q0_a, Ql_a, Q2_a, Q3_a) for the plurality of memory banks. The physical addresses ( _a, P0_a, QO a, Ql_a, Q2_a, Q3_a) for the plurality of memory banks are supplied to the first and the second parameter input sections 11a and 1 lb while the interleave parameters (N_i, PO i, Q0_i, Ql_i, Q2_i, Q3_i) are supplied to the third and the fourth input parameter sections 11c and l id.

Upon generating the interleave address corresponding to the forward direction of the ARP interleave method, the arithmetic blocks included in the first through the fourth

intermediate value generating sections 10a, 10b, 10c, and lOd carry out the processing as follows, respectively.

The first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d carry out addition processing. On carrying out the addition processing, the first and the second main addition and subtraction selection circuits 12a and 12b, and the third and the fourth main addition and subtraction selection circuits 12c and 12d are connected to each other with carry chains as shown in Fig. 1. When an arithmetic result of the first main addition and subtraction selection circuit 12a is larger than a predetermined value N_a, the carry signal thereof is delivered to the second main addition and subtraction selection circuit 12b. Similarly, when the an arithmetic result of the third main addition and subtraction selection circuit 12c is larger than the predetermined value N_a, the carry signal thereof is delivered to the fourth main addition and subtraction selection circuit 12d.

The first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d carry out subtraction processing. The first through the fourth comparison and selection circuits 14a, 14b, 14c, and 14d produce results of the first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d when the results of the first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d are positive and produce results of the first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d when they are negative.

The first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd are classified into two groups in the manner similar to that of the QPP interleave method, are connected in pipeline fashion, and carry out operation at timings of Fig. 3.

Points different from the QPP interleave method are input timings of the parameters. In the case of the ARP interleave method, there are five parameters (P0, Q0, Ql, Q2, Q3) other than N as the parameters required to input and it is necessary to produce Q0, Ql, Q2, and Q3 at there input timings by rotating them as shown in Fig. 3. By performing such an operation, it is possible to obtain the interconnect parameter and the physical address for the memory bank.

The description will proceed to operation in a case of carrying out the interleave address generation processing corresponding to the backward direction of the ARP interleave method.

Before and during generating the interleave address, parameters for interleave are supplied to the first through the fourth parameter input sections 11a, l ib, 11c, and lid. The supplied parameters for the interleave comprise a code length N, and interleave initial parameters P0, Q0, Ql, Q2, Q2, and Q3. In this event, the code length N and the interleave initial parameters P0, Q0, Ql, Q2, and Q3 are preliminarily separated in accordance with the sub- window number p into interleave parameters (N_i, P0_i, QO i, Ql_i, Q2_i, Q3_i) and physical addresses ( _a, PO a, Q0_a, Ql_a, Q2_a, Q3_a) for the plurality of memory banks. The physical addresses (N_a, PO a, QO a, Ql_a, Q2_a, Q3_a) for the plurality of memory banks are supplied to the first and the second parameter input sections 11a and l ib while the interleave parameters (N_i, PO i, QO i, Ql i, Q2_i, Q3_i) are supplied to the third and the fourth input parameter sections 11c and l id.

Upon generating the interleave address corresponding to the backward direction of the

ARP interleave method, the arithmetic blocks included in the first through the fourth

The first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d carry out subtraction processing. On carrying out the subtraction processing, the first and the second main addition and subtraction selection circuits 12a and 12b, and the third and the fourth main addition and subtraction selection circuits 12c and 12d are connected to each other with carry chains as shown in Fig. 1. When an arithmetic result of the first main addition and subtraction selection circuit 12a is less than zero, the carry signal thereof is delivered to the second main addition and subtraction selection circuit 12b. Similarly, when the an arithmetic result of the third main addition and subtraction selection circuit 12c is less than zero, the carry signal thereof is delivered to the fourth main addition and subtraction selection circuit 12d.

The first through the fourth subsidiary addition and subtraction selection circuits 13 a, 13b, 13c, and 13d carry out addition processing. The first through the fourth comparison and selection circuits 14a, 14b, 14c, and 14d produce results of the first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d when the results of the first through the fourth main addition and subtraction selection circuits 12a, 12b, 12c, and 12d are positive and produce results of the first through the fourth subsidiary addition and subtraction selection circuits 13a, 13b, 13c, and 13d when they are negative.

The first through the fourth intermediate value generating sections 10a, 10b, 10c, and lOd are classified into two groups in the manner similar to that of the QPP interleave method, are connected in pipeline fashion, and carry out operation at timings on the forward direction.

Points different from the QPP interleave method are input timings of the parameters. In the case of the ARP interleave method, there are five parameters (P0, Q0, Ql, Q2, Q3) other than N as the parameters required to input and it is necessary to produce Q3, Q2, Ql, and Q0 in inverse order to the forward direction at there input timings by rotating them as shown in Fig. 3. By performing such an operation, it is possible to obtain the interconnect parameter and the physical address for the memory banks.

In the manner which is apparent from the above-description, in the interleave address generating circuit 10, the first intermediate value generating section 10a serves as a first intermediate value generating unit (10a) for generating the intermediate value required to generate the address supplied to the plurality of data storage units (41-1 to 41-n). The second intermediate value generating section 10b serves as a second intermediate value generating unit (10b) for generating the address supplied to the plurality of data storage units (41-1 to 41-n) from the value obtained from the first intermediate generating unit (10a). The third intermediate value generating section 10c serves as a third intermediate value generating unit (10c) for generating the intermediate value required to generate the parameter supplied to the data string conversion unit (42). The fourth intermediate value generating section lOd serves as a fourth intermediate value generating unit (lOd) for generating the parameter supplied to the data string conversion unit (42) from the value obtained from the third intermediate value generating unit (10c). In addition, the first through the fourth intermediate value generating units (10a to lOd) are configured to enable to generate the interleave address corresponding to the forward direction and to the backward direction.

The first and the second parameter input sections 11a and l ib serve as first and second parameter input units (11a, l ib) for supplying initial parameters for generating the address to the first and the second intermediate value generating units (10a, 10b), respectively. The third and the fourth parameter input sections 11c and l id serve as third and fourth parameter input units (1 lc, 1 id) for supplying initial parameters for generating the parameter to the third and the fourth intermediate value generating units (10c, lOd), respectively.

In addition, each of the first through the fourth intermediate value generating units (10a, 10b, 10c, lOd) comprises the main addition and subtraction selection circuit (12a, 12b, 12c, 12d) which can select the addition processing and the subtraction processing, the subsidiary addition and subtraction selection circuit (13a, 13b, 13c, 13d) which can select the addition processing and the subtraction processing, and the comparison and selection circuit (14a, 14b, 14c, 14d) for selecting one of two values produced by the main addition and subtraction selection circuit and the subsidiary addition and subtraction selection circuit to produce selected value when the selected value is positive and to produce not-selected value when the selected value is negative.

The main addition and subtraction selection circuits (12b, 12d) of the second and the fourth intermediate value generating units (10b, lOd) carry out addition processing or subtraction processing by receiving the carry signals from the main addition and subtraction selection circuits (12a, 12c) of the first and the third intermediate value generating units (10a, 10c), respectively. The main addition and subtraction selection circuits (12a, 12c) of the first and the second intermediate value generating units (10a, 10c) produce the carry signals when the results obtained on the addition is larger than the predetermined value (N_a) and produce the carry signals when the results obtained on the subtraction is less than zero.

In a case of generating the interleave address corresponding to the forward direction, the main addition and subtraction selection circuits (12a, 12b, 12c, 12d) carry out the addition processing and the subsidiary addition and subtraction selection circuits (13a, 13b, 13c, 13d) carry out the subtraction processing.

In a case of generating the interleave address corresponding to the backward direction, the main addition and subtraction selection circuits (12a, 12b, 12c, 12d) carry out the subtraction processing and the subsidiary addition and subtraction selection circuits (13a, 13b, 13c, 13d) carry out the addition processing.

Now, the description will proceed to advantageous effects of the first exemplary embodiment.

In the interleave address generating circuit 10 according to the first exemplary embodiment, it is possible to generate the interleave address corresponding to the forward direction and to the backward diction of QPP and ARP by a single address generating device composing the multicore type turbo decode processing apparatus 40. In addition, inasmuch as the interleave address generating circuit 10 adopts a method of preliminarily separating the interleave address into parameters for memory banks generated and physical addresses, it is in no need of the module subtracter 37 required in the related interleave address generator 30 (Fig. 9). In comparison with the related interleave address generator 30 (Fig. 9), it is possible in the interleave address generating circuit 10 to cut a memory for storing interleave addresses in reverse order and circuitry amount of the module subtracter for generating the interconnect parameter and the physical address for the memory bank.

[Second Exemplary Embodiment]

Next, a second exemplary embodiment of the present invention will be described in detail with reference to the drawings.

The second exemplary embodiment is modification of the first exemplary embodiment. Differences from the first exemplary embodiment are as follows. In the first exemplary embodiment, the interleave address generation processing for the interconnect parameter and the interleave address generation processing intended for the physical address for the plurality of memory banks are processed in a division fashion. In comparison with this, the second exemplary embodiment is configured to first generate an interleave address using two intermediate value generating circuits in the manner similar to the conventional method and to obtain an interconnect parameter and a physical address for memory banks.

In a case where the code length N of a decode target (a data string) is specifically a value obtained by raising two to integral power, it is advantageous in that the load of the size of circuitry is few because it is possible to separate the interleave address into the interconnect parameter and the physical address for the memory banks by division of bits alone without using module or division.

As a precondition, the interleave address generating circuit according to the second exemplary embodiment of the present invention is implemented as the address generating section 40 of the multicore type turbo decode processing apparatus 40 as shown in Fig. 8

The multicore type turbo decode processing apparatus 40 comprises first through n-th memory bank sections 41-1 to 41 -n, an interconnect section 42, first through n-th turbo decode processing sections 43-1 to 43-n, and the address generating section 44.

The first through the n-th memory bank sections 41-1 to 41 -n are used for storing turbo decode target data (which will later be called "input data") and decoded results. The interconnect section 42 is connected to the first through the n-th memory bank sections 41-1 to 41-n and to the first through the n-th turbo decode processing sections 43-1 to 43-n. By switching internal connection configuration of the interconnect section 42, connection configuration between the first through the n-th memory bank sections 41-1 to 41-n and the first through the n-th turbo decode processing sections 43-1 to 43-n is controlled. The first through the n-th turbo decode processing sections 43-1 to 43-n carry out actual turbo decode processing. The address generating section 44 generates a physical address for the first through the n-th memory bank sections 41-1 to 41-n and a parameter carrying out connection switching for the interconnect section 42.

In other words, in the multicore type turbo decode processing apparatus 40, the firs through the n-th memory bank sections 41 - 1 to 41 -n serve as a plurality of data storage units (41- 1 to 41-n). The interconnect section 42 is operable as a data string conversion unit (42) for receiving data from the plurality of data storage units (41-1 to 41-n) to convert an order of data in a data string. The first through the n-th turbo decode processing sections 43-1 to 43-n serve as a plurality of turbo decode processing units (43-1 to 43-n) for receiving data from the data string converting unit (42) to carry out turbo decode processing on them. And, the address generating section 44 is operable as an address generating section (44) generating the address supplied to the plurality of data storage units (41-1 to 41-n) and the parameter supplied to the data string conversion unit (42).

Referring to Fig. 4, the description will proceed to the interleave address generating circuit 20 according to the second exemplary embodiment of the present invention that is used as the above-mentioned address generating section 44.

As shown in Fig. 4, the interleave address generating circuit 20 comprises first and second intermediate value generating sections 20a and 20b. The first and the second

intermediate value generating sections 20a and 20b are connected to first and second parameter input sections 21a and 21b through selection circuits which will later be described, respectively. The first and the second intermediate value generating sections 20a and 20b comprise first and second main addition and subtraction selection circuits 22a and 22b, first and second subsidiary addition and subtraction selection circuits 23a and 23b, first and second comparison and selection circuits 24a and 24b, and first and second registers 25a and 25b, respectively. A selection circuit 26a is disposed between an output end of the first parameter input section 21a and an input end of the first intermediate value generating section 20a. The selection circuit 26a selects one of a first initial parameter produced by the first parameter input section 21a and an output signal of the first intermediate value generating section 20a to supply a selected signal to a first input terminal of the first main addition and subtraction selection circuit 22a. The first main addition and subtraction selection circuit 22a has a second input terminal which is supplied with a second initial parameter from the first parameter input section 21a. An output signal of the first main addition and subtraction selection circuit 22a is supplied to a first input terminal of the first subsidiary addition and subtraction selection circuit 23a and to a first input terminal of the first comparison and selection circuit 24a. The first subsidiary addition and subtraction selection circuit 23a has a second input terminal which is supplied with a third initial parameter from the first parameter input section 21a. An output signal of the first subsidiary addition and subtraction selection circuit 23a is supplied to a second input terminal of the first comparison and selection circuit 24a. An output signal of the first comparison and selection circuit 24a is held in the first register 25a. A signal held in the first register 25a is produced as the output signal of the first intermediate value generating section 20a.

Two selection circuits 26b 1 and 26b2 are disposed between output ends of the second parameter input section 21b and input ends of the second intermediate generating section 20c. The selection circuit 26b 1 selects one of a first initial parameter produced by the second parameter input section 21b and an output signal of the second intermediate value generating section 20b to supply a selected signal to a first input terminal of the second main addition and subtraction selection circuit 22b. The selection circuit 26b2 selects one of a second initial parameter produced by the second parameter input section 21b and the output signal of the first intermediate value generating section 20a to supply a selected signal to a second input terminal of the second main addition and subtraction selection circuit 22b. An output signal of the second main addition and subtraction selection circuit 22b is supplied to a first input terminal of the second subsidiary addition and subtraction selection circuit 23b and to a first input terminal of the second comparison and selection circuit 24b. The second subsidiary addition and subtraction selection circuit 23b has a second input terminal which is supplied with the third initial parameter from the first parameter input section 21a. An output signal of the second subsidiary addition and subtraction selection circuit 23b is supplied to a second input terminal of the second comparison and selection circuit 24b. An output signal of the second comparison and selection circuit 24b is held in the second register 25b. A signal held in the second register 25b is produced as the output signal of the second intermediate value generating section 20b. In the manner which is described above, the interleave address generating circuit 20 comprises intermediate value generating blocks (20a, 20b) whose arithmetic portions are modified to enable to generate not only an interleave address corresponding to the forward direction but also an interleave address corresponding to the backward direction.

They operate as follows, respectively.

In order to facilitate the description, as a precondition, it is assumed that the interleave address generating circuit 20 according to the second exemplary embodiment of the present invention is connected to one memory bank section in the first through the n-th memory bank sections 41-1 to 41 -n and to the interconnect section 42 which are included in the afore- mentioned multicore type turbo decode processing apparatus 40. That is, it is assumed that the interleave address generating circuit 20 according to the second exemplary embodiment of the present invention supplies a physical address for the one memory bank section and a connection parameter for the interconnect section 42 that indicates connection between the one memory bank section and the turbo decode processing sections.

Before generating the interleave address, initial parameters for interleave are supplied to the first and the second parameter input sections 21a and 21b. The supplied interleave parameters comprise a code length N and interleave initial parameters 2*f2.

Upon generating the interleave address corresponding to the forward direction of the QPP interleave method, the arithmetic blocks included in the first and the second intermediate value generating sections 20a and 20b carry out the processing as follows, respectively.

The first and the second main addition and subtraction selection circuits 22a and 22b carry out addition processing. The first and the second subsidiary addition and subtraction selection circuit 23a and 23b carry out subtraction processing. The first and the second comparison and selection circuits 24a and 24b carry out processing so as to select results of the first and the second subsidiary addition and subtraction selection circuits 23a and 23b when the results of the first and the second subsidiary addition and subtraction selection circuits 23 a and 23b are positive and so as to select results of the first and the second main addition and subtraction selection circuits 22a and 22b when they are negative.

The first and the second intermediate value generating sections 20a and 20b are calcified into one for generating a Γ value and another for producing the interleave address. The first and the second intermediate value generating sections 20a and 20b are connected in a pipeline fashion and operate at timings as shown in Fig. 5. In other words, first, the first intermediate value generating section 20a for generating the Γ value operates, and the second intermediate value generating sections 20b for producing the interleave address receives the obtained result to generate the interleave address.

Thereafter, the interleave address is separated by a separator 27 into the interconnect parameter and the physical address for the memory bank. By operating in the above-mentioned manner, it is possible to obtain the interconnect parameter and the physical address for the memory bank.

Now, the description will proceed to operation in a case of carry out the interleave address generation processing corresponding to the backward direction of the QPP interleave method.

Before generating the interleave address, parameters for interleave are supplied to the first and the second parameter input sections 21a and 21b. The supplied parameters for the interleave comprise a code length N and interleave initial parameters 2*2f.

QPP interleave method, the arithmetic blocks included in the first and the second intermediate value generating sections 20a and 20b carry out the processing as follows, respectively.

The first and the second main addition and subtraction selection circuits 22a and 22b carry out subtraction processing. The first and the second subsidiary addition and subtraction selection circuits 23a and 23b carry out addition processing. The first and the second comparison and selection circuits 24a and 24b produce results of the first and the second main addition and subtraction selection circuits 22a and 22b when the results of the first and the second main addition and subtraction selection circuits 22a and 22b are positive and produce results of the first and the second subsidiary addition and subtraction selection circuits 23a and 23b when they are negative.

The first and the second intermediate value generating sections 20a and 20b play two roles in the manner similar to operation on the forward direction. The first and the second intermediate value generating sections 20a and 20b are connected in pipeline fashion, respectively and carry out operation at timings of Fig. 5. In other words, first, the first intermediate value generating section 20a for generating the Γ value operates, and the second intermediate value generating sections 20b for producing the interleave address receives the obtained result to generate the interleave address.

The obtained interleave address is supplied to the separator 27 which separates it into the interconnect parameter and the physical address for the memory bank. By operating in the above-mentioned manner, it is possible to obtain the interconnect parameter and the physical address for the memory bank.

Before and during generating the interleave address, parameters for interleave are supplied to the first and the second parameter input sections 21 a and 21b. The supplied parameters for the interleave comprise a code length N, and interleave initial parameters PO, QO, Q1, Q2, Q2, and Q3.

Upon generating the interleave address corresponding to the forward direction of the ARP interleave method, the arithmetic blocks included in the first and the second intermediate value generating sections 20a and 20b carry out the processing as follows, respectively.

The first and the second main addition and subtraction selection circuits 22a and 22b carry out addition processing. The first and the second subsidiary addition and subtraction selection circuit 23a and 23b carry out subtraction processing. The first and the second comparison and selection circuits 24a and 24b produce results of the first and the second subsidiary addition and subtraction selection circuits 23 a and 23b when the results of the first and the second subsidiary addition and subtraction selection circuits 23 a and 23b are positive and produce results of the first and the second main addition and subtraction selection circuits 22a and 22b when they are negative.

The first and the second intermediate value generating sections 20a and 20b are connected in pipeline fashion in the manner similar to that of the QPP interleave method and carry out operation at timings of Fig. 6.

Points different from the QPP interleave method are input timings of the parameters. In the case of the ARP interleave method, there are five parameters (P0, Q0, Ql, Q2, Q3) other than N as the parameters required to input and it is necessary to produce Q0, Ql , Q2, and Q3 at there input timings by rotating them as shown in Fig. 6.

The interleave address obtained from the second intermediate value generating circuit 20b is supplied to the separator 27 which separates it into the interconnect parameter and the physical address for the memory bank. By performing such an operation, it is possible to obtain the interconnect parameter and the physical address for the memory banks.

Upon generating the interleave address corresponding to the backward direction of the ARP interleave method, the arithmetic blocks included in the first and the second intermediate value generating sections 20a and 20b carry out the processing as follows, respectively.

The first and the second main addition and subtraction selection circuits 22a and 22b carry out subtraction processing. The first and the second subsidiary addition and subtraction selection circuit 23 a and 23b carry out addition processing. The first and the second comparison and selection circuits 24a and 24b produce results of the first and the second main addition and subtraction selection circuits 22a and 22b when the results of the first and the second main addition and subtraction selection circuits 22a and 22b are positive and produce results of the first and the second subsidiary addition and subtraction selection circuits 23 a and 23b when they are negative.

The first and the second intermediate value generating sections 20a and 20b are connected in pipeline fashion in the manner similar to that of the QPP interleave method and carry out operation at timings in the manner similar on the forward direction of the ARP interleave method. Points different from the QPP interleave method are input timings of the parameters. In the case of the ARP interleave method, there are five parameters (P0, Q0, Ql, Q2, Q3) other than N as the parameters required to input and it is necessary to produce Q3, Q2, Ql, and Q0 in inverse order to the forward direction at there input timings by rotating them as shown in Fig. 6.

The interleave address obtained from the second intermediate value generating circuit 20b is supplied to the separator 27 which separates it into the interconnect parameter and the physical address for the memory bank. By performing such an operation, it is possible to obtain the interconnect parameter and the physical address for the memory bank.

In the manner which is apparent from the above-description, in the interleave address generating circuit 20, the first and the second intermediate value generating sections 20a and 20b serve as first and second intermediate value generating units (20a, 20b). The separator 27 serves as an address/parameter separating unit (27).

The first intermediate value generating unit (20a) generates the intermediate value required to generate input data for the address/parameter separating unit (27). The second intermediate value generating unit (20b) generates the input data for the address/parameter separating unit (27) from the value obtained from the first intermediate generating unit (20a). The first and the second intermediate value generating units (20a, 20b) are configured to enable to generate the interleave address corresponding to the forward direction and to the backward direction. The address/parameter separating unit (27) generates, on the basis of the value obtained from the second intermediate value generating unit (20b), the address supplied to the plurality of data storage units (41-1 to 41-n) and the parameter supplied to the data string conversion unit (42).

It is preferable that the code length (N) of the data string is a value obtained by raising two to integral power.

In addition, each of the first and the second intermediate value generating units (20a, 20b) comprises the main addition and subtraction selection circuit (22a, 22b) which can select the addition processing and the subtraction processing, the subsidiary addition and subtraction selection circuit (23 a, 23b) which can select the addition processing and the subtraction processing, and the comparison and selection circuit (24a, 24b) for selecting one of two values produced by the main addition and subtraction selection circuit and the subsidiary addition and subtraction selection circuit to produce a selected value when the selected value is positive and to produce not-selected value when the selected value is negative.

In a case of generating the interleave address corresponding to the forward direction, the main addition and subtraction selection circuits (22a, 22b) carry out the addition processing and the subsidiary addition and subtraction selection circuits (23a, 23b) carry out the subtraction processing.

In a case of generating the interleave address corresponding to the backward direction, the main addition and subtraction selection circuits (22a, 22b) carry out the subtraction processing and the subsidiary addition and subtraction selection circuits (23a, 23b) carry out the addition processing.

Now, the description will proceed to advantageous effects of the second exemplary embodiment.

In the interleave address generating circuit 20 according to the second exemplary embodiment, it is possible to generate the interleave address corresponding to the forward direction and to the backward diction of QPP and ARP by a single address generating device composing the multicore type turbo decode processing apparatus 40. In comparison with the related interleave address generator 30 (Fig. 9), it is possible in the interleave address generating circuit 20 to cut a memory for storing interleave addresses in reverse order.

Industrial Applicability:

The present invention is applicable to an error correction processing apparatus in a wireless communication system, and in particular, to the use of a turbo decoding apparatus.

This application is based upon and claims the benefit to priority from Japanese patent application No. 2011-032751, filed on February 18, 2011, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A multicore type turbo decode processing apparatus comprising:

a plurality of data storage units;

a data string conversion unit receiving data from said plurality of data storage units to convert an order of data in a data string;

a plurality of turbo decode processing units receiving data from said data string conversion unit to carry out turbo decode processing on them; and

an address generating unit generating an address supplied to said plurality of data storage units and a parameter supplied to said data string conversion unit,

characterized in that said address generating unit comprises first through fourth intermediate value generating units,

said first intermediate value generating unit generating an intermediate value required to generate the address supplied to said plurality of data storage units,

said second intermediate value generating unit generating the address supplied to said plurality of data storage units from the value obtained from said first intermediate value generating unit,

said third intermediate value generating unit generating an intermediate value required to generate the parameter supplied to the data string conversion unit,

said fourth intermediate value generating unit generating the parameter supplied to said data string conversion unit from the value obtained from said third intermediate value generating unit,

wherein said first through said fourth intermediate value generating units are configured to enable to generate an interleave address which corresponds to a forward direction and to a backward direction.

2. The multicore type turbo decode processing apparatus as recited in claim 1, further comprising:

first and second parameter input units supplying initial parameters for generating the address to said first and said second intermediate value generating units, respectively; and

third and fourth parameter input units supplying initial parameters for generating the parameter to said third and said fourth intermediate value generating units, respectively.

3. The multicore type turbo decode processing apparatus as recited in claim 2, wherein each of said first through said fourth intermediate value generating units comprises: a main addition and subtraction selection circuit which can select addition processing and subtraction processing:

a subsidiary addition and subtraction selection circuit which can select addition processing and subtraction processing; and

a comparison and selection circuit selecting one of two values produced by said main addition and subtraction selection circuit and said subsidiary addition and subtraction selection circuit, said comparison and selection circuit producing a selected value when the selected value is positive and producing not-selected value when the selected value is negative,

wherein said main addition and subtraction selection circuits of said second and said fourth intermediate value generating units carry out the addition processing or the subtraction processing by receiving carry signals from said main addition and subtraction selection circuits of said first and said third intermediate value generating units, respectively,

wherein said main addition and subtraction selection circuits of said first and said second intermediate value generating units produce the carry signals when results obtained on the addition is larger than a predetermined value and produce the carry signals when the results obtained on the subtraction is less than zero.

4. The multicore type turbo decode processing apparatus as recited in claim 3, wherein said main addition and subtraction selection circuits carry out the addition processing and said subsidiary addition and subtraction selection circuits carry out the subtraction processing in a case of generating the interleave address corresponding to the forward direction,

wherein said main addition and subtraction selection circuits carry out the subtraction processing and said subsidiary addition and subtraction selection circuits carry out the addition processing in a case of generating the interleave address corresponding to the backward direction..

5. A multicore type turbo decode processing apparatus comprising:

a plurality of data storage units;

a plurality of turbo decode processing units receiving data from said data string conversion unit to carry out turbo decode processing on them; and an address generating unit generating an address supplied to said plurality of data storage units and a parameter supplied to said data string conversion unit,

characterized in that said address generating unit comprises first and second

intermediate value generating units and an address/parameter separating unit,

said first intermediate value generating unit generating an intermediate value required to generate input data for said address/parameter separating unit,

said second intermediate value generating unit generating the input data for said address/parameter separating unit from the value obtained from said first intermediate value generating unit,

wherein said first and said second intermediate value generating units are configured to enable to generate an interleave address which corresponds to a forward direction and to a backward direction,

said address/parameter separating unit generating, on the basis of the value obtained from said second intermediate value generating unit, the address supplied to said plurality of data storage units and the parameter supplied to said data string conversion unit.

6. The multicore type turbo decode processing apparatus as recited in claim 5, wherein said data string has a code length which is a value obtained by raising two to integral power.

7. The multicore type turbo decode processing apparatus as recited in claim 5 or 6, wherein each of said first and said second intermediate value generating units comprises:

a main addition and subtraction selection circuit which can select addition processing and subtraction processing;

a comparison and selection circuit selecting one of two values produced by said main addition and subtraction selection circuit and said subsidiary addition and subtraction selection circuit, said comparison and selection circuit producing selected value when the selected value is positive and producing not-selected value when the selected value is negative.

8. The multicore type turbo decode processing apparatus as recited in claim 7, wherein said main addition and subtraction selection circuits carry out the addition processing and said subsidiary addition and subtraction selection circuits carry out the subtraction processing in a case of generating the interleave address corresponding to the forward direction,,

wherein said main addition and subtraction selection circuits carry out the subtraction processing and said subsidiary addition and subtraction selection circuits carry out the addition processing in a case of generating the interleave address corresponding to the backward direction.