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EP2335374A4 - Data sampling circuit and method for clock and data recovery - Google Patents

Data sampling circuit and method for clock and data recovery

Info

Publication number
EP2335374A4
EP2335374A4 EP08877195A EP08877195A EP2335374A4 EP 2335374 A4 EP2335374 A4 EP 2335374A4 EP 08877195 A EP08877195 A EP 08877195A EP 08877195 A EP08877195 A EP 08877195A EP 2335374 A4 EP2335374 A4 EP 2335374A4
Authority
EP
European Patent Office
Prior art keywords
data
clock
sampling circuit
recovery
data recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08877195A
Other languages
German (de)
French (fr)
Other versions
EP2335374A1 (en
Inventor
Wilhelm C Fischer
David A Inglis
Yusuke Ota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZENKO TECHNOLOGIES Inc
Original Assignee
ZENKO TECHNOLOGIES Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZENKO TECHNOLOGIES Inc filed Critical ZENKO TECHNOLOGIES Inc
Publication of EP2335374A1 publication Critical patent/EP2335374A1/en
Publication of EP2335374A4 publication Critical patent/EP2335374A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
EP08877195A 2008-10-02 2008-10-02 Data sampling circuit and method for clock and data recovery Withdrawn EP2335374A4 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2008/011416 WO2010039108A1 (en) 2008-10-02 2008-10-02 Data sampling circuit and method for clock and data recovery

Publications (2)

Publication Number Publication Date
EP2335374A1 EP2335374A1 (en) 2011-06-22
EP2335374A4 true EP2335374A4 (en) 2012-03-28

Family

ID=42073727

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08877195A Withdrawn EP2335374A4 (en) 2008-10-02 2008-10-02 Data sampling circuit and method for clock and data recovery

Country Status (3)

Country Link
EP (1) EP2335374A4 (en)
CA (1) CA2774482C (en)
WO (1) WO2010039108A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8724764B2 (en) * 2012-05-30 2014-05-13 Xilinx, Inc. Distortion tolerant clock and data recovery
US9274545B2 (en) 2013-10-24 2016-03-01 Globalfoundries Inc. Apparatus and method to recover a data signal
CN113886315B (en) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 Clock data recovery system, chip and clock data recovery method
CN117917873B (en) * 2023-12-25 2025-07-11 深圳市聚亿芯电子有限公司 Optical clock recovery system and method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1061691A2 (en) * 1999-06-15 2000-12-20 Matsushita Electric Industrial Co., Ltd. Digital pll circuit for burst-mode data and optical receiving circuit using the same
WO2006011830A2 (en) * 2004-07-20 2006-02-02 Igor Anatolievich Abrosimov Re-timer circuit for data recovery with fast recovery from a low power mode
US20070064848A1 (en) * 2005-09-21 2007-03-22 Jayen Desai Clock recovery
US20080152057A1 (en) * 2000-08-30 2008-06-26 Lee Sang-Hyun Data Recovery Using Data Eye Tracking

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4486739A (en) 1982-06-30 1984-12-04 International Business Machines Corporation Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code
US20020085656A1 (en) * 2000-08-30 2002-07-04 Lee Sang-Hyun Data recovery using data eye tracking
US7983368B2 (en) * 2006-12-11 2011-07-19 International Business Machines Corporation Systems and arrangements for clock and data recovery in communications
TW200835178A (en) * 2007-02-02 2008-08-16 Smedia Technology Corp Multi-sampling data recovery circuit and method applicable to receiver

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1061691A2 (en) * 1999-06-15 2000-12-20 Matsushita Electric Industrial Co., Ltd. Digital pll circuit for burst-mode data and optical receiving circuit using the same
US20080152057A1 (en) * 2000-08-30 2008-06-26 Lee Sang-Hyun Data Recovery Using Data Eye Tracking
WO2006011830A2 (en) * 2004-07-20 2006-02-02 Igor Anatolievich Abrosimov Re-timer circuit for data recovery with fast recovery from a low power mode
US20070064848A1 (en) * 2005-09-21 2007-03-22 Jayen Desai Clock recovery

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2010039108A1 *

Also Published As

Publication number Publication date
EP2335374A1 (en) 2011-06-22
CA2774482A1 (en) 2010-04-08
WO2010039108A1 (en) 2010-04-08
CA2774482C (en) 2015-12-01

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Legal Events

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A4 Supplementary search report drawn up and despatched

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Ipc: H04L 7/00 20060101AFI20120223BHEP

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