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EP2126967A2 - Solution de gravure et procédé de gravure - Google Patents

Solution de gravure et procédé de gravure

Info

Publication number
EP2126967A2
EP2126967A2 EP08706778A EP08706778A EP2126967A2 EP 2126967 A2 EP2126967 A2 EP 2126967A2 EP 08706778 A EP08706778 A EP 08706778A EP 08706778 A EP08706778 A EP 08706778A EP 2126967 A2 EP2126967 A2 EP 2126967A2
Authority
EP
European Patent Office
Prior art keywords
etching solution
etching
silicon
silicon wafers
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08706778A
Other languages
German (de)
English (en)
Inventor
Peter Fath
Ihor Melnyk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GP Solar GmbH
Original Assignee
GP Solar GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GP Solar GmbH filed Critical GP Solar GmbH
Publication of EP2126967A2 publication Critical patent/EP2126967A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K3/00—Materials not provided for elsewhere
    • C09K3/14—Anti-slip materials; Abrasives
    • C09K3/1454—Abrasive powders, suspensions and pastes for polishing
    • C09K3/1463—Aqueous liquid suspensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/02087—Cleaning of wafer edges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/0209—Cleaning of wafer backside
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

Definitions

  • the invention relates to an etching solution according to the preamble of claim 1, its use for etching silicon and an etching method according to the preamble of claim 12.
  • Semiconductor devices play a major role in many technology branches. Depending on the variety of different components, there are various demands on the technologies for processing this material. Among these, etching technologies and etching techniques have become very important. This is based on the fact that with their help on the one hand, the material can be selectively processed at individual points, on the other hand, a large-scale processing, especially on an industrial scale, is possible. Most currently manufactured semiconductor devices are based on silicon as the starting material.
  • etching solution When selectively machining individual locations of the components or blanks, it must be ensured that the etching solution only reaches those locations where removal of material is to take place, but other areas remain unaffected. This is usually done by masking areas that are not to be etched with a material that is resistant to the etching solution, so to speak. Such masking may be accomplished by applying etching-solution-resistant paints, films, foils or the like. Such masks are complex. If possible, other effects are used to preserve individual areas from contact with the etching solution, such as wetting phenomena or gravitational effects. In the simplest case, a blank is held only partially in a not completely wetting etching solution, so that below the liquid level of the etching solution and etched below the wetted areas of the blank, but not above the wetted areas.
  • the present invention is therefore based on the object to provide an improved etching solution, which allows a more precise selective processing of individual areas.
  • the invention is based on the object to improve the etching of silicon, in particular silicon wafers with a surface structuring.
  • the invention is based on the object to provide an improved etching process for silicon wafers available.
  • the etching solution according to the invention has a comparatively low surface tension combined with a good etching effect in the case of inorganic materials, in particular silicon. As a result, it tends less to penetrate into small-sized surface structures.
  • Such surface structures may be formed by microcracks or machining structures in the surface of the blank to be etched.
  • some surface structuring - often referred to as surface texturing - may also be introduced into the blank.
  • Such surface structuring can be introduced mechanically, for example, as happens in particular in the mechanical structuring of solar cells for the purpose of increasing the light coupling. But they can also be the result of a previous etching process.
  • anisotropic etching solutions are used, which have different strong etching effects in different spatial directions, optionally depending on the crystal orientation of a crystal to be etched, so that a surface structure is formed. This surface structure can in turn cause increased light coupling into the solar cells.
  • the etching solution according to the invention is preferably used for the, optionally selective, etching of silicon or silicon-containing compounds, in particular silicate glasses. This also means doped silicon.
  • the sulfuric acid in the etching solution according to the invention does not participate in the chemical etching reaction. It serves primarily to increase the specific gravity of the etching solution. Although the chemical reactions taking place during the etching process and the associated reaction of the reagents reduce the specific gravity of the etching solution per se, this is approximately compensated by the etched silicon now in the etching solution. As a result, supply of sulfuric acid to maintain the initial specific gravity is not required.
  • the etching solution according to the invention can be advantageously used.
  • dopants are diffused into silicon wafers, which form silicate glasses, which are often removed. This can be done with the etching solution according to the invention.
  • boron or phosphorus silicate glasses formed during phosphorus or boron diffusion can be removed.
  • doped layers can be removed locally with simultaneously low risk of damage to the surrounding doped regions.
  • silicon wafers so-called wafers
  • wafers starting material used for the production of semiconductor devices such as integrated circuits or solar cells. These are mostly made by sawing cast silicon slices into slices or sawing off slices from drawn silicon columns. In dies.en sawing, which are usually carried out with wire saws, there is a damage to the surface of the silicon wafers. This is usually removed by overetching the silicon wafers, in which case also the etching solution according to the invention can be used.
  • silicon wafers are drawn directly from the desired thickness from a silicon melt. These silicon wafers are often called silicon bands. Although there is no sawing damage in these
  • the near-surface layer is often relatively heavily contaminated, so here over-etching of the silicon wafers for the purpose of at least partial removal of these contaminated layers is made.
  • the etching solution according to the invention can be used.
  • FIG. 1 Schematic representation of a silicon wafer provided with a surface structuring in an etching solution according to the invention during the etching according to an etching method according to the invention in a side view.
  • FIG. 2 front view of the silicon wafer from FIG. 1 1 shows a silicon wafer 3 intended for the production of a solar cell, which has already been exposed to phosphorus diffusion. As a result, it carries over its entire surface a phosphorus doped layer and a phosphosilicate glass. Furthermore, the silicon wafer was provided with a surface structuring 5 before the phosphorus diffusion. This was introduced mechanically here. For the invention, however, it is irrelevant how the surface structure is introduced. This can also be done, for example, by chemical processes such as anisotropic or crystal orientation-dependent etching.
  • the two largest side surfaces of the silicon wafer 3 form the front side 25 and the back side 27.
  • the silicon wafer 3 peripherally edge surfaces 7, 9, of which in Fig. 1, the edge surface 7 is visible.
  • Each of the edge surfaces has a longitudinal extent 8 and 10, respectively.
  • the silicon wafer 3 is partially immersed in an etching solution 1.
  • the immersion depth is chosen so that each edge surface, in particular the edge surfaces 7 and 9, are always located partially below the liquid level 11 of the etching solution along the direction of their longitudinal extension, in the case of edge surfaces 7 and 9 along the direction of the longitudinal extensions 8 and 10 ,
  • the phosphosilicate glass and the phosphorus-doped layer underneath can be removed at the edge surfaces in such a way that, when a conductive layer is applied to the back side 27 of the solar cell, there is no electrically conductive connection to the front side 25 over the edge surfaces, which would short the solar cell , Moreover, the phosphorus doped layer as well as the phosphorous glass on the back side 27 can be removed.
  • the etching solution used is an etching solution 1 according to the invention comprising water, nitric acid, hydrofluoric acid and sulfuric acid, which contains 15 to 40% by weight of nitric acid, 10 to 41% by weight of sulfuric acid and 0.8 to 2.0% by weight of hydrofluoric acid. It is preferable to use an etching solution 1 containing 27% by weight of nitric acid, 26% by weight of sulfuric acid and 1.4% by weight of hydrofluoric acid. In the present case, deionized water is also used in order to prevent contamination entry into the silicon wafer 3, which could impair the performance of the finished solar cell. At lower purity requirements, water can be used instead in commonly available form.
  • the etching solution 1 is always maintained during the etching at a temperature between 4 0 C and 15 0 C, preferably at a temperature between 7 0 C and 10 0 C. This allows in conjunction with the etching solution 1 according to the invention that this is not due to capillary effects as stated above, enters parts of the surface structuring 5 and damages them.
  • the thickness ie, the distance between the front side 25 and the back side 27 of the silicon wafer 3 is usually in the range of 100 nm to 350 nm, with a tendency to further decrease the thickness.
  • the immersion depth of the silicon wafer is determined by the conveyor belts 13, 15 shown in Figures 1 and 2, on which the silicon wafer 3 rests.
  • other devices are also conceivable, on which the silicon wafer 3 rests, for example lowerable wire mesh or the like.
  • the advantage of the conveyor belts 13, 15, the number of which, depending on the mechanical properties of the silicon wafer 3 in principle is arbitrary, is that they are relatively easy to drive; For example, by means of drive rollers 17, 19, 21. This allows etching of silicon wafers 3 in an efficient continuous process.
  • conveyor belts 13, 15 may be provided in a known manner arranged in a continuous sequence transport rollers, which transport the silicon wafer through the etching solution 1 through and chen ermölow- a continuous process.
  • elastic conveyor belts may be more advantageous to some extent.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Weting (AREA)
  • Photovoltaic Devices (AREA)

Abstract

Solution de gravure (1) qui contient de l'eau, de l'acide nitrique, de l'acide fluorhydrique et de l'acide sulfurique, à raison de 15 à 40 pour cent en poids d'acide nitrique, de 10 à 41 pour cent en poids d'acide sulfurique et de 0,8 à 2,0 pour cent en poids d'acide fluorhydrique. La présente invention concerne également l'utilisation de cette solution pour la gravure de silicium, ainsi que des procédés de gravure pour des tranches de silicium.
EP08706778A 2007-01-22 2008-01-22 Solution de gravure et procédé de gravure Withdrawn EP2126967A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007004060A DE102007004060B4 (de) 2007-01-22 2007-01-22 Verwendung einer Ätzlösung aufweisend Wasser, Salpetersäure und Schwefelsäure und Ätzverfahren
PCT/DE2008/000099 WO2008089733A2 (fr) 2007-01-22 2008-01-22 Solution de gravure et procédé de gravure

Publications (1)

Publication Number Publication Date
EP2126967A2 true EP2126967A2 (fr) 2009-12-02

Family

ID=39530927

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08706778A Withdrawn EP2126967A2 (fr) 2007-01-22 2008-01-22 Solution de gravure et procédé de gravure

Country Status (6)

Country Link
US (1) US20100120248A1 (fr)
EP (1) EP2126967A2 (fr)
KR (1) KR20090127129A (fr)
CN (1) CN101622697A (fr)
DE (1) DE102007004060B4 (fr)
WO (1) WO2008089733A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008056455B3 (de) * 2008-11-07 2010-04-29 Centrotherm Photovoltaics Technology Gmbh Oxidations- und Reinigungsverfahren für Siliziumscheiben
KR20120135185A (ko) * 2009-09-21 2012-12-12 바스프 에스이 단결정 및 다결정 규소 기판의 표면을 조직화하기 위한 산성 에칭 수용액 및 방법
WO2011072706A1 (fr) * 2009-12-18 2011-06-23 Rena Gmbh Procédé d'enlèvement de couches d'un substrat
KR20120064364A (ko) * 2010-12-09 2012-06-19 삼성전자주식회사 태양 전지의 제조 방법
CN103117325B (zh) * 2011-11-17 2015-09-30 中建材浚鑫科技股份有限公司 不合格多晶扩散方块电阻的返工方法
CN103137782A (zh) * 2011-12-01 2013-06-05 浚鑫科技股份有限公司 单晶硅电池片中分离p-n结及太阳能电池制作方法
DE102014013591A1 (de) 2014-09-13 2016-03-17 Jörg Acker Verfahren zur Herstellung von Siliciumoberflächen mit niedriger Reflektivität
US9633866B2 (en) * 2015-05-18 2017-04-25 Texas Instruments Incorporated Method for patterning of laminated magnetic layer
CN107553764B (zh) * 2017-09-26 2019-05-03 无锡琨圣科技有限公司 一种金刚线切割硅片用扩孔槽的槽体

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2337062A (en) * 1942-04-07 1943-12-21 Solar Aircraft Co Pickling solution and method
EP0496229A2 (fr) * 1991-01-21 1992-07-29 Riedel-De Haen Aktiengesellschaft Solution d'attaque pour traitements chimiques par voie humide dans la fabrication de semi-conducteurs
WO2005093788A1 (fr) * 2004-03-22 2005-10-06 Rena Sondermaschinen Gmbh Procede de traitement de surfaces de substrats

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Publication number Priority date Publication date Assignee Title
DE3728693A1 (de) * 1987-08-27 1989-03-09 Wacker Chemitronic Verfahren und vorrichtung zum aetzen von halbleiteroberflaechen
DE19962136A1 (de) * 1999-12-22 2001-06-28 Merck Patent Gmbh Verfahren zur Rauhätzung von Siliziumsolarzellen
DE10229499B4 (de) * 2002-04-23 2007-05-10 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Bearbeiten eines Wafers
US20030230548A1 (en) * 2002-06-18 2003-12-18 Wolfgang Sievert Acid etching mixture having reduced water content
KR100742276B1 (ko) * 2004-11-10 2007-07-24 삼성전자주식회사 저유전율 유전막을 제거하기 위한 식각 용액 및 이를이용한 저유전율 유전막 식각 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2337062A (en) * 1942-04-07 1943-12-21 Solar Aircraft Co Pickling solution and method
EP0496229A2 (fr) * 1991-01-21 1992-07-29 Riedel-De Haen Aktiengesellschaft Solution d'attaque pour traitements chimiques par voie humide dans la fabrication de semi-conducteurs
WO2005093788A1 (fr) * 2004-03-22 2005-10-06 Rena Sondermaschinen Gmbh Procede de traitement de surfaces de substrats

Also Published As

Publication number Publication date
KR20090127129A (ko) 2009-12-09
WO2008089733A3 (fr) 2009-01-08
US20100120248A1 (en) 2010-05-13
CN101622697A (zh) 2010-01-06
DE102007004060B4 (de) 2013-03-21
WO2008089733A2 (fr) 2008-07-31
DE102007004060A1 (de) 2008-07-24

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