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EP1964173A1 - Microcomponent comprising two wafers interconnected by pins and the associated interconnection process - Google Patents

Microcomponent comprising two wafers interconnected by pins and the associated interconnection process

Info

Publication number
EP1964173A1
EP1964173A1 EP06831789A EP06831789A EP1964173A1 EP 1964173 A1 EP1964173 A1 EP 1964173A1 EP 06831789 A EP06831789 A EP 06831789A EP 06831789 A EP06831789 A EP 06831789A EP 1964173 A1 EP1964173 A1 EP 1964173A1
Authority
EP
European Patent Office
Prior art keywords
wafer
pins
microcomponent
electrical connection
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06831789A
Other languages
German (de)
French (fr)
Inventor
Jean Brun
François BALERAS
Jean-Louis Pornin
Lydie Mathieu
Béatrice BONVALOT-DUBOIS
Julien Roumegoux
Frédéric DEPOUTOT
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales DIS France SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Axalto SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Axalto SA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1964173A1 publication Critical patent/EP1964173A1/en
Withdrawn legal-status Critical Current

Links

Classifications

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Definitions

  • Microcomponent comprising two wafers interconnected by pins and the associated interconnection process
  • the invention relates to a microcomponent comprising:
  • the invention also relates to an associated interconnection process for such a microcomponent.
  • wafer any element that could form part of the microcomponent - that is a part of an electronic circuit, an electronic circuit, a single substrate, etc.
  • the two wafers of the microcomponent must be interconnected to each other.
  • the search to find the best possible interconnection between the wafers of a microcomponent is an acknowledged issue in the industry, relating to issues of conditioning during the manufacture of the microcomponent and issues of security, notably against all types of chemical, physical and energy attacks.
  • microcomponent 1 consists of a first wafer 2, for instance a silicon substrate with a CMOS circuit, consisting of a first side 3 on which there are the electrical connection pads 4.
  • a plurality of electrical connection pins 5 are then formed on the electrical connection pads 4 of the first wafer 2.
  • a layer 6 of a sealing material is then applied to the first side 3 of the first wafer 2 (figure 1).
  • a second wafer 7 for instance a silicon substrate provided with a CMOS circuit, consists of a plurality of electrical connection pads 8, intended to cooperate with the electrical connection pins 5 of the first wafer 2.
  • the sealing layer 6 is structured, preferably, around the electrical connection pins 5 of the first wafer 2, such that they are awaiting cooperation with the electrical connection pads 8 of the second wafer 7.
  • the interconnection process for wafers 2 and 7 of the microcomponent 1 thus consists of placing the electrical connection pads 8 of the second wafer 7 in front of the electrical connection pins 5 of the first wafer 2 (figure 2).
  • the second wafer 7 is then sealed to the first wafer 2, by means of layer 6 of the sealing material, for example by thermocompression.
  • the electrical connection pins 5 of the first wafer 2 are in contact with the electrical connection pads 8 of the second wafer 7 and sealing material layer 6 is distributed between the electrical connection pins 5 of the first wafer 2.
  • the microcomponent 1 thus assembled now has its two wafers 2 and 7 interconnected by means of the electrical connection pins 5 and anchored by sealing layer 6.
  • a microcomponent assembled using an interconnection process such as that described above does not have optimum characteristics in terms of the electrical connections and mechanical solidity, notably with regard to the location of the pins relative to the electrical connection pads.
  • a microcomponent does not provide sufficient guarantees in terms of issues relating to security, concerning the coming apart of the wafers of the microcomponent.
  • the purpose of the invention is to resolve the above mentioned drawbacks and is intended to produce a microcomponent consisting of two interconnected wafers, simple to produce and achieving a good mechanical solidity between the wafers and an optimum electrical connection between the two wafers, whilst satisfying the security criteria aimed at preventing the deterioration of the microcomponent.
  • the subject of the invention is characterised by the fact that the second wafer has a plurality of interconnection pins, located on a first side of the second wafer, opposing the first side of the first wafer.
  • the first interconnection pins of the second wafer are formed on the electrical connection pads of the second wafer, with the first interconnection pins being positioned facing the electrical connection pins of the first wafer and coming into contact by nesting one within the other.
  • the first wafer has additional pins, formed on the support pads of the first wafer and act to provide the basis for the mechanical support.
  • the second interconnection pins on the second wafer, formed on the support pads of the second wafer act as mechanical anchoring pins, facing the sealing material.
  • each pad is associated with a bi-dimensional matrix of pins.
  • the purpose of the invention is also for the realisation of an interconnection process with the assembling and anchoring of a first wafer and a second wafer to form a microcomponent, with the first and second wafers being anchored and interconnected to each other, with the process comprising at least the following steps:
  • Figures 1 to 3 are schematic representations of various stages of a process for the interconnection by assembling and sealing of two wafers of a microcomponent in application of the existing state of the art.
  • Figure 4 is a schematic representation of a first embodiment of a microcomponent according to the invention, before the assembling and sealing of its wafers.
  • Figure 5 is a highly schematic representation of a detailed section of the nesting pins of the microcomponent according to figure 4.
  • Figure 6 is a schematic representation of a variant for the formation of a microcomponent according to the invention, before the assembling and sealing of its wafers.
  • Figure 7 is a schematic representation of another variant for the formation of a microcomponent according to the invention, before the assembling and sealing of its wafers.
  • Figures 8 and 9 are each highly schematic representations of a detailed section of the nesting in the variants of pins of a microcomponent according to the invention.
  • microcomponent 1 has a plurality of interconnection pins, formed on a first side, side 9 of the second wafer 7, intended to face the first side 3 of the first wafer 2.
  • FIGS 4, 6 and 7, the various embodiments of the microcomponent 1 are shown before assembly and sealing of wafers 2 and 7 of microcomponent 1.
  • the second wafer 7 has first interconnection pins 10, formed on electrical connection pads 8 of the second wafer 7.
  • the electrical connection pads 8 and the interconnection pins 10 of the second wafer 7 are slightly offset relative to the electrical connection pads 4 and the electrical connection pins 5 of the first wafer 2.
  • the interconnection pins 10 of the second wafer 7 and the electrical connection pins 5 of the first wafer 2 come into contact by nesting with each other (figure 5).
  • the interconnection pins 10 of the second wafer 7 and the electrical connection pins 5 of the first wafer 2 then act to provide an electrical contact between the two wafers 2 and 7.
  • microcomponent 1 can have a passivation layer (not shown in figure 4), formed conventionally on the first side 9 of the second wafer 7, preferably prior to the formation of the electrical connection pads 8, and intended particularly to protect the first side 9 of the second wafer 7.
  • the interconnection pins 10 of the second wafer 7 must thus be long enough to project through this passivation layer and overcome the disadvantages of such passivation layer.
  • FIG 5 the nesting of the electrical connection pins 5 of the first wafer 2 and the interconnection pins 10 of the second wafer 7 is shown highly schematically.
  • the nesting consists of placing in contact at least part of an electrical connection pin 5 of the first wafer 2 with at least part of an interconnection pin 10 of the second wafer 7.
  • the interconnection pins 10 associated with each connection pad 8 of the second wafer 7 and the electrical connection pins 5 associated with each electrical connection pad 4 of the first wafer 2 are distributed, preferably, in accordance with the bi-dimensional matrices. At least a sufficient number of pins 5, 10 thus enable the establishing of an optimum contact between wafers 2 and 7.
  • electrical connection pins 5 and the interconnection pins 10 of the second wafer 7 are cylindrical.
  • the electrical connection pins 5 of the first wafer 2 have a height hi of approximately 3 ⁇ m to 9 ⁇ m and a width L1 of approximately 2/vm to 5 ⁇ m.
  • Interconnection pins 10 of the second wafer 7 have a height h2 of approximately 2 ⁇ m and a width L2 of approximately 2//m.
  • Electrical connection pins 5 of the first wafer 2 and interconnection pins 10 of the second wafer 7 nest, for example, with an overlay height H of approximately 0.5 ⁇ m to 1 ⁇ m.
  • the second wafer 7 has second interconnection pins 11 , formed on the support pads 12 formed on the first side 9 of the second wafer 7.
  • the second interconnection pins 11 of the second wafer 7 constitute mechanical anchoring pins, facing the sealing layer 6 and intended to work with sealing layer 6 during the assembly of wafers 2 and 7 of the microcomponent 1.
  • the second interconnection pins 11 are, preferably, identical to the first interconnection pins 10, as shown in figure 5.
  • the second interconnection pins 11 are intended solely for ensuring an optimum mechanical anchoring of the two wafers 2 and 7 of the microcomponent 1.
  • the electrical connection of the microcomponent 1 is then achieved by electrical connection pins 5 of the first wafer 2, working with the electrical connection pads 8 of the second wafer 7.
  • the second interconnection pins 11 can also be formed on the support pads 12 formed on the first side 9 of the second wafer 7 of the microcomponent 1 as shown in figure 4.
  • the same microcomponent 1 then has both the first interconnection pins 10 of the second wafer 7, for the electrical connection of wafers 2 and 7 (figure 4), and the second interconnection pins 11 of the second wafer 7, for the mechanical anchoring of the second wafer 7 to the first wafer 2 (figure 6).
  • the first wafer 2 of the microcomponent 1 has electrical connection pins 5, mating both with the electrical connection pads 8 of the second wafer 7, shown on the right-hand side of the first wafer 2, and with the first interconnection pins 10 of the second wafer 7, shown on the left-hand side of the first wafer 2.
  • the electrical connection pads 4 of the first wafer 2 are connected to the corresponding electrical circuits (not shown) by means, for example, of electrical connection tracks 13.
  • the electrical connection pads 8 of the second wafer 7 are linked to the corresponding electrical circuits (not shown) by means, for example, of electrical connection tracks 14.
  • the first wafer 2 of the microcomponent 1 also has additional pins 15, on the support pads 16 formed on the first side 3 of the first wafer 2.
  • the additional pins 15 of the first wafer 2 act as mechanical support elements for the microcomponent 1 , performing notably the role of spacers for the assembling of the two wafers 2 and 7.
  • the additional pins 15 can be nested, as a preference, with the additional interconnection pins 17 of the second wafer 7, formed on the support pads 12 on the first side 9 of the second wafer 7.
  • Additional pins 15 and 17 thus act solely as mechanical support elements for microcomponent 1 and act as spacers and thickness shims for the microcomponent 1.
  • the additional pins 15 and 17 enable more specifically the increasing of the security of the interconnection between wafers 2 and 7.
  • the additional pins 15, 17 enable notably the prevention of any functional disassembling of the two wafers 2, 7 of the microcomponent 1.
  • Such additional pins 15, 17 thus maximise the security with regard to the deterioration of one of the wafers 2, 7 of the microcomponent 1 in the event of polishing.
  • the second interconnection pins 11 intended for anchoring in sealing layer 6, as shown in figure 6, can be formed on the other support pads 12 on the first side 9 of the second wafer 7 of a microcomponent 1 as shown in figure 7.
  • the mechanical anchoring of the two wafers 2 and 7 is strengthened because wafers 2 and 7 are held by the additional pins 15 of the first wafer 2 and the additional pins 17 of the second wafer 7 and the second interconnection pins 11 of the second wafer 7, anchored in sealing layer 6.
  • a multitude of additional pins 15, 17, and/or pins 11 provided for the mechanical anchoring in the sealing layer are directly placed on part or on the whole of the surface of at least one wafer 2, 7. This multitude of pins thus allows the achievement of a mechanical anchoring by means of nesting the pins one with the other.
  • the fact of including a large number of small size pins 15, 17, 11 , on the surface of the wafers enables a reduction in the assembling energy by limiting the efforts in terms of the nesting.
  • all of the pins 5, 15 of the first wafer 2 are, preferably, of the same shape and the same size and all of the pins 10, 11 , 17 of the second wafer 7 are also all, preferably, of the same shape and the same size.
  • each pad of the first wafer 2, that is the electrical connection pads 4 and the support pads 16, and each pad of the second wafer 7, that is the electrical connection pads 8 and the support pads 12, are associated with a bi-dimensional matrix of corresponding pins 5, 10, 11 , 15, 17.
  • the bi-dimensional matrices of pins 5, 10, 11 , 15, 17 can take any shape, for example, square, rectangular, circular or even dissymmetric, provided they enable a good quality contact or an sufficient contact between pins 5, 10, 11 , 15, 17.
  • all of the pins 5, 10, 11 , 15, 17 have, preferably, the same section, for example square, rectangular, or circular, and are made of the same material, for example nickel or copper.
  • a free end of each of the pins 5, 10, 11 , 15, 17 can also include a finishing coating of gold.
  • pins 5, 15 of the first wafer 2 are formed on the corresponding pads 4, 16 of the first wafer 2, preferably, by electrochemical growth.
  • Pins 10, 11 , 17 of the second wafer 7 are formed on the corresponding pads 8, 12 of the second wafer 7, preferably, by chemical growth, also known as "electroless" deposition.
  • Pins 5, 15 of the first wafer 2 are thus hard, and pins 10, 11 , 17 of the second wafer 7 are thus soft, relative to pins 5, 15 of the first wafer 2.
  • Pins 5, 15 of the first wafer 2 are, preferably, higher and harder than pins 10, 11 , 17 of the second wafer 7, for safety reasons, and pins 10, 11 , 17 of the second wafer 7 are softer than pins 5, 15 of the first wafer 2, notably to enable their hardening by annealing after sealing, in order to optimise the anchoring of the two wafers 2 and 7.
  • pins 10, 11 , 17 of the second wafer 7 can be produced simultaneously with pins 5, 15 of the first wafer 2, during a same production step of wafers 2 and 7, or can be produced after pins 5, 15 of the first wafer 2, during the two succeeding fabrication stages.
  • both the pins 5, 15 of the first wafer 2 and pins 10, 11 , 17 of the second wafer 7 by electro-chemical growth, as all of the pins 5, 10, 11 , 15, 17 of the microcomponent 1 are hard, or by chemical growth, as all of the pins 5, 10, 11 , 15, 17 of the microcomponent 1 are soft.
  • pins 5, 15 of the first wafer 2 can be formed by chemical growth and pins 10, 11 , 17 of the second wafer 7 can be formed by electro- chemical growth, as pins 5, 15 of the first wafer 2 are thus soft relative to pins 10, 11 , 17 of the second wafer 7.
  • the layer 6, for example, in a polymer material is deposited, for example, on the first side 3 of the first wafer 2.
  • the layer 6, for example, in polyimide is then, preferably, structured by means of masks and etching stages, notably around pins 5, 15 of the first wafer 2.
  • first side 9 of the second wafer 7 is aligned relative to the first side 3 of the first wafer 2 and the assembly and sealing of the second wafer 7 on the first wafer 2 is performed, for example, by thermocompression, eutectic soldering, gluing, etc.
  • a liquid glue for example epoxy resin, replacing sealing layer 6.
  • the process consists of applying the liquid glue, for example on the first side 3 of the first wafer 2, and of performing the assembly and sealing of the two wafers 2 and
  • thermocompression for example by thermocompression or just using cold compression.
  • the pins 10, 11 , 17 of the second wafer 7 are softer than pins 5, 15 of the first wafer 2 and have a relatively short height h2, they can be hardened by an annealing phase, after the sealing of wafers 2 and 7.
  • the microcomponent 1 notably provides a reliable and optimum interconnection in terms of the electrical connection and mechanical anchoring, thanks namely to the interconnection pins forming both means of electrical connection and means of mechanical anchoring. Furthermore, the protection against disassembly of wafers 2 and 7 is ensured, namely thanks to the additional pins 15 of the first wafer 2 and to the additional interconnection pins 17 of the second wafer 7. In addition, the presence of interconnection pins on each active side of the microcomponent 1 , that is on the first side 3 of the first wafer 2 and on the first side 9 of the second wafer 7, increases the capacity and the reliability of the microcomponent 1.
  • pins 5, 10, 11 , 15, 17 in a bi-dimensional matrix enables the optimising of the large-scale electrical contact.
  • the connection surface of the pins, from a mechanical and electrical point of view, is greater, more robust and offers increased flexibility of contact.
  • connection pads 4, 8 of the two wafers The electrical connection is achieved, at the level of the connection pads 4, 8 of the two wafers, through contact between the interconnection pins 5, 10 of the two wafers.
  • the embodiments as described above do not require huge accuracy in the aligning of the connection pads 4, 8 with regard to each other. Indeed, given that several interconnection pins 5, 10 are supported by each connection pad 4, 8, it is sufficient that at least two interconnection pins 5, 10 are nested to achieve an electrical connection.
  • the assembling can therefore include a slight offset in the connection pads 4, 8 with regard to each other.
  • the assembling does not require the use of assembly spacers to maintain the assembly height, as this is fixed by the assembly conditions, that is by the force applied, the temperature, shape of the pins, the materials used and the materials used for the sealing layer.
  • this interconnection process for wafers 2, 7 of the microcomponent 1 is easily implemented and ensures a reliable interconnection in terms of the electrical connection and mechanical anchoring.
  • the sealing of wafers 2 and 7 is irreversible and the security of the assembling is notably ensured by means of the additional pins 15 and 17.
  • the conditioning of the microcomponent 1 also achieves an optimum efficiency, thanks notably to the simplicity of the interconnection process according to the invention.
  • the invention is not limited to the various embodiments as described above.
  • the shape and the dimensions of the pins 5, 10, 11 , 15, 17 can be different, provided that the pins ensure the achievement of an optimum electrical connection and mechanical interconnection.
  • the electrical connection pins 5 of the first wafer 2 can notably conform according to a body, for example, in a cylindrical shape, with an enlarged, domed and malleable free end 19, in the general shape of a cap.
  • the interconnection pins 10 of the second wafer 7 have, for example, a bevelled end 20, intended to mate with the enlarged ends 19 of the electrical connection pins 5 of the first wafer 2.
  • the enlarged ends 19 of the electrical connection pins 5 are malleable, as shown by the dotted lines in figure 8, under the effect of the bevelled end 20 of the interconnection pins 10. This configuration enables namely the optimising of the electrical contact between the pins 5 and 10.
  • the interconnection pins 10 of the second wafer 7 may be identical with the electrical connection pins 5 of the first wafer 2, shown in figure 8, and can have an enlarged, domed and malleable end 19.
  • the enlarged ends 19 distort, in order for the enlarged ends 19 of interconnection pins 10 of the second wafer 7 to come within the enlarged ends 19 of the electrical connection pins 5 of the first wafer 2.
  • the additional pins 15 of the first wafer 2, the additional interconnection pins 17 and the second interconnection pins 11 of the second wafer 7 can also be the same shape as the electrical connection pins 5 of the first wafer 2 and the first interconnection pins 10 of the second wafer 7, as shown in figures 8 and 9.
  • the height of the covering H can vary, depending on the deformation and the various heights to be taken up by the pins 10, 11 , 17 of the second wafer 7, during the sealing of the microcomponent 1.
  • the pads 4, 8, 12, 16 of wafers 2 and 7 can be formed by the metallization of the surface and etching. Their exact location on the first side 3 of the first wafer 2 and on the first side 9 of the second wafer 7 is not important, provided that they allow the achievement of a good interconnection between the two wafers 2, 7.
  • the microcomponent 1 shown in figures 4 and 6 can have electrical connection tracks, such as shown in figure 7, linking the corresponding pads 4, 8 with the associated electrical circuits (not shown in figures 4 and 6).
  • microcomponent 1 deriving the benefits of having all of the types of pins, that is the electrical connection pins 5 on the first wafer 2 mating with interconnection pins 10 of the second wafer 7 and with the electrical connection pads 8 of the second wafer 7, the additional pins 15 on the first wafer 2, mating with the additional pins 17 of the second wafer 7, and the second interconnection pins 11 on the second wafer 7, mating with the sealing layer 6 for the mechanical anchoring.
  • the microcomponent 1 is used namely in the field of integrated circuits, and more specifically for chip cards.

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Abstract

The microcomponent (1) has a first wafer (2), equipped with multiple electrical connection pins (5), a second wafer (7), equipped with multiple electrical connection pads (8), intended to cooperate with the electrical connection pins (5) of the first wafer (2). The second wafer (7) has multiple first interconnection pins (10), formed on the electrical connection pads (8) of the second wafer (7), positioned facing the electrical connection pins (5) of the first wafer (2) and coming into contact with each other by nesting. An interconnection process for the first (2) and second (7) wafers of the microcomponent (1) consisting of at least the stages of the formation of the pins (5) of the first wafer (2), for example by electro-chemical growth, and of the formation of the pins (10) of the second wafer (7), for example by chemical growth.

Description

Microcomponent comprising two wafers interconnected by pins and the associated interconnection process
Technical domain of the invention
The invention relates to a microcomponent comprising:
- a first wafer provided with a plurality of electrical connection pins formed on a first side of the first wafer,
- a second wafer provided with a plurality of electrical connection pads, intended to connect with the electrical connection pins of the first wafer,
- and means for sealing the two wafers.
The invention also relates to an associated interconnection process for such a microcomponent.
Current techniques
In the domain of integrated circuits, notably for chip cards, the production of microcomponents using two wafers, each containing part of an electronic circuit is a recognised process. By wafer is meant any element that could form part of the microcomponent - that is a part of an electronic circuit, an electronic circuit, a single substrate, etc.
To operate, the two wafers of the microcomponent must be interconnected to each other. For safety reasons, it is preferable to have the wafers anchored to each other such that the separation of the two wafers destroys one of them. The search to find the best possible interconnection between the wafers of a microcomponent is an acknowledged issue in the industry, relating to issues of conditioning during the manufacture of the microcomponent and issues of security, notably against all types of chemical, physical and energy attacks.
The article "Localized micro-inserts connection for smart card secure micro packaging" by J. Brun, et al. (7th IEEE CPMT International Conference on High Density Microsystem Design and Packaging and Component Failure Analysis, June 27-30, 2005, Shanghais, China) describes a specific process for the interconnection of the two wafers of a microcomponent.
In figures 1 to 3, representing the various stages in a interconnection process for a microcomponent 1 and according to an existing process (figure 3), microcomponent 1 consists of a first wafer 2, for instance a silicon substrate with a CMOS circuit, consisting of a first side 3 on which there are the electrical connection pads 4. A plurality of electrical connection pins 5 are then formed on the electrical connection pads 4 of the first wafer 2. A layer 6 of a sealing material is then applied to the first side 3 of the first wafer 2 (figure 1).
In figure 2, a second wafer 7, for instance a silicon substrate provided with a CMOS circuit, consists of a plurality of electrical connection pads 8, intended to cooperate with the electrical connection pins 5 of the first wafer 2. The sealing layer 6 is structured, preferably, around the electrical connection pins 5 of the first wafer 2, such that they are awaiting cooperation with the electrical connection pads 8 of the second wafer 7.
The interconnection process for wafers 2 and 7 of the microcomponent 1 thus consists of placing the electrical connection pads 8 of the second wafer 7 in front of the electrical connection pins 5 of the first wafer 2 (figure 2).
In figure 3, the second wafer 7 is then sealed to the first wafer 2, by means of layer 6 of the sealing material, for example by thermocompression. The electrical connection pins 5 of the first wafer 2 are in contact with the electrical connection pads 8 of the second wafer 7 and sealing material layer 6 is distributed between the electrical connection pins 5 of the first wafer 2. The microcomponent 1 thus assembled now has its two wafers 2 and 7 interconnected by means of the electrical connection pins 5 and anchored by sealing layer 6.
However, a microcomponent assembled using an interconnection process such as that described above does not have optimum characteristics in terms of the electrical connections and mechanical solidity, notably with regard to the location of the pins relative to the electrical connection pads. In addition, such a microcomponent does not provide sufficient guarantees in terms of issues relating to security, concerning the coming apart of the wafers of the microcomponent.
Purpose of the invention
The purpose of the invention is to resolve the above mentioned drawbacks and is intended to produce a microcomponent consisting of two interconnected wafers, simple to produce and achieving a good mechanical solidity between the wafers and an optimum electrical connection between the two wafers, whilst satisfying the security criteria aimed at preventing the deterioration of the microcomponent.
The subject of the invention is characterised by the fact that the second wafer has a plurality of interconnection pins, located on a first side of the second wafer, opposing the first side of the first wafer.
According to an embodiment, the first interconnection pins of the second wafer are formed on the electrical connection pads of the second wafer, with the first interconnection pins being positioned facing the electrical connection pins of the first wafer and coming into contact by nesting one within the other.
According to another embodiment, the first wafer has additional pins, formed on the support pads of the first wafer and act to provide the basis for the mechanical support.
According to another embodiment, the second interconnection pins on the second wafer, formed on the support pads of the second wafer, act as mechanical anchoring pins, facing the sealing material.
According to a preferred mode of realisation, each pad is associated with a bi-dimensional matrix of pins.
The purpose of the invention is also for the realisation of an interconnection process with the assembling and anchoring of a first wafer and a second wafer to form a microcomponent, with the first and second wafers being anchored and interconnected to each other, with the process comprising at least the following steps:
- the formation of pins of the first wafer on the pads of a first side of the first wafer,
- the formation of pins of the second wafer on the pads of a first side of the second wafer,
- the first sides of the first and second wafers facing each other and said pins providing the electrical connection and/or reinforcing the anchoring of said wafers.
Summary description of the drawings
The other advantages and characteristics will be identified more clearly in the following description of the specific details for the forming of the invention given by way of non-limiting examples and represented in the appended drawings, in which:
Figures 1 to 3 are schematic representations of various stages of a process for the interconnection by assembling and sealing of two wafers of a microcomponent in application of the existing state of the art.
Figure 4 is a schematic representation of a first embodiment of a microcomponent according to the invention, before the assembling and sealing of its wafers.
Figure 5 is a highly schematic representation of a detailed section of the nesting pins of the microcomponent according to figure 4.
Figure 6 is a schematic representation of a variant for the formation of a microcomponent according to the invention, before the assembling and sealing of its wafers.
Figure 7 is a schematic representation of another variant for the formation of a microcomponent according to the invention, before the assembling and sealing of its wafers.
Figures 8 and 9 are each highly schematic representations of a detailed section of the nesting in the variants of pins of a microcomponent according to the invention.
Description of specific modes for the formation
In the specific embodiments as shown in figures 4 to 9, microcomponent 1 has a plurality of interconnection pins, formed on a first side, side 9 of the second wafer 7, intended to face the first side 3 of the first wafer 2. In figures 4, 6 and 7, the various embodiments of the microcomponent 1 are shown before assembly and sealing of wafers 2 and 7 of microcomponent 1.
In the specific embodiment of the microcomponent 1 , represented in figure 4, the second wafer 7 has first interconnection pins 10, formed on electrical connection pads 8 of the second wafer 7. The first side 9 of the second wafer
7 is placed opposite the first side 3 of the first wafer 2 and the interconnection pins 10 of the second wafer 7 face the electrical connection pins 5 of the first wafer 2.
In figure 4, the electrical connection pads 8 and the interconnection pins 10 of the second wafer 7 are slightly offset relative to the electrical connection pads 4 and the electrical connection pins 5 of the first wafer 2. During the assembly and anchoring of the microcomponent 1 , the interconnection pins 10 of the second wafer 7 and the electrical connection pins 5 of the first wafer 2 come into contact by nesting with each other (figure 5). The interconnection pins 10 of the second wafer 7 and the electrical connection pins 5 of the first wafer 2 then act to provide an electrical contact between the two wafers 2 and 7.
In addition, microcomponent 1 can have a passivation layer (not shown in figure 4), formed conventionally on the first side 9 of the second wafer 7, preferably prior to the formation of the electrical connection pads 8, and intended particularly to protect the first side 9 of the second wafer 7. The interconnection pins 10 of the second wafer 7 must thus be long enough to project through this passivation layer and overcome the disadvantages of such passivation layer.
Indeed, as shown in figure 2, a passivation layer 18, formed on the first side 9 of the second wafer 7 and structured around the electrical connection pads
8 of the second wafer 7, can result notably in a poor electrical contact, in the event of an incorrect alignment of the electrical connection pins 5 of the first wafer 2 with the electrical connection pads 8 of the second wafer 7.
In figure 5, the nesting of the electrical connection pins 5 of the first wafer 2 and the interconnection pins 10 of the second wafer 7 is shown highly schematically. The nesting consists of placing in contact at least part of an electrical connexion pin 5 of the first wafer 2 with at least part of an interconnection pin 10 of the second wafer 7.
The interconnection pins 10 associated with each connection pad 8 of the second wafer 7 and the electrical connection pins 5 associated with each electrical connection pad 4 of the first wafer 2 are distributed, preferably, in accordance with the bi-dimensional matrices. At least a sufficient number of pins 5, 10 thus enable the establishing of an optimum contact between wafers 2 and 7.
By way of example, electrical connection pins 5 and the interconnection pins 10 of the second wafer 7 are cylindrical. The electrical connection pins 5 of the first wafer 2 have a height hi of approximately 3μm to 9μm and a width L1 of approximately 2/vm to 5μm. Interconnection pins 10 of the second wafer 7 have a height h2 of approximately 2μm and a width L2 of approximately 2//m. Electrical connection pins 5 of the first wafer 2 and interconnection pins 10 of the second wafer 7 nest, for example, with an overlay height H of approximately 0.5μm to 1μm.
In the alternative embodiment of the microcomponent 1 , shown in figure 6, the second wafer 7 has second interconnection pins 11 , formed on the support pads 12 formed on the first side 9 of the second wafer 7. The second interconnection pins 11 of the second wafer 7 constitute mechanical anchoring pins, facing the sealing layer 6 and intended to work with sealing layer 6 during the assembly of wafers 2 and 7 of the microcomponent 1. The second interconnection pins 11 are, preferably, identical to the first interconnection pins 10, as shown in figure 5.
In figure 6, the second interconnection pins 11 are intended solely for ensuring an optimum mechanical anchoring of the two wafers 2 and 7 of the microcomponent 1. The electrical connection of the microcomponent 1 is then achieved by electrical connection pins 5 of the first wafer 2, working with the electrical connection pads 8 of the second wafer 7.
In an alternative embodiment not shown the second interconnection pins 11 , as shown in figure 6, can also be formed on the support pads 12 formed on the first side 9 of the second wafer 7 of the microcomponent 1 as shown in figure 4. The same microcomponent 1 then has both the first interconnection pins 10 of the second wafer 7, for the electrical connection of wafers 2 and 7 (figure 4), and the second interconnection pins 11 of the second wafer 7, for the mechanical anchoring of the second wafer 7 to the first wafer 2 (figure 6).
In the alternative embodiment of the microcomponent 1 , shown in figure 7, the first wafer 2 of the microcomponent 1 has electrical connection pins 5, mating both with the electrical connection pads 8 of the second wafer 7, shown on the right-hand side of the first wafer 2, and with the first interconnection pins 10 of the second wafer 7, shown on the left-hand side of the first wafer 2.
The electrical connection pads 4 of the first wafer 2 are connected to the corresponding electrical circuits (not shown) by means, for example, of electrical connection tracks 13. The electrical connection pads 8 of the second wafer 7 are linked to the corresponding electrical circuits (not shown) by means, for example, of electrical connection tracks 14.
In figure 7, the first wafer 2 of the microcomponent 1 also has additional pins 15, on the support pads 16 formed on the first side 3 of the first wafer 2. The additional pins 15 of the first wafer 2 act as mechanical support elements for the microcomponent 1 , performing notably the role of spacers for the assembling of the two wafers 2 and 7. The additional pins 15 can be nested, as a preference, with the additional interconnection pins 17 of the second wafer 7, formed on the support pads 12 on the first side 9 of the second wafer 7.
The nesting of the additional pins 15 and 17 is thus done in the same way as for the nesting of the electrical connection pins 4 and the interconnection pins 10, as shown in figures 4 and 5. Additional pins 15 and 17 thus act solely as mechanical support elements for microcomponent 1 and act as spacers and thickness shims for the microcomponent 1.
Furthermore, the additional pins 15 and 17 enable more specifically the increasing of the security of the interconnection between wafers 2 and 7. By way of example, in the event of polishing action on the microcomponent 1 , the additional pins 15, 17 enable notably the prevention of any functional disassembling of the two wafers 2, 7 of the microcomponent 1. Such additional pins 15, 17 thus maximise the security with regard to the deterioration of one of the wafers 2, 7 of the microcomponent 1 in the event of polishing.
In an alternative embodiment not shown the second interconnection pins 11 , intended for anchoring in sealing layer 6, as shown in figure 6, can be formed on the other support pads 12 on the first side 9 of the second wafer 7 of a microcomponent 1 as shown in figure 7. In this case, the mechanical anchoring of the two wafers 2 and 7 is strengthened because wafers 2 and 7 are held by the additional pins 15 of the first wafer 2 and the additional pins 17 of the second wafer 7 and the second interconnection pins 11 of the second wafer 7, anchored in sealing layer 6.
In another variant not shown, a multitude of additional pins 15, 17, and/or pins 11 provided for the mechanical anchoring in the sealing layer, are directly placed on part or on the whole of the surface of at least one wafer 2, 7. This multitude of pins thus allows the achievement of a mechanical anchoring by means of nesting the pins one with the other. The fact of including a large number of small size pins 15, 17, 11 , on the surface of the wafers enables a reduction in the assembling energy by limiting the efforts in terms of the nesting.
Whatever the embodiment of the microcomponent 1 (figures 4, 6 and 7), all of the pins 5, 15 of the first wafer 2 are, preferably, of the same shape and the same size and all of the pins 10, 11 , 17 of the second wafer 7 are also all, preferably, of the same shape and the same size.
Furthermore, each pad of the first wafer 2, that is the electrical connection pads 4 and the support pads 16, and each pad of the second wafer 7, that is the electrical connection pads 8 and the support pads 12, are associated with a bi-dimensional matrix of corresponding pins 5, 10, 11 , 15, 17.
As described previously, of all the pins 5, 10, 11 , 15, 17 in a matrix, some of these may not be in contact with other corresponding pins (figure 5). This does not affect the contact and the electrical connection, because a sufficient and minimum number of pins are in contact, thanks to the specific arrangement on the basis of a bi-directional matrix.
In addition, the bi-dimensional matrices of pins 5, 10, 11 , 15, 17 can take any shape, for example, square, rectangular, circular or even dissymmetric, provided they enable a good quality contact or an sufficient contact between pins 5, 10, 11 , 15, 17.
Further, all of the pins 5, 10, 11 , 15, 17 have, preferably, the same section, for example square, rectangular, or circular, and are made of the same material, for example nickel or copper. A free end of each of the pins 5, 10, 11 , 15, 17 can also include a finishing coating of gold. There is now a more detailed description of an interconnection process by assembling and sealing the first 2 and second 7 wafers of the microcomponent 1 with regard to figures 4 to 7.
In figures 4, 6 and 7, pins 5, 15 of the first wafer 2 are formed on the corresponding pads 4, 16 of the first wafer 2, preferably, by electrochemical growth. Pins 10, 11 , 17 of the second wafer 7 are formed on the corresponding pads 8, 12 of the second wafer 7, preferably, by chemical growth, also known as "electroless" deposition.
Pins 5, 15 of the first wafer 2 are thus hard, and pins 10, 11 , 17 of the second wafer 7 are thus soft, relative to pins 5, 15 of the first wafer 2. Pins 5, 15 of the first wafer 2 are, preferably, higher and harder than pins 10, 11 , 17 of the second wafer 7, for safety reasons, and pins 10, 11 , 17 of the second wafer 7 are softer than pins 5, 15 of the first wafer 2, notably to enable their hardening by annealing after sealing, in order to optimise the anchoring of the two wafers 2 and 7.
Moreover, pins 10, 11 , 17 of the second wafer 7 can be produced simultaneously with pins 5, 15 of the first wafer 2, during a same production step of wafers 2 and 7, or can be produced after pins 5, 15 of the first wafer 2, during the two succeeding fabrication stages.
In other embodiments, it is possible to form both the pins 5, 15 of the first wafer 2 and pins 10, 11 , 17 of the second wafer 7 by electro-chemical growth, as all of the pins 5, 10, 11 , 15, 17 of the microcomponent 1 are hard, or by chemical growth, as all of the pins 5, 10, 11 , 15, 17 of the microcomponent 1 are soft.
In another variant, pins 5, 15 of the first wafer 2 can be formed by chemical growth and pins 10, 11 , 17 of the second wafer 7 can be formed by electro- chemical growth, as pins 5, 15 of the first wafer 2 are thus soft relative to pins 10, 11 , 17 of the second wafer 7.
After the formation of pins 5, 10, 11 , 15, 17 on wafers 2 and 7, a sealing layer
6, for example, in a polymer material is deposited, for example, on the first side 3 of the first wafer 2. The layer 6, for example, in polyimide is then, preferably, structured by means of masks and etching stages, notably around pins 5, 15 of the first wafer 2.
Then, the first side 9 of the second wafer 7 is aligned relative to the first side 3 of the first wafer 2 and the assembly and sealing of the second wafer 7 on the first wafer 2 is performed, for example, by thermocompression, eutectic soldering, gluing, etc.
In a variant not shown it is possible to perform the sealing by means of a liquid glue, for example epoxy resin, replacing sealing layer 6. The process consists of applying the liquid glue, for example on the first side 3 of the first wafer 2, and of performing the assembly and sealing of the two wafers 2 and
7, for example by thermocompression or just using cold compression.
Furthermore, if the pins 10, 11 , 17 of the second wafer 7 are softer than pins 5, 15 of the first wafer 2 and have a relatively short height h2, they can be hardened by an annealing phase, after the sealing of wafers 2 and 7.
Regardless of the mode of production of the microcomponent 1 , such as described above, the microcomponent 1 notably provides a reliable and optimum interconnection in terms of the electrical connection and mechanical anchoring, thanks namely to the interconnection pins forming both means of electrical connection and means of mechanical anchoring. Furthermore, the protection against disassembly of wafers 2 and 7 is ensured, namely thanks to the additional pins 15 of the first wafer 2 and to the additional interconnection pins 17 of the second wafer 7. In addition, the presence of interconnection pins on each active side of the microcomponent 1 , that is on the first side 3 of the first wafer 2 and on the first side 9 of the second wafer 7, increases the capacity and the reliability of the microcomponent 1.
Furthermore, the distribution of pins 5, 10, 11 , 15, 17 in a bi-dimensional matrix enables the optimising of the large-scale electrical contact. The connection surface of the pins, from a mechanical and electrical point of view, is greater, more robust and offers increased flexibility of contact.
In general, during the nesting of the interconnection and additional pins, regardless of their functions, these latter are subject to a deformation in their topmost sections. Depending on the materials used and the shape of the pins, it is possible to get localised deformations on the pins of just one of the wafers, or of the two wafers.
The electrical connection is achieved, at the level of the connection pads 4, 8 of the two wafers, through contact between the interconnection pins 5, 10 of the two wafers. The embodiments as described above do not require huge accuracy in the aligning of the connection pads 4, 8 with regard to each other. Indeed, given that several interconnection pins 5, 10 are supported by each connection pad 4, 8, it is sufficient that at least two interconnection pins 5, 10 are nested to achieve an electrical connection. The assembling can therefore include a slight offset in the connection pads 4, 8 with regard to each other.
Furthermore whatever the embodiment, the assembling does not require the use of assembly spacers to maintain the assembly height, as this is fixed by the assembly conditions, that is by the force applied, the temperature, shape of the pins, the materials used and the materials used for the sealing layer. In addition, this interconnection process for wafers 2, 7 of the microcomponent 1 is easily implemented and ensures a reliable interconnection in terms of the electrical connection and mechanical anchoring. The sealing of wafers 2 and 7 is irreversible and the security of the assembling is notably ensured by means of the additional pins 15 and 17.
The conditioning of the microcomponent 1 also achieves an optimum efficiency, thanks notably to the simplicity of the interconnection process according to the invention.
The invention is not limited to the various embodiments as described above. The shape and the dimensions of the pins 5, 10, 11 , 15, 17 can be different, provided that the pins ensure the achievement of an optimum electrical connection and mechanical interconnection.
In figure 8, showing the nesting of pins 5 and 10 of a microcomponent 1 as shown in figure 4, the electrical connection pins 5 of the first wafer 2 can notably conform according to a body, for example, in a cylindrical shape, with an enlarged, domed and malleable free end 19, in the general shape of a cap. The interconnection pins 10 of the second wafer 7 have, for example, a bevelled end 20, intended to mate with the enlarged ends 19 of the electrical connection pins 5 of the first wafer 2. During the nesting, the enlarged ends 19 of the electrical connection pins 5 are malleable, as shown by the dotted lines in figure 8, under the effect of the bevelled end 20 of the interconnection pins 10. This configuration enables namely the optimising of the electrical contact between the pins 5 and 10.
In figure 9, the interconnection pins 10 of the second wafer 7 may be identical with the electrical connection pins 5 of the first wafer 2, shown in figure 8, and can have an enlarged, domed and malleable end 19. During the nesting of pins 5 and 10, the enlarged ends 19 distort, in order for the enlarged ends 19 of interconnection pins 10 of the second wafer 7 to come within the enlarged ends 19 of the electrical connection pins 5 of the first wafer 2.
In other variants not shown, the additional pins 15 of the first wafer 2, the additional interconnection pins 17 and the second interconnection pins 11 of the second wafer 7 can also be the same shape as the electrical connection pins 5 of the first wafer 2 and the first interconnection pins 10 of the second wafer 7, as shown in figures 8 and 9.
The specific shape of the pins shown in figures 8 and 9 namely helps to ensure the correct alignment and the correct nesting of the pins, as well as an optimum compensation for the effects of the thermal and mechanical dilatation of the materials of which the pins 5, 10, 11 , 15, 17 and the wafers 2, 7 are made.
For the nesting of the pins (figures 5, 8 and 9), the height of the covering H can vary, depending on the deformation and the various heights to be taken up by the pins 10, 11 , 17 of the second wafer 7, during the sealing of the microcomponent 1.
The pads 4, 8, 12, 16 of wafers 2 and 7 can be formed by the metallization of the surface and etching. Their exact location on the first side 3 of the first wafer 2 and on the first side 9 of the second wafer 7 is not important, provided that they allow the achievement of a good interconnection between the two wafers 2, 7.
The microcomponent 1 shown in figures 4 and 6 can have electrical connection tracks, such as shown in figure 7, linking the corresponding pads 4, 8 with the associated electrical circuits (not shown in figures 4 and 6).
It is possible to have a single microcomponent 1 deriving the benefits of having all of the types of pins, that is the electrical connection pins 5 on the first wafer 2 mating with interconnection pins 10 of the second wafer 7 and with the electrical connection pads 8 of the second wafer 7, the additional pins 15 on the first wafer 2, mating with the additional pins 17 of the second wafer 7, and the second interconnection pins 11 on the second wafer 7, mating with the sealing layer 6 for the mechanical anchoring.
The microcomponent 1 is used namely in the field of integrated circuits, and more specifically for chip cards.

Claims

Claims
1. Microcomponent (1) comprising:
- a first wafer (2) provided with a plurality of electrical connection pins (5), formed on a first side (3) of the first wafer (2),
- a second wafer (7) provided with a plurality of electrical connection pads (8) on which are formed first interconnection pins (10) intended to cooperate with the electrical connection pins (5) of the first wafer (2),
- and the means for the seal (6) between the two wafers (2, 7), microcomponent characterized in that :
- the first interconnection pins (10) of the second wafer and the electrical connection pins (5) of the first wafer (2) come into contact by nesting one with the other to ensure an electrical connection, in that
- the first wafer (2) further comprises, on its first side (3), additional pins (15),
- the second wafer (7) further comprises additional pins (17),
- and in that the additional pins (17) of the second wafer (7) and the additional pins (15) of the first wafer (2) cooperate by nesting one with each other, acting as spacers for the assembly of the two wafers.
2. Microcomponent according to claim 1 , in which the additional pins (15) of the first side (3) of the first wafer (2) are located on support pads (16), and the additional pins (17) of the second wafer (7) are located on support pads (12).
3. Microcomponent according to one of the claims 1 to 2, in which the electrical connection pins (5) of the first wafer (2) and the first interconnection pins (10) of the second wafer (7) nest in an overlay height (H) of approximately 0.5μm to 1μm. I B
4. Microcomponent according to claim 1 , in which the second interconnection pins (11) of the second wafer (7), formed on the support pads (12) of the second wafer (7), act as mechanical anchoring pins, and facing the sealing means (6).
5. Microcomponent according to one of the claims 1 to 4, in which the pins (5, 15) of the first wafer (2) are hard and the pins (10, 11 , 17) of the second wafer (7) are soft.
6. Microcomponent according to one of the claims 1 to 5, in which the pins (5, 10, 11 , 15, 17) are made of nickel.
7. Microcomponent according to one of the claims 1 to 5, in which the pins (5, 10, 11 , 15, 17) are made of copper.
8. Microcomponent according to one of the claims 6 and 7, in which a free end of each pin (5, 10, 11 , 15, 17) has a finishing layer of gold.
9. Microcomponent according to one of the claims 1 to 8, in which each pin (5, 10, 11 , 15, 17) has an enlarged domed free end (19).
10. Microcomponent according to one of the claims 1 to ,9, in which the pins (5, 15) of the first wafer (2) have a height (hi) of approximately 3μm to 9μm and a width (L1) of approximately 2μm to 5μm and the pins (10, 11 , 17) of the second wafer (7) have a height (h2) of approximately 2μm and a width (L2) of approximately 2μm.
11. Microcomponent according to one of the claims 1 to 10, in which each pad (4, 8, 12, 16) is associated with a bi-dimensional matrix of pins (5, 10, 1 1 , 15, 17).
12. Interconnection process by assembling and sealing of a first wafer (2) and of a second wafer (7) forming a microcomponent (1), the first (2) and second (7) wafers being sealed and interconnected with each other, characterized in that it comprises at least the following steps: - the formation of pins (5, 15) of the first wafer (2) on pads (4, 16) of the first side (3) of the first wafer (2),
- the formation of pins (10, 11 , 17) of the second wafer (7) on pads (8, 12) on the first side (9) of the second wafer (7),
- the first sides (3, 9) of the first (2) and second (7) wafers facing each other and said pins (5, 10, 11 , 15, 17) ensuring the electrical connection and reinforcing the sealing of said wafers (2, 7).
13. Interconnection process according to claim 12, which comprises the formation by electro-chemical growth of pins (5, 10, 11 , 15, 17) of at least one wafer (2, 7).
14. Interconnection process according to one of the claims 12 and 13, which comprises the formation by chemical growth of pins (5, 10, 11 , 15, 17) of at least one wafer (2, 7).
15. Interconnection process according to one of the claims 12 to 14, which comprises, after the formation of the pins (5, 10, 11 , 15, 17):
- the depositing of a sealing layer (6), made of polymer material, on the first side (3) of the first wafer (2), - the assembling and sealing of the wafers (2, 7).
16. Interconnection process according to claim 15, which comprises, between the depositing of the sealing layer (6) and the assembly and the sealing of the wafers (2, 7), the structuring of this sealing layer (6).
17. Interconnection process according to one of the claims 12 to 14, which comprises, after the formation of the pins (5, 10, 11 , 15, 17): the depositing of a liquid glue, on the first side (3) of the first wafer (2), the assembling and the sealing of the wafers (2, 7).
EP06831789A 2005-12-22 2006-12-19 Microcomponent comprising two wafers interconnected by pins and the associated interconnection process Withdrawn EP1964173A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0513197A FR2895567B1 (en) 2005-12-22 2005-12-22 MICRO COMPONENT COMPRISING TWO PLATES INTERCONNECTED BY PICOTS AND ASSOCIATED INTERCONNECTION METHOD
PCT/IB2006/003741 WO2007072202A1 (en) 2005-12-22 2006-12-19 Microcomponent comprising two wafers interconnected by pins and the associated interconnection process

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EP1964173A1 true EP1964173A1 (en) 2008-09-03

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WO (1) WO2007072202A1 (en)

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FR2932004B1 (en) * 2008-06-03 2011-08-05 Commissariat Energie Atomique STACKED ELECTRONIC DEVICE AND METHOD FOR PRODUCING SUCH AN ELECTRONIC DEVICE
DE102009013826A1 (en) * 2009-03-18 2011-03-10 Michalk, Manfred, Dr. Circuit arrangement, method for electrical and / or mechanical connection and apparatus for applying connecting elements
US10137789B2 (en) * 2016-07-20 2018-11-27 Ford Global Technologies, Llc Signal pin arrangement for multi-device power module
WO2018145968A1 (en) * 2017-02-09 2018-08-16 Siemens Aktiengesellschaft Power module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362437B1 (en) * 1999-06-17 2002-03-26 Nec Corporation Mounting structure of integrated circuit device having high effect of buffering stress and high reliability of connection by solder, and method of mounting the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5411400A (en) * 1992-09-28 1995-05-02 Motorola, Inc. Interconnect system for a semiconductor chip and a substrate
US6130148A (en) * 1997-12-12 2000-10-10 Farnworth; Warren M. Interconnect for semiconductor components and method of fabrication
US6297063B1 (en) * 1999-10-25 2001-10-02 Agere Systems Guardian Corp. In-situ nano-interconnected circuit devices and method for making the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362437B1 (en) * 1999-06-17 2002-03-26 Nec Corporation Mounting structure of integrated circuit device having high effect of buffering stress and high reliability of connection by solder, and method of mounting the same

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WO2007072202A1 (en) 2007-06-28
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