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EP1525610A1 - Procede de structuration verticale de substrats en technique des semiconducteurs par depot non conforme - Google Patents

Procede de structuration verticale de substrats en technique des semiconducteurs par depot non conforme

Info

Publication number
EP1525610A1
EP1525610A1 EP03787693A EP03787693A EP1525610A1 EP 1525610 A1 EP1525610 A1 EP 1525610A1 EP 03787693 A EP03787693 A EP 03787693A EP 03787693 A EP03787693 A EP 03787693A EP 1525610 A1 EP1525610 A1 EP 1525610A1
Authority
EP
European Patent Office
Prior art keywords
cover layer
layer
depth
deposition
precursor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03787693A
Other languages
German (de)
English (en)
Inventor
Thomas Hecht
Matthias Goldbach
Uwe Schröder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1525610A1 publication Critical patent/EP1525610A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
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    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
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    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
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    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H10D1/665—Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
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Definitions

  • the invention relates to a method for structuring process surfaces of a substrate having a relief that are inclined and / or vertical and that extend in relation to the substrate surface to a relief depth with respect to a depth of coverage that is to be predetermined between the relief depth and the substrate surface.
  • the structuring of planar substrate surfaces which are horizontal to an afer surface is carried out by means of photolithographic processes in conjunction with selective etching processes.
  • reliefs with a pronounced topography are created on the wafer or substrate surface.
  • Such a relief also has vertical or inclined surfaces with respect to the substrate surface.
  • vertical or inclined process surfaces in order to differentiate the structures in their vertical extent functionally. Examples of this are the deep trench capacitor, the stack capacitor, and vertical transistor designs.
  • the structuring of reliefs in the direction vertical to the substrate surface is not directly possible using photolithographic processes.
  • Such vertical structuring is conventionally carried out with the aid of a suitable filler material which, as a mask, covers regions of the relief located below a depth of coverage during processing of unmasked regions.
  • Structuring a relief in the direction vertical to the substrate surface with respect to one between a substrate surface and a relief depth chosen then usually takes place according to one of the following two methods:
  • an oxide is to be deposited exclusively in a lower region of a relief which is arranged between the depth of coverage and the relief depth, the oxide is deposited or produced over the entire surface of the relief in a first step.
  • the relief is then completely filled with a suitable filler and then the filler is reduced to the depth of coverage. Exposed sections of the oxide are then removed and, as a last step, remanent sections of the filling material are completely removed.
  • an etching stop layer for example a nitride layer
  • a suitable filler material for example polycrystalline silicon
  • the filler material is etched back to the depth of coverage.
  • the nitride layer is now removed in the unmasked sections and an oxide is deposited or thermally generated in the exposed areas.
  • the oxide is then etched anisotropically. This is followed by the removal of the filler material and, as a last step, the complete removal of the etch stop layer.
  • PECVD plasma-based chemical vapor deposition processes
  • Thin layers are created on the surfaces of a relief, the thickness of which decreases with increasing depth on vertical or inclined surfaces.
  • the run-out of the layers produced in depth is difficult to control in these processes.
  • such layers have very thick distinguished between an end point in depth and an area near the substrate surface.
  • the silicon oxide grows on surfaces that are vertical or inclined to the substrate surface at a rate that decreases in relation to the relief depth, so that the layer thickness of the silicon oxide thus produced decreases in the direction of the relief depth.
  • TEOS tetraethylorthosilane
  • a cover layer is thus generated by a deposition process in a process chamber from precursor materials, a deposition of at least one of the precursor materials is restricted compared to a deposition of a complete cover layer, and thereby the cover layer is almost exclusively and with essentially uniform layer thickness is provided on the upper sections of the process areas arranged between the substrate surface and the depth of coverage.
  • a cover layer with an essentially uniform layer thickness is provided between the upper sections of the relief by means of the deposition process, for example an ALD process (atomic layer deposition).
  • ALD atomic layer deposition
  • Process parameters of the deposition process in particular a deposition time, a quantity of a precursor material deposited in the course of the deposition process and / or a chamber pressure in the process chamber are controlled in a manner that leads to incomplete coverage of the relief.
  • Such an incomplete, non-conformal covering layer (inconformal liner) produced according to the invention covers the relief only above the depth of coverage.
  • the cover layer has an essentially uniform layer thickness.
  • a first pre-stage material is fed to a process chamber in which the substrate is located.
  • the first precursor material is only deposited in designated (activated) sections of the substrate surface.
  • the first prepress material is usually modified. Are all activated sections with the modified prepress material covered, the first process phase of the deposition is completed and a monomolecular partial single cell layer is deposited from a modified precursor material on the substrate surface. Thereafter, non-separated portions of the first precursor material are removed from the process chamber by flushing with an inert gas and / or pumping.
  • a second pre-stage material is introduced into the process chamber, which deposits almost exclusively on the partial single-cell layer from the first pre-stage material.
  • the precursor materials are converted into the layer material.
  • a single layer (monolayer) of the layer to be produced is formed.
  • a process cycle of the ALD process is completed after the removal of non-deposited portions of the second pre-stage material from the process chamber. The process cycle is repeated until a layer of a predetermined layer thickness is formed from the individual layers deposited in each process cycle.
  • the prerequisite for this is that the precursor material is only offered in limited quantities, or the deposition process is terminated in good time before it is completely covered and the chamber pressure in the process chamber is selected so that a sufficiently slow diffusion of the precursor material into the depth of the relief is ensured.
  • the deposited layer is already a functional layer, any masking is not necessary.
  • the deposited layer can be a mask, with at least one etching back step for structuring the mask being saved compared to conventional methods.
  • the accuracy with which a predetermined depth of coverage can be achieved, with predetermined process parameters, depends on the total area of the relief to be covered on the substrate or wafer surface.
  • the total area to be covered becomes larger, since the relief in the horizontal extent is structured increasingly finer and denser and functional structures are increasingly realized on vertical surfaces.
  • a particular advantage of the method according to the invention lies in the fact that the accuracy with which a predetermined coverage depth can be achieved increases in the same way in the previously described development of integrated circuits.
  • the coverage depth is preferably set as a function of an exposure resulting from a product of a quantity or concentration of one of the precursor materials in the process chamber, a deposition time of the precursor material and a process pressure in the process chamber during the deposition.
  • At least one of the precursor materials preferably one with high Hem sticking coefficient offered in a smaller amount or concentration than would be necessary for complete coverage.
  • At least one process phase of a process cycle of the deposition process ends with the consumption of the scarce pre-stage material. There is advantageously no time monitoring of the deposition process. A total area covered by the generated cover layer and thus the depth of coverage correlates with the amount of the pre-stage material made available.
  • a particularly precise control and control of the deposition process results when at least one of the precursor materials is supplied by means of liquid injection. With this method, the amount of the previous material supplied and thus the coverage depth can be set very precisely.
  • the deposition time of at least one pre-stage material is checked during one process cycle of the deposition method.
  • the depth of coverage is set via the deposition time of the prepress material.
  • the method according to the invention is preferably adapted to different types of reliefs via the chamber pressure in the process chamber during the deposition, in particular of the precursor material with a high adhesive coefficient.
  • a non-conforming top layer is deposited on a flat relief that has structures with low aspect ratios and / or a high proportion of process surfaces inclined to the surface requires a lower chamber pressure for the same depth of coverage than a deposition on a deep relief with structures with a high aspect ratio.
  • a distribution device shown head extending over the entire substrate surface is provided for homogeneous distribution of at least the scarced precursor material over the entire substrate surface. This enables a uniform coverage depth to be achieved over an entire wafer surface.
  • the cover layer can already be a functional layer. However, it is also possible to use a cover layer produced in the manner mentioned as a mask. Compared to conventional methods for producing a mask for vertical structuring, there is at least no etching back and structuring of a mask material deposited over the entire surface.
  • a material forming the cover layer is provided as such with a high etching resistance to a material forming the lower sections of the process surfaces arranged between the relief depth and the depth of coverage.
  • the material forming the process areas in the lower sections can then be etched after depositing a cover layer with a high etching selectivity with respect to the cover layer, the etching being masked at least in sections by the cover layer.
  • a material which is substantially inert to an oxidation process is provided for the cover layer.
  • the material forming the process areas between the relief depth and the coverage depth is then oxidized by means of the oxidation process.
  • the oxidation process is masked at least in sections by the cover layer.
  • the cover layer is provided as a barrier layer against a doping process.
  • the material forming the process areas between the relief depth and the coverage depth is doped by means of the doping process, the doping process being masked at least in sections by the cover layer.
  • the cover layer is removed again after use as a mask.
  • the substrate in which the relief is made is composed of one or more layers of materials customary in semiconductor process technology. Common layer materials of the substrate are, for example, crystalline, polycrystalline or epitaxially grown silicon or silicon compounds.
  • HSG structures also form to a large extent on an inconsistent cover layer made of A1 2 0 3 .
  • An additional layer is therefore preferably provided before the application of the non-conforming cover layer, which is first masked with the non-conforming cover layer.
  • the non-conforming top layer is removed before process steps for which the properties of the material of the non-conforming top layer are disadvantageous and replaced by the additional layer underneath.
  • Preferred materials of the additional layer are silicon oxide and silicon nitride.
  • Possible materials of the non-conforming cover layer are those which are functionally suitable either as dielectric 'or conductive layers or as a mask. These include A1 2 0 3 , Hf0 2 , Zr0 2 , Ti0 2 , TiN, WN, SiN and La0 2 and other oxi- de rare earth.
  • the deposition typically takes place at a temperature between 25 and 800 degrees Celsius and a pressure between 0.13 Pa and 1013 hPa. Depending on the precursor materials selected, the temperature and pressure ranges must be restricted in a manner known to the person skilled in the art.
  • the precursor materials to be selected are in particular those which have a high adhesive coefficient or a low desorption coefficient.
  • tri-methyl aluminum is therefore preferably chosen as the first precursor material (precursor) and H 2 0 and / or 0 3 as the second precursor.
  • cover layer is hafnium oxide, with HfCl, Hf-t-butoxide, Hf-di-methyl-amide, Hf-ethyl-methyl-amide, Hf-diethyl-a id or Hf (MMP) as the first precursor and as second precursor H 2 0 and / or 0 3 is selected.
  • zirconium oxide is selected as the material of the cover layer
  • ZrCl or an organic Zr compound is preferably chosen as the first precursor and H 2 0 and / or 0 3 as the second precursor.
  • titanium oxide is formed from the first precursors TiCl 4 , Ti (OC 2 H 5 ) 4 or Ti (OCH (CH 3 ) 2 ) i and the second precursors H 2 0 and / or 0 3 as the material of the cover layer ,
  • cover layer is titanium nitride, which is formed from TiCl 4 and from NH 3 as precursors.
  • tungsten nitride is formed from the precursor materials WF ⁇ and NH 3 .
  • silicon nitride is preferably formed from the precursors SiH 2 , Cl 2 or NH 3 and / or N 2 H as the material of the cover layer.
  • silicon oxide as the material of the cover layer, using Si (NCO) or CH 3 OSi (NCO) 3 as the first precursor and H 2 0 and / or 0 3 as the second precursor.
  • the method according to the invention is in principle suitable for the vertical structuring of different types of reliefs. However, it is particularly suitable for structuring trenches which are formed in a substrate in a high aspect ratio. Especially in trenches with a high aspect ratio, the arrangement of the scarced precursor material is determined systematically from the substrate surface in a diffusion-determined manner.
  • the trenches are functionally formed as capacitors. If the capacitors have a dielectric collar (collar) that closes around the trench at approximately the depth of coverage, the collar can serve as an already adjusted edge of a mask. For a mask arranged in the upper trench region, there is then a lower accuracy requirement for its expansion in the direction of the relief depth. If, according to the method according to the invention, a cover layer is now arranged in an upper trench region, then an oxidation process of a material forming a trench wall in the lower trench region is controlled and then the cover layer is removed, this results in a particularly simple method for arranging an oxide layer as a cover layer in a lower one Trench area trench formed in a substrate. On the other hand, the formation of an oxide layer as a cover layer in the upper trench region results in a particularly simple method for producing an oxide layer in the upper trench region of a trench formed in a substrate.
  • FIG. 1 shows schematic cross sections through a section of a substrate in the course of a first exemplary embodiment of the method according to the invention.
  • FIG. 2 shows schematic cross sections through a section of a substrate in the course of a second exemplary embodiment of the method according to the invention.
  • FIG. 3 shows schematic cross sections through a section of a substrate in the course of a third exemplary embodiment of the method according to the invention.
  • FIG. 4 shows schematic cross sections through a section of a substrate in the course of a fourth exemplary embodiment of the method according to the invention.
  • FIG. 5 shows a schematic cross section through a capacitor structure produced according to the invention.
  • FIGS. La to le show successive phases of structuring a trench wall 43 of a trench 4 made in a substrate 1.
  • a substrate 1 consisting of a semiconductor substrate 11 and an auxiliary layer 12 arranged on the semiconductor substrate 11 has a horizontal substrate surface 101, from which a trench 4 extends into the substrate surface 101 extends in the vertical direction up to a relief depth 103 in the substrate 1.
  • the trench wall 43 forms vertical process surfaces 2 with respect to the substrate surface 101.
  • a coverage depth 102 is specified up to or from which the relief formed by the trench 4 is to be covered with a cover layer 3 to be formed below. The depth of coverage 102 divides the trench 4 into one towards the substrate surface
  • upper sections 21 of the process area 2 are arranged between the substrate surface 101 and the coverage depth 102 and lower sections 22 of the process area 2 between the coverage depth 102 and the relief depth 103.
  • a cover layer 3 is produced on the substrate surface 101 and the upper sections 21 of the process surfaces 2. Due to the high coefficient of adhesion of at least one of the precursor materials, the cover layer 3 grows from the substrate surface 101 in the direction of the relief depth 103. This applies to every molecular partial cell. The growth of the cover layer 3 in the direction of the relief depth 103 is restricted. For example, a process quantity of the preliminary material with a high adhesion coefficient is limited so that the cover layer 3 per individual layer does not grow further than the depth of coverage 102. In addition, the deposition process can be terminated for each individual layer of the top layer 3 when the coverage depth 102 is reached.
  • cover layer 3 is shown in FIG. 1b.
  • the cover layer 3 extends, apart from a short, wedge-shaped transition region 31, above the depth of coverage 102 uniformly and with the same layer thickness. Below the level of coverage
  • the cover layer 3 functions as an etching and doping mask.
  • an etching (bottle etch) takes place first in the lower trench region 42.
  • the trench 4 in the lower trench region 42 is widened.
  • FIG. 1 d This is followed by a gas phase doping, shown schematically in FIG. 1 d, of an area 13 of the semiconductor substrate 11 after previous HSG deposition (hemispherical silicone grain) with optional subsequent etching back.
  • the doped region 13 produced in this way corresponds to a low-resistance connection of an outer electrode (buried plate) when used in the production of DT (deep trench) DRAM memory cells.
  • FIG. 1 is structured in the vertical direction to the substrate surface 101 by an etching step which only acts on the lower trench region 42 and a doping step which likewise only acts on the lower trench region 42.
  • FIGS. 2a to 2c A further exemplary embodiment for structuring a trench 4 is shown in FIGS. 2a to 2c.
  • the trench 4 of FIG. 2 has a collar 44 arranged in the upper trench region 41, which is embedded in the semiconductor substrate 11 and surrounds the trench 4.
  • FIG. 2a shows a trench 4, which is introduced into a substrate 1 from a substrate surface 101 to a relief depth 103 and has a collar 44 in the upper trench region 41.
  • sections 411 of the trench wall 43 between the substrate surface 101 and an upper edge of the collar 44 are to be masked.
  • an incomplete cover layer 3 (non-conformal liner) is now produced, which only covers the trench wall 43 up to a depth of coverage 102.
  • both the cover layer 3 and the collar 44 act as a mask.
  • the method according to the invention is particularly suitable for this example, since a precise position of the upper edge of an etching and doping process is already defined by a lower edge of the collar 44.
  • the cover layer 5 only covers a portion 411 of the trench wall 43 in the upper trench region 41 located between the substrate surface 101 and an upper edge of the collar 44. A precise vertical adjustment of the coverage depth 102 by the deposition process is not necessary, provided that it is ensured that the cover layer 3 runs out in the area of the collar 44. After bottle etching and subsequent gas phase doping, the cover layer 3 is removed, a dielectric layer (node dielectric) is produced on the trench wall 43 and the trench 4 is then filled with polysilicon.
  • FIGS. 3a to 3c show, as a further exemplary embodiment of the method according to the invention, the arrangement of electrodes and a dielectric in the course of processing stacked capacitors in different phases.
  • auxiliary layer 12 for example made of silicon dioxide, is first applied to the semiconductor substrate 11.
  • the semiconductor substrate 11 forms together with the auxiliary layer 12 a substrate 1, into which trenches 4 are introduced from a substrate surface 101.
  • an inconsistent, conductive covering layer 31 and an inconsistent dielectric covering layer 32 are first produced one after the other.
  • the non-conforming dielectric cover layer 32 is drawn deeper into the trenches 4 than the non-conforming conductive cover layer 31.
  • FIG. 3a The resulting arrangement is shown schematically in FIG. 3a.
  • the non-conforming dielectric cover layer 32 is then etched back to about the upper edge of the trench 4 (spacer etch) and a conformal conductive cover layer 33, for example made of doped polysilicon, is applied.
  • the stacked capacitor is electrically connected to the doped region 54 of the transistor 5 with the conformal conductive cover layer 33.
  • the conformal conductive cover layer 33 is first etched back up to approximately the upper edge of the trench 4 and then a conformal dielectric cover layer 34 and a second conformal conductive cover layer 35 are deposited.
  • the arrangement shown in FIG. 3c results.
  • the first conformal conductive cover layer 33 forms a first electrode (node electrode) of the stacked capacitor embodied in the trench 4 which is connected to a doped region 54 of the transistor 5.
  • the non-conformally deposited conductive cover layer 31 and the second conformally deposited conductive cover layer 35 form an outer and inner counterelectrode which are deposited by the non-conformally or conformally dielectric cover layers 32, 34 are insulated from the first electrode 33.
  • the process according to the invention for the deposition of an inconsistent top layer results in a very substantial simplification of the process flow.
  • a multi-stage process sequence consisting of depositing a filler material, etching back the filler material and completely removing the filler material is unnecessary for both non-conformally deposited cover layers.
  • 4a shows the additional layer 7 which lines the trench 4 and on which an non-conformal cover layer 3, which is deposited according to the invention up to a depth of coverage 102, is arranged.
  • the additional layer 7 below the covering depth 102 is subsequently removed and the trench 4 is widened by etching in a trench region 42 arranged below the covering depth 102 (wet bottle etch). A gas phase doping is then carried out, which is masked by the non-conformally deposited cover layer 3.
  • FIG. 4b This results in the structure shown in FIG. 4b, in which the trench 4 is lined in an upper trench region 41 above the depth of coverage 102 with the additional layer 7 and the non-conforming cover layer 3 lying thereon.
  • the semiconductor substrate 11 is doped in the regions 13 adjoining the lower trench region 42.
  • the non-conforming cover layer 3 is then removed and HSG formation with subsequent etching back is carried out, which results in the structure shown in FIG. 4c.
  • the trench 4 is lined with the additional layer 7 in the upper trench region 41 and has HSG structures 6 in the lower trench region 42. Subsequently, the additional layer 7 is removed and a dielectric is deposited.
  • the HSG formation according to the method shown in FIG. 4 is only carried out after the non-conforming cover layer has been removed. This avoids the formation of HSG structures on the non-conforming cover layer, as is increasingly observed when A1 2 0 3 is selected as the material of the cover layer 3.
  • FIG. 5 shows a capacitor structure arranged in a substrate 1.
  • the capacitor structure shown can be realized by repeatedly depositing non-conforming cover layers according to the invention.
  • a capacitor based on the capacitor structure has a high reliability, a low leakage current and a high specific capacity in terms of volume.
  • a capacitor having a high specific capacitance can be easily and inexpensively implemented with two or more electrodes designed in the form of a comb in a trench using the method according to the invention.
  • trenches 4 with a high aspect ratio are first introduced into a substrate 1 by dry etching or macropores.
  • the trenches 4 have a longitudinal extension perpendicular to the cross-sectional plane of the illustration.
  • a capacitor The structure then extends over one or more trenches 4 arranged parallel to one another.
  • Functional silicon structures provided in the substrate 1 are then doped, also for connecting electrodes of the capacitor structure, for example.
  • first non-conforming dielectric cover layer 32 and an non-conforming conductive cover layer 31 are provided in a shortened manner compared to the first non-conforming dielectric cover layer 32 arranged underneath.
  • a second non-conforming dielectric cover layer 32 ' is provided such that it completely covers the non-conforming conductive cover layer 31, which forms an outer electrode, and connects to the first non-conformally deposited dielectric cover layer 32.
  • a conformally deposited conductive cover layer 33 is provided as the inner electrode.
  • the contacting of the inner electrode takes place through a doped region of the substrate 1 or, for example, by structuring the deposited cover layers on the surface of the substrate 1.
  • the capacitor structure is prepared for a repetition of the above-mentioned deposition steps, so that with a sufficient trench width the The partial structure of the cover layers shown in FIG. 5 can be repeated within a trench 4. All the respective inner electrodes 33 on the trench bottom are advantageously conductively connected without further measures. With suitable etching back of the conformally deposited conductive cover layer 33 and the dielectric cover layers 32 ', a conductive connection between the respective outer electrodes 31 of the repeating partial structures likewise results without further measures.
  • Example 1 In the processing of vertical transistor structures, such as trench power transistors and IGBTs (isolated gate bipolar transistors), the doping of a drain zone is advantageously simplified with a cover layer which acts as a doping barrier and is in accordance with the invention in a non-conformal manner.
  • trenches are first made in a substrate, in each of which a gate electrode is provided in the later course of the process.
  • the trenches are lined in an upper region, which lies opposite the source and channel zones formed in the substrate in the finished structure, with a doping barrier which is deposited in a manner not conforming to the invention.
  • the drain zone of the substrate adjoining a lower region of the trenches is then doped and the doping barrier is subsequently removed.
  • An increasing integration density in integrated circuits leads to the need to provide through-contacts to structures in a deep layer arranged below the upper layer during their processing from a substrate surface through an upper layer with already formed conductive regions.
  • the conductive areas are doped semiconductor areas or metallizations.
  • an opening (channel) is etched down to the deeper layer in the substrate and then filled with a conductive material.
  • a non-conforming, dielectric cover layer is provided on a wall of the opening in an upper region of the channel, which covers any exposed sections of conductive regions of the upper layer. A bottom of the opening, in the area of which the conductive region of the deep layer is contacted, remains uncovered. An undesired electrical short circuit between the two conductive areas is avoided.
  • a typical example of such an application of the method according to the invention is for stacked capacitor structures.
  • a transistor structure is arranged along a deep layer between a semiconductor substrate and an overlying oxide layer, in which capacitor structures and signal lines (bit lines) are formed, and to be contacted through the oxide layer from a substrate surface.
  • bit lines signal lines
  • the signal lines can be exposed to an opening.

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Abstract

A la surface (101) d'un substrat (1), structurée en relief, notamment d'une plaquette de semiconducteurs, une couche de couverture (3) est créée au moyen d'un procédé de dépôt (ADL : dépôt de couche atomique) sur des surfaces de traitement (2) verticales ou inclinées par rapport à la surface (101) du substrat. Par limitation d'une quantité de traitement d'au moins un matériau précurseur et/ou limitation temporelle du procédé de dépôt, ladite couche de couverture (3) peut être structurée perpendiculairement par rapport à la surface (101) du substrat et conçue simplement en tant que couche fonctionnelle ou masque pour les étapes ultérieures du processus.
EP03787693A 2002-07-30 2003-07-21 Procede de structuration verticale de substrats en technique des semiconducteurs par depot non conforme Withdrawn EP1525610A1 (fr)

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DE10234735 2002-07-30
DE10234735A DE10234735A1 (de) 2002-07-30 2002-07-30 Verfahren zum vertikalen Strukturieren von Substraten in der Halbleiterprozesstechnik mittels inkonformer Abscheidung
PCT/DE2003/002438 WO2004017394A1 (fr) 2002-07-30 2003-07-21 Procede de structuration verticale de substrats en technique des semiconducteurs par depot non conforme

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US7344953B2 (en) 2008-03-18
WO2004017394A1 (fr) 2004-02-26
KR100615743B1 (ko) 2006-08-25
KR20050026050A (ko) 2005-03-14
DE10234735A1 (de) 2004-02-12
TW200403724A (en) 2004-03-01
JP2006500763A (ja) 2006-01-05
US20050164464A1 (en) 2005-07-28

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