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EP1340414A2 - Procede pour former dans un substrat une ouverture ou une cavite destinee a recevoir un composant electronique - Google Patents

Procede pour former dans un substrat une ouverture ou une cavite destinee a recevoir un composant electronique

Info

Publication number
EP1340414A2
EP1340414A2 EP01915623A EP01915623A EP1340414A2 EP 1340414 A2 EP1340414 A2 EP 1340414A2 EP 01915623 A EP01915623 A EP 01915623A EP 01915623 A EP01915623 A EP 01915623A EP 1340414 A2 EP1340414 A2 EP 1340414A2
Authority
EP
European Patent Office
Prior art keywords
substrate
opening
cavity
layer
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01915623A
Other languages
German (de)
English (en)
Inventor
John Gregory
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STS ATL Corp
Original Assignee
STS ATL Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0012754.8A external-priority patent/GB0012754D0/en
Application filed by STS ATL Corp filed Critical STS ATL Corp
Priority to EP04106328A priority Critical patent/EP1517599A1/fr
Publication of EP1340414A2 publication Critical patent/EP1340414A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0397—Tab
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0207—Partly drilling through substrate until a controlled depth, e.g. with end-point detection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting

Definitions

  • This invention relates to a method of forming an opening or cavity in a substrate.
  • the substrate is preferably of the type which can include an electronic component or integrated circuit.
  • An example of such a substrate is a printed circuit board (PCB).
  • PCB printed circuit boards
  • soldering and wire bonding techniques are expensive and require cumbersome equipment in order to achieve efficiency in the fabrication process. Additionally there may be a requirement to heat the solder twice; firstly on preparation of the PCB and again when mounting components on the PCB
  • JP 10098081 discloses using a carbon gas laser to cut a perimeter trench for an opening in a substrate having a copper foil laminated on both sides, the remaining substrate material being removed in a second step.
  • the copper foil is then patterned by lithography and etching to form leads to retain a component.
  • the present invention arose in order to provide smaller interconnect dimensions on a PCB, thereby rendering it capable of being produced thinner and eliminating the need for synthetic plastics leaded chip carriers (PLCCs).
  • the present invention can also be used to manufacture chip carriers with beneficial properties and lower cost.
  • Figure 1 shows a diagrammatic view of an embodiment of an apparatus for forming interconnects on a substrate
  • Figures 2a and 2b are diagrammatic sectional and plan views of a single component mounted on the substrate produced using the apparatus of Figure 1 ;
  • Figures 3a to 3c are plan views showing examples of interconnects; and Figure 4 shows a method of forming a contact through a via hole.
  • Figure 1 is an overall view of an apparatus 10 for forming interconnects on a substrate 12.
  • the apparatus 10 includes a laser 14, focussed through a suitable lens system 16, which in use, reflects off mirror 18.
  • a CO 2 laser having a power of 50 - 500 Watts and a beam diameter of 480 microns is used.
  • An Excimer laser or YAG laser can be used as an alternative.
  • Means for delivering the substrate such as a flat bed table 24.
  • Means for selectively removing regions from a first layer of material may include a photo imager (not shown) and an etch bath (not shown).
  • Means for removing volumes of the substrate may be a laser 14 or an ion beam etching device (not shown) or a plasma etcher (not shown).
  • Means for removing the material from the second surface may be a modified etch bath capable of etching an electrical conductor.
  • Power output of the laser 14 is controlled by micro-processor 20.
  • micro-processor 20 orientates mirror 18 and may also be used to focus the laser 14 via the lens system 16.
  • a different depth cavity can be formed either by pulsing a larger number of pulses from the energy source or increasing the duration of each pulse.
  • an array of cavities can be fabricated, the number and size of cavities in the array can be varied to produce different products or accommodate different devices.
  • Substrate 12 shown in greater detail in Figure 2, is in the form of a laminated sheet or tape.
  • Two layers 21 a and 21 b of metallic material, such as copper (or aluminium) sandwich a flexible substrate 12 comprises an etchable polymer such as polyethylene (tri-thalmate) (PET).
  • PET polyethylene
  • the thickness of the substrate is 190 microns, although thicknesses between 100 microns and 600 microns have been employed. Ideally if a silicon chip is to be inserted, it will be ground down from the back to give a similar thickness to that of the substrate. Alternatively, a substrate thickness is chosen according to the thickness of the semiconductor chip.
  • a non-metallic base material such as PET substrate 12 is clad with a metal material on at least one of its surfaces by laminating a sheet of the metal material, using an adhesive bonding agent or by catalysing the base material and plating a layer of metal which coats the base material in uniform thickness.
  • Substrate 12 may be introduced in a part finished or 'raw' form. If it is raw, the substrate needs to be treated. This is achieved by firstly coating the substrate with a photoresist. This may be applied as a curtain coat by thin uniform spraying, or using other known techniques. Conductor tracks, interconnects and die bonding sites are then photo- imaged on both surfaces. This is a routine step in printed wiring board processing.
  • a circuit pattern is formed on the metal clad surface of the substrate.
  • the circuit pattern has attachment locations 52 which correspond to bond pad dimensions and locations of a semiconductor component (not shown) to be inserted into the cavity defined on the substrate and connected to interconnects.
  • Laser ablation occurs at extremely high rates, typically between 300 to 800 pulses per second.
  • Micro-processor 20 varies the rate and duration of pulses from laser 14. This combination permits the vaporisation rate to be controlled and administered for the specific properties of the substrate material. The result is that ablation occurs at a precise X and Y location over a known area to a predetermined depth for a given array of M rows of cavities by N columns of cavities, defined over a specific area.
  • the substrate is firstly coated, then photo-imaged. Etching and stripping then occur. Laser ablation of the opening or cavity is then performed.
  • the next step is plasma and/or wet chemical cleaning using for example a potassium permanganate solution.
  • metal is deposited on the mechanical tab structures such (or contacts) just formed. This is achieved by immersion alloy deposition from solution. This is an electrodeless process, although electroplating could be used as an alternative.
  • the metal alloy chosen must be compatible with the application or bonding method chosen. Typical materials include tin, gold or silver based materials.
  • material ablated from the cavity can redeposit on other parts of the substrate. Such deposits are usually removed during the plasma and/or wet cleaning step. However, if the material being ablated is polyimide removal can be difficult.
  • an optional sacrificial layer can be deposited on the substrate surface or surfaces prior to the laser ablation step. The sacrificial layer can be photoresist for example. After ablation this layer can be easily removed by plasma and/or wet cleaning, and any redeposited material is removed at the same time.
  • This contouring step can be achieved by CNC routing, die punching, or YAG laser contouring
  • Electrodes are pre-defined by the etching process.
  • a series of digitated connectors, spaced one from another and arranged to be in register with contacts of the component or die to be inserted into the cavity or die are formed by a metal etch process before laser ablation of the dielectric.
  • the electrodes can be laser etched in the metal layer at the base of the cavity after the dielectric material has been ablated.
  • modifications to a pre-etched pattern in this layer can be made with the laser after the cavity has been formed (for example by removing tabs to free the end of an elongate structure).
  • the perforated substrate with contacts defined on one surface acts as a shelved recess for receiving electronic components (50).
  • the simplest embodiment is an embodiment with one or two contacts, suitable for receiving, for example, capacitors (Figure 3a).
  • Transistors require a third contact to be formed and a sketch of such is shown in Figure 3b.
  • More complex devices, such as integrated circuits (ICs), Read Only Memory (ROM), Random Access Memory (RAM) or micro-processors require many contacts (51 ).
  • An example is shown in Figure 3c.
  • the elongate metal bond leads or tabs which form the electrical contacts perform a dual function. Firstly, they act as electrical pathways to/from components. Secondly, they retain components at least during the fabrication process, due to their mechanical properties. For example, devices can be compression mounted, where insertion of the device causes the projecting tabs to fold, creating resilient clip structures which keep the device in place. It has been found that silver coated contact tabs are particularly advantageous in this application.
  • each etched region, on each surface is crucial. However, it will be appreciated that a certain degree of tolerance is permitted and die locations may be offset so as to provide for a suitable mechanical recess, capable of receiving and holding electrical components.
  • Components can be bonded to the electrodes projecting adjacent the cavity by for example ultrasonic bonding and/or pressure bonding. Alternatively shrink- wrap films can be adapted to urge a component against the electrodes, or an adhesive tape or tab may be used.
  • the invention may be used to create an array of cavities.
  • An advantage of this arrangement is that a plurality of devices may be produced on a single substrate.
  • the substrate may be flexible, and capable of being wound or folded so as to ease transportation by reducing its bulk.
  • the substrate may be stored on a spool.
  • Components may be introduced into previously formed cavities by any known technique, such as for example a pick-and-place machine, by air jet (vacuum) or by hand.
  • An arrangement whereby a reduced air pressure is created at one surface is particularly convenient. The pressure difference draws electronic components into each cavity, so that the component (such as a semiconductor chip or die) may be bonded to the substrate.
  • individual chip carriers may be die cut, routed, or sawn from a relatively large sheet or tape of the substrate.
  • a particularly advantageous feature of the invention is that it facilitates a flatter chip carrier profile than is normally achievable.
  • thickness of a chip carrier is fabricated in accordance with the invention is 17 micron greater than the die thickness.
  • the resultant carrier profile is thinner than has been previously achievable.
  • Many different types of electrical and electronic components can be placed into the substrate opening or cavity. These include resistors, capacitors, inductors, transistors, integrated circuits, tuners, wave-guides, piezoelectric devices, coils and/or heat-sinks.
  • each opening or cavity may be adapted to receive an electro-optical device, such as a liquid crystal device or a light emitting diode. In this latter case conductive tracks may be defined on a surface, using a transparent material such as Indium Tin Oxide (ITO).
  • ITO Indium Tin Oxide
  • the opening formed by laser ablation has extended all the way through the substrate.
  • a blank opening or cavity may be fabricated by stopping the ablation before all the substrate is removed. This technique is useful for making cavities in multilayer PCBs.
  • Multilayer PCBs have prepreg dielectric layers, typically 70 microns thick, interleaved with conductive metal layers.
  • the laser ablation process can be used to remove such material to expose bond pads in a subsurface metal layer.
  • a flip chip die with solder bumps can then be placed on top of the bond pads, so that when the assembly is heated the solder flows and bonds the chip in place.
  • An advantage of this technique is that the subsurface layers of the multilayer PCB can be used for signal input and output to the chip, which shortens the signal conductor length and reduces propagation delays.
  • an elongate flap or tab of metal (30) is left at the bottom of the via hole (31).
  • This flap or tab is longer than the depth of the via hole, and can optionally have an end shaped to form a serrated edge (32) or a barb or spike.
  • This flap or tab can be urged into the via by blowing a gas or liquid towards the via, or by pushing using a pin or similar solid tool.
  • the part of the flap or tab projecting though the other side of the via hole can then be crimped to a conductive track at the other side of the PCB, forming a through contact without the usual plating steps.
  • the serrated edges are shown engaging with a second opening or cavity (33) in the substrate, which can be formed by laser ablation or otherwise. This technique may also be advantageous in conventional PCB manufacture, when openings or cavities for receiving electronic devices are not cut in the substrate.
  • the laser ablation occurs through a patterned metal layer carried by the substrate, it is possible to use a separate metal sheet with corresponding holes cut therein as a mask positioned adjacent the substrate as an alternative.
  • the laser ablation step exposed elongate contacts which projected into the resulting cavity.
  • Such elongate metal members need not be electrical contacts, however - they can form mechanical structures such as for example for pressure switches.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Laser Beam Processing (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé qui permet de former dans un substrat une ouverture ou une cavité destinée à recevoir un composant électronique. Le procédé consiste à disposer une couche de masquage façonnée opaque sur ou adjacente à une première surface principale du substrat, ladite couche de masquage présentant une ouverture sus-jacente à l'emplacement auquel la cavité doit être ménagée. Le procédé consiste ensuite à retirer le matériau du substrat par ablation au laser, à travers l'ouverture, afin de former une ouverture ou une cavité de taille appropriée pouvant recevoir ledit composant électronique.
EP01915623A 2000-02-28 2001-02-26 Procede pour former dans un substrat une ouverture ou une cavite destinee a recevoir un composant electronique Withdrawn EP1340414A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04106328A EP1517599A1 (fr) 2000-02-28 2001-02-26 Procédé d'interconnexion des faces opposées d'un dispositif d'interconnexion pour composants électroniques

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US514257 1983-07-15
US51425700A 2000-02-28 2000-02-28
GB0012754 2000-05-26
GBGB0012754.8A GB0012754D0 (en) 2000-02-28 2000-05-26 Apparatus for forming interconnects on a substrate and related method
PCT/IB2001/000555 WO2001065595A2 (fr) 2000-02-28 2001-02-26 Procede pour former dans un substrat une ouverture ou une cavite destinee a recevoir un composant electronique

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP04106328A Division EP1517599A1 (fr) 2000-02-28 2001-02-26 Procédé d'interconnexion des faces opposées d'un dispositif d'interconnexion pour composants électroniques

Publications (1)

Publication Number Publication Date
EP1340414A2 true EP1340414A2 (fr) 2003-09-03

Family

ID=26244351

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01915623A Withdrawn EP1340414A2 (fr) 2000-02-28 2001-02-26 Procede pour former dans un substrat une ouverture ou une cavite destinee a recevoir un composant electronique

Country Status (5)

Country Link
EP (1) EP1340414A2 (fr)
JP (1) JP2003526205A (fr)
CN (2) CN100366132C (fr)
AU (1) AU2001242703A1 (fr)
WO (1) WO2001065595A2 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10213879C1 (de) * 2002-03-27 2003-07-10 Infineon Technologies Ag Elektronisches Bauteil
DE10213881C1 (de) * 2002-03-27 2003-10-02 Infineon Technologies Ag Speichermodul mit aneinander haftenden Halbleiterchips und Herstellung sverfahren
EP2313230A4 (fr) 2008-07-09 2017-03-08 FEI Company Procédé et appareil d'usinage laser
CN102110866B (zh) * 2009-12-24 2013-08-28 深南电路有限公司 波导槽制作工艺

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3608410A1 (de) * 1986-03-13 1987-09-17 Siemens Ag Herstellung von feinstrukturen fuer die halbleiterkontaktierung
JPH0793485B2 (ja) * 1988-05-16 1995-10-09 カシオ計算機株式会社 Ｉｃユニットの接続方法
DE4326424A1 (de) * 1993-08-06 1995-02-09 Ant Nachrichtentech Verfahren zum Herstellen von TAB-Filmträgern
GB2286787A (en) * 1994-02-26 1995-08-30 Oxford Lasers Ltd Selective machining by dual wavelength laser
GB9420182D0 (en) * 1994-10-06 1994-11-23 Int Computers Ltd Printed circuit manufacture
JP3593234B2 (ja) * 1996-04-23 2004-11-24 日立電線株式会社 半導体装置用両面配線テープキャリアの製造方法
JPH1098081A (ja) * 1996-09-24 1998-04-14 Hitachi Cable Ltd 半導体チップ実装用のテープキャリア及びその製造方法
FR2766654B1 (fr) * 1997-07-28 2005-05-20 Matsushita Electric Works Ltd Procede de fabrication d'une carte de circuit imprime
JP3506002B2 (ja) * 1997-07-28 2004-03-15 松下電工株式会社 プリント配線板の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0165595A3 *

Also Published As

Publication number Publication date
WO2001065595A3 (fr) 2002-01-03
CN100366132C (zh) 2008-01-30
WO2001065595A2 (fr) 2001-09-07
CN1668167A (zh) 2005-09-14
JP2003526205A (ja) 2003-09-02
AU2001242703A1 (en) 2001-09-12
CN1406452A (zh) 2003-03-26

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