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EP1236280A1 - Detecteur de cretes numerique a seuil de bruit et procede associe - Google Patents

Detecteur de cretes numerique a seuil de bruit et procede associe

Info

Publication number
EP1236280A1
EP1236280A1 EP00973413A EP00973413A EP1236280A1 EP 1236280 A1 EP1236280 A1 EP 1236280A1 EP 00973413 A EP00973413 A EP 00973413A EP 00973413 A EP00973413 A EP 00973413A EP 1236280 A1 EP1236280 A1 EP 1236280A1
Authority
EP
European Patent Office
Prior art keywords
peak
input
maximum
output
minimum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP00973413A
Other languages
German (de)
English (en)
Inventor
Valentin T. Jordanov
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mirion Technologies Canberra Inc
Original Assignee
Canberra Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canberra Industries Inc filed Critical Canberra Industries Inc
Publication of EP1236280A1 publication Critical patent/EP1236280A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1532—Peak detectors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of AC or of pulses

Definitions

  • the present invention relates to digital peak detectors generally and, more particularly to a novel digital peak detector with noise threshold and method of use
  • Radiation spectrometers perform pulse height analysis of pulse signals from a radiation detector The pulse height is measured by detecting the peak values of the pulses The peak detection involves two signals - peak detect and peak value. In general, the peak value is referred to the maximum of the pulse waveform It is, however, beneficial to know both the minimal (MIN) and maximal (MAX) peak values of the signal, as is described in V Joranov and G F. Knoll, "Digital Pulse Processor Using A Moving Average Technique", IEEE Trans. Nucl. Sci., Vol. 40, No 4, pp 764-769, August 1 93, and H Sawata and Y Tomimitsu, "Digitalized Amplitude Detection Circuit For Analog Input Signal", U S Patent No 4,769,613
  • the MAX peak value is used to address a channel in the spectral memory that is incremented
  • the increment process is initiated by the peak detect signal.
  • the peak value is the signal value when the peak detect signal becomes active That is, the pulse waveform is sampled at the activation of the peak detect signal
  • a similar approach can be used with time invariant systems, but the peak value capture becomes sensitive to the time jitter of the peak detect signal
  • the MIN peak value can be used to estimate the noise of the pulse waveform. This is done, for example, by averaging MIN peak values The average is used to set the noise threshold of the spectrometer
  • Both analog and digital pulse processors use peak detectors.
  • the analog peak detectors typically use a complex scheme of external digital signals to activate and reset the peak detector
  • Digital peak detectors can be built in a similar fashion but it is advantageous to implement a self-triggered peak detection scheme, as is described in Jordanov, supra, and V T Jordanov, "Som Digital lechmcpies for Real Time Processing of Pulses from Radiation Detectors", Ph D thesis, The University of Michigan, Ann Arbor, Michigan, March 1 94
  • the pulse signal is assumed to be discrete
  • the pulse signal samples change at the active edge (e g LOW-to-HIGH transition) of the system clock (CLK)
  • the active state of the level signals is HIGH and the inactive state is LOW Note that these assumptions are only for clarity and simplicity of the description
  • FIG. 1 depicts a block diagram of a low-level discriminator based peak dctecloi ⁇ first digital compaialoi CM l 30 conli ⁇ ls the peak detection process
  • the discrete pulse signal is connected to one of the inputs (A) of comparator 20, while a threshold value is applied to the other input (B)
  • the output of comparator 30 is in inactive state (LOW)
  • peak register PREG 40 is held in reset state - the output thereof is forced to zero
  • a second digital compai at ⁇ i CMP2 50 is used to c ⁇ mpai e the output of peak register 40 with the discrete pulse signal
  • the output of second comparator 50 is HIGH when the pulse signal sample is greater than the PREG value
  • the output of second comparator CMP2 50 output controls the enable input of peak register 40 When the enable signal is HIGH, the current pulse signal value at the input of peak register
  • first comparator CMPl 30 When the discrete pulse signal exceeds the threshold, the output of first comparator CMPl 30 becomes active PREG 40 starts tracking the maximum of the discrete pulse signal The output of PREG 40 is updated only if the current sample of the discrete pulse signal is greater than the PREG output value When the pulse signal becomes smaller than the threshold, the first comparator CMP l 30 latches the output of PREG 40 into a latch MAXL 60 and puts peak detector 40 in a reset state The Peak Detect signal output of first comparator CMPl 30 is the transition of the CMPl from active to inactive state - HIGH to LOW transition
  • Figures 2a and 2b illustrate the operation of the low-level discriminator based peak detector of Figure 1
  • Fig 2a illustrates the component of the discrete pulse signal- system noise and two pulses corresponding to two interactions in the radiation detector are shown
  • Two pulses that partially overlap are shown in Figure 2b together with the threshold
  • the output of PREG 40 (Figure 1) is shown in the second wavefoim in Figuie 2b
  • the MAX peak value that will be captured is indicated
  • the last waveform in Figure 2b is the peak detect signal It is clear that this type of peak detectoi detects the absolute maximum while the signal is above the threshold and Figures 2a and 2b illustrate a limitation of the low-level discriminator approach, namely, that only one peak over the threshold is detected, even though the resulting pulse signal comp ⁇ ses two pulses each having its own MAX pulse peak
  • Figure 3 shows a modified configuration of the low-level discriminator based peak detector, generally indicated by the reference numeral 70, with MAX and MLN peak values detection
  • PREG 40 tracks the maximum values when the output of first comparator CMPl 30 is HIGH, while the minimum values are obtained when the CMPl is inactive
  • the HIGH to LOW transition of the peak detect signal indicates the capture of the MAX values
  • the LOW to HIGH transition of the peak detect indicates capture of the MIN detector
  • An exclusive OR gate leceives as inputs the output signals A>B of first and second comparators 30 and 50 and provides and enables the output of PREG 40 to latch into either latch MAXL 60 oi M1NL 90, depending on whether MAX or MIN peak values have been detected
  • peak detector 70 has good noise immunity, the throughput rate is reduced due to the fact that partially overlapping pulses cannot be distinguished, as was the case with low-level discriminator 20 ( Figure 1 ) Note that even partially ovei lapping the pulse amplitudes can be free of pile-up In order to peak detect and acqune partially overlapped pulses a peak detector capable of detecting local peaks is needed
  • comparator CMP 30 As soon as the disci ete pulse signal becomes zeio or starts decreasing, comparator CMP 30 changes its state The HIGH to LOW transition captures the MAX peak value while the LOW to HIGH transition captures the MIN peak value
  • FIG. 6 A modification of peak detector 100 ( Figure 4) is shown in Figure 6, where it is generally indicated by the reference numeral 1 10
  • the sign bit of a subtractor 120 connected to leceive as inputs the output of PREG 40 and the discrete pulse signal, that actually performs the differentiation of the discrete pulse signal indicates the zero crossing
  • the sign output of subtractor 120 passes through an inverter 130 before serving as latching inputs to latches MAXL 60 and MINL 90
  • the subtractor sign bit equivalent to a comparator gieatei (or less) output signal with one input of the comparator connected to zero
  • the present invention achieves the above objects, among others, by providing, in a preferred embodiment, a method of operating a peak detector, comprising providing said peak detector, applying a discrete pulse input signal to said peak detector, and using said peak detector to detect local maximum or local minimum of said input signal
  • Figure 1 is a block diagram of a conventional low-level discriminator based peak detector.
  • Figure 2a comprises waveforms showing the resulting signal of noise plus two, partially overlapping pulses.
  • Figure 2b comprises waveforms showing the operation of the peak detector of Figure 1.
  • Figure 3 is a block diagram showing a conventional modification of the peak detector of Figure 1.
  • Figure 4 is block diagram of a peak detector using a differentiated pulse signal and detecting zero crossings.
  • Figure 5 comprises waveforms showing the operation of the peak detector of Figure 4.
  • Figure 6 is block diagram showing a conventional modification of the peak detector of Figure 4.
  • Figure 7 is a block diagram showing a peak detector according to the present invention.
  • Figure 8 comprises waveforms showing the operation of the peak detector of Figure 7.
  • Figure 9 is a block diagram showing a modification of the peak detector of Figure 7.
  • Figure 10 comprises waveforms showing the operation of the peak detector of Figure 9.
  • FIG. 7 A digital peak detector configuration according to the present invention is shown in Figure 7 where it is indicated generally by the reference numeral 200. All registers and flip-flops have their clock inputs tied to the system clock elk
  • the Discrete Pulse Signal is applied to a subtractor SUB 210 and to a peak register PREG 220
  • PREG 220 is an enable type edge triggered register
  • the output of PREG 220 is connected to the subtracting input of SUB 210 and the MAX and MIN peak value latches MAXL 230 and M1NL 240, respectively
  • the output of SUB 210 is applied to one of the inputs of a comparator CMP 250 (trace A)
  • the sign bit of the subtractor is applied to one of the inputs of an XOR gate 260 that acts as a programmable inverter
  • the output of XOR gate 260 is applied to the enable input of the PREG 220
  • a Noise Threshold digital value is applied to one of the inputs of a data multiplexer MUX 270 and to the input of a negating and scaling unit NEG 280
  • the output of NEG 280 is applied to the other input of MUX 270
  • the output of CMP 250 is applied to the D input of a d-type flip-flop DFF 290.
  • the output of the DFF is connected to the selecting input of MUX 270, the other input of the XOR gate, and the latching inputs of MAXL 230 and M1NL 240.
  • peak detector 200 ( Figure 7) is illustrated in Figure 8. Referring to both Figures 7 and 8, peak detector 200 at any moment can be in one of two operating modes - tracking maximum and tracking minimum The MIN and MAX values are detected when the peak detector changes its state The operating mode is determined by the output of DFF 290 (Peak Detect Signal) - when it is HIGH, the peak detector tracks maximum and, when LOW, the peak detector tracks minimum
  • DFF 290 Peak Detect Signal
  • the output of DFF 290 When the output of DFF 290 is HIGH, the output of MUX 270 is connected to the output of NEG 280 The value of the output of NEG 280 is the positive Noise Ilshold value multiplied by k Normally, the positive constant k is equal to one.
  • the sign bit of SUB 210 is inverted by XOR 260 If the output of DFF 290 is HIGH and sign is LOW, then PREG 220 is enabled to capture the current Discrete Pulse Signal sample. The sign is LOW if the Discrete Pulse Signal is greater or equal to current output value of PREG 220, thus a maximum peak value tracking is achieved.
  • the sign of SUB 210 is HIGH, disabling the update of PREG 220 - the PREG is holding the captured maximum value. If the output of SUB 210 (CMP 250 input A) becomes smaller than the output of MUX 270 (negative threshold at the B input of the CMP), then the output of the CMP becomes zero and DFF 290 switches its state to LOW.
  • Peak detector 200 has a controllable noise sensitivity that is determined by the value of the Noise Threshold.
  • the Noise Threshold should be set slightly above the noise level of the discrete pulse signal.
  • the circuit exhibits a hysteresis that is equal to (k + ] )* (Noise Threshold). Peak detector 200 allows peak detection of local minimum and maximum values providing high throughput capability.
  • the configuration of Figure 7 can be realized in different functionally equivalent arrangements.
  • Figure 9 depicts a modified circuit arrangement of peak detector 200 (Figure 7), the modified peak detector being indicated generally by the reference numeral 400.
  • a discrete pulse signal is applied as an input to first comparator CM l 410 and as an input to a second comparator CMP2 420
  • the discrete pulse signal is also an input to the D input of peak register PREG 430.
  • the output of PREG 430 is connected to one of the inputs of an adder ADD 440 and to the D inputs of registers MAXL 450 and MINL 460.
  • the outputs of MAXL 450 and MINL 460 represent the maximum MAX and minimum MIN values of the signal detected between the transitions of the peak detect signal. All registers and flip-flops have their clock inputs tied to the system clock elk.
  • a noise threshold signal is applied to one of the inputs of a data multiplexer MUX 500 and to the input of a negating and scaling unit NEG 510.
  • the output of MUX 500 is connected to one of the inputs of ADD 440.
  • the output of ADD 440 is applied to the B input of CMP2 420
  • the output of CMP2 feeds the D input of flip- flop DFF 520.
  • the output of DFF 520 is the peak detect signal and is applied to the latch inputs of registers MAXL 450 and MINL 460 and one of the inputs of an exclusive OR gate 530, the other input of which OR gate is the output of CMPl 410.
  • the output of exclusive OR gate 530 is applied to the enable input of PREG 430.
  • Figure 10 illustrates the operation of discriminator 400 (Figure 9).
  • the circuit tracks maximum (Peak Detect HIGH). If Peak Deled is HIGH, exclusive OR gate 530 inverts the output of CMP l 410.
  • PREG 430 storage in PREG 430 is enabled only when the Discrete Pulse Signal is larger or equal to the current value stored in PREG 430 - a condition of tracking maximum. The maximum will be tracked until the Peak Detect signal transitions to LOW.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne un procédé permettant d'activer un détecteur (200) de crêtes. Ce procédé consiste à fournir un détecteur de crêtes; à appliquer un signal d'entrée d'impulsion discret au détecteur de crêtes; puis à utiliser ce détecteur pour détecter le maximum local ou le minimum local d'un signal d'entrée.
EP00973413A 1999-10-08 2000-10-05 Detecteur de cretes numerique a seuil de bruit et procede associe Withdrawn EP1236280A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15855999P 1999-10-08 1999-10-08
US158559P 1999-10-08
PCT/US2000/027501 WO2001028101A1 (fr) 1999-10-08 2000-10-05 Detecteur de cretes numerique a seuil de bruit et procede associe

Publications (1)

Publication Number Publication Date
EP1236280A1 true EP1236280A1 (fr) 2002-09-04

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Application Number Title Priority Date Filing Date
EP00973413A Withdrawn EP1236280A1 (fr) 1999-10-08 2000-10-05 Detecteur de cretes numerique a seuil de bruit et procede associe

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EP (1) EP1236280A1 (fr)
JP (1) JP2003511949A (fr)
WO (1) WO2001028101A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4524622B2 (ja) * 2005-01-07 2010-08-18 株式会社島津製作所 Ｘ線分析用信号処理装置
JP4895161B2 (ja) * 2005-10-31 2012-03-14 横河電機株式会社 ピーク検出回路および放射線測定装置
JP4706566B2 (ja) * 2006-06-09 2011-06-22 株式会社島津製作所 Ｘ線分析用信号処理装置
US8828329B2 (en) 2010-10-01 2014-09-09 Church & Dwight, Co., Inc. Electronic analyte assaying device
US9588113B2 (en) 2012-02-22 2017-03-07 Church & Dwight Co., Inc. Methods for electronic analyte assaying

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769613A (en) * 1985-12-05 1988-09-06 Nec Corporation Digitalized amplitude detection circuit for analog input signal
US4827191A (en) * 1987-09-08 1989-05-02 Motorola, Inc. Adaptive range/DC restoration circuit or use with analog to digital convertors
DE4005037A1 (de) * 1990-02-16 1991-08-22 Siemens Nixdorf Inf Syst Verfahren zum umsetzen einer analogen spannung in einen digitalwert
JPH04134269A (ja) * 1990-09-26 1992-05-08 Kikusui Electron Corp グリッチ検出装置
US5194865A (en) * 1991-12-06 1993-03-16 Interbold Analog-to-digital converter circuit having automatic range control
US6100829A (en) * 1997-10-20 2000-08-08 Seagate Technology, Inc. Method and apparatus for a digital peak detection system including a countdown timer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0128101A1 *

Also Published As

Publication number Publication date
WO2001028101A1 (fr) 2001-04-19
JP2003511949A (ja) 2003-03-25

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