EP1160851A3 - Méthode de fabrication d'un dispositif semiconducteur multicouche - Google Patents
Méthode de fabrication d'un dispositif semiconducteur multicouche Download PDFInfo
- Publication number
- EP1160851A3 EP1160851A3 EP01112083A EP01112083A EP1160851A3 EP 1160851 A3 EP1160851 A3 EP 1160851A3 EP 01112083 A EP01112083 A EP 01112083A EP 01112083 A EP01112083 A EP 01112083A EP 1160851 A3 EP1160851 A3 EP 1160851A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- epitaxial
- epitaxial layer
- substrate
- fabricating
- theoretical calculation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Materials Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Junction Field-Effect Transistors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000159707 | 2000-05-30 | ||
| JP2000159707A JP4757370B2 (ja) | 2000-05-30 | 2000-05-30 | エピタキシャル基板の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP1160851A2 EP1160851A2 (fr) | 2001-12-05 |
| EP1160851A3 true EP1160851A3 (fr) | 2006-06-14 |
Family
ID=18664000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP01112083A Withdrawn EP1160851A3 (fr) | 2000-05-30 | 2001-05-28 | Méthode de fabrication d'un dispositif semiconducteur multicouche |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6569693B2 (fr) |
| EP (1) | EP1160851A3 (fr) |
| JP (1) | JP4757370B2 (fr) |
| KR (1) | KR20010110115A (fr) |
| TW (1) | TWI228759B (fr) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2001247984A1 (en) * | 2000-02-16 | 2001-08-27 | Bea Systems Inc. | Workflow integration system for enterprise wide electronic collaboration |
| US7552443B2 (en) * | 2001-10-18 | 2009-06-23 | Bea Systems, Inc. | System and method for implementing an event adapter |
| US8135772B2 (en) * | 2002-05-01 | 2012-03-13 | Oracle International Corporation | Single servlets for B2B message routing |
| US7257645B2 (en) * | 2002-05-01 | 2007-08-14 | Bea Systems, Inc. | System and method for storing large messages |
| US7519976B2 (en) | 2002-05-01 | 2009-04-14 | Bea Systems, Inc. | Collaborative business plug-in framework |
| US7165249B2 (en) * | 2002-05-02 | 2007-01-16 | Bea Systems, Inc. | Systems and methods for modular component deployment |
| US7627631B2 (en) * | 2002-05-02 | 2009-12-01 | Bea Systems, Inc. | Systems and methods for collaborative business plug-ins |
| US7484224B2 (en) * | 2002-05-02 | 2009-01-27 | Bae Systems, Inc. | Adapter deployment without recycle |
| JP3601527B2 (ja) * | 2002-06-27 | 2004-12-15 | 住友電気工業株式会社 | バックゲート特性判定方法及びバックゲート特性判定装置 |
| US7752599B2 (en) * | 2003-02-25 | 2010-07-06 | Bea Systems Inc. | Systems and methods extending an existing programming language with constructs |
| US7293038B2 (en) * | 2003-02-25 | 2007-11-06 | Bea Systems, Inc. | Systems and methods for client-side filtering of subscribed messages |
| US20050022164A1 (en) * | 2003-02-25 | 2005-01-27 | Bea Systems, Inc. | Systems and methods utilizing a workflow definition language |
| US20040167915A1 (en) * | 2003-02-25 | 2004-08-26 | Bea Systems, Inc. | Systems and methods for declaratively transforming data objects between disparate representations |
| JP4518886B2 (ja) * | 2004-09-09 | 2010-08-04 | シャープ株式会社 | 半導体素子の製造方法 |
| KR100681673B1 (ko) * | 2005-12-29 | 2007-02-09 | 동부일렉트로닉스 주식회사 | 불순물층에 의해 이동된 에피택시층 측정 방법 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4284467A (en) * | 1972-02-14 | 1981-08-18 | Hewlett-Packard Company | Method for making semiconductor material |
| US5198879A (en) * | 1990-03-19 | 1993-03-30 | Fujitsu Limited | Heterojunction semiconductor device |
| US5863811A (en) * | 1995-06-28 | 1999-01-26 | Sony Corporation | Method for growing single crystal III-V compound semiconductor layers on non single crystal III-V Compound semiconductor buffer layers |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1528192A (en) * | 1975-03-10 | 1978-10-11 | Secr Defence | Surface treatment of iii-v compound crystals |
| DE3567871D1 (en) * | 1984-03-26 | 1989-03-02 | Secr Defence Brit | The preparation of metal alkyls |
| GB8428032D0 (en) * | 1984-11-06 | 1984-12-12 | Secr Defence | Growth of crystalline layers |
| GB8606748D0 (en) * | 1986-03-19 | 1986-04-23 | Secr Defence | Monitoring surface layer growth |
| US5371399A (en) * | 1991-06-14 | 1994-12-06 | International Business Machines Corporation | Compound semiconductor having metallic inclusions and devices fabricated therefrom |
| US5277769A (en) * | 1991-11-27 | 1994-01-11 | The United States Of America As Represented By The Department Of Energy | Electrochemical thinning of silicon |
| US5508829A (en) * | 1992-12-18 | 1996-04-16 | International Business Machines Corporation | LTG AlGaAs non-linear optical material and devices fabricated therefrom |
| MY112590A (en) * | 1994-09-02 | 2001-07-31 | Sec Dep For Defence Acting Through His Defence Evaluation And Research Agency United Kingdom | Semi-conductor devices and their production |
| JP3329685B2 (ja) * | 1996-05-16 | 2002-09-30 | 株式会社東芝 | 計測装置および計測方法 |
| JPH11148812A (ja) * | 1997-11-14 | 1999-06-02 | Sony Corp | エピタキシャル成長層の表面粗さの評価方法及びその装置、エピタキシャル成長層の反射率測定方法及びその装置、並びに半導体装置の製造方法 |
| KR100292030B1 (ko) * | 1998-09-15 | 2001-08-07 | 윤종용 | 반도체 박막 공정에서의 박막 두께 제어 방법 |
-
2000
- 2000-05-30 JP JP2000159707A patent/JP4757370B2/ja not_active Expired - Lifetime
-
2001
- 2001-05-24 TW TW090112503A patent/TWI228759B/zh not_active IP Right Cessation
- 2001-05-28 EP EP01112083A patent/EP1160851A3/fr not_active Withdrawn
- 2001-05-29 US US09/865,482 patent/US6569693B2/en not_active Expired - Lifetime
- 2001-05-29 KR KR1020010029610A patent/KR20010110115A/ko not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4284467A (en) * | 1972-02-14 | 1981-08-18 | Hewlett-Packard Company | Method for making semiconductor material |
| US5198879A (en) * | 1990-03-19 | 1993-03-30 | Fujitsu Limited | Heterojunction semiconductor device |
| US5863811A (en) * | 1995-06-28 | 1999-01-26 | Sony Corporation | Method for growing single crystal III-V compound semiconductor layers on non single crystal III-V Compound semiconductor buffer layers |
Non-Patent Citations (1)
| Title |
|---|
| SASAJIMA YUICHI ET AL: "Heavy Si doping in AlGaAs near modulation-doped heterointerfaces", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 75, no. 17, 25 October 1999 (1999-10-25), pages 2596 - 2598, XP012023827, ISSN: 0003-6951 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001338884A (ja) | 2001-12-07 |
| US6569693B2 (en) | 2003-05-27 |
| EP1160851A2 (fr) | 2001-12-05 |
| JP4757370B2 (ja) | 2011-08-24 |
| TWI228759B (en) | 2005-03-01 |
| US20010051382A1 (en) | 2001-12-13 |
| KR20010110115A (ko) | 2001-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1160851A3 (fr) | Méthode de fabrication d'un dispositif semiconducteur multicouche | |
| WO2005050711A3 (fr) | Procede de fabrication de dispositifs semi-conducteurs a l'aide d'une matiere contenant du silicium contraint | |
| HK177896A (en) | Semiconductor device with dummy features in active layers | |
| IE822220L (en) | Semi-conductor integrated circuit with interconnecting¹layers | |
| TW200515474A (en) | Semiconductor device and fabrication method thereof | |
| WO2002071458A3 (fr) | Croissance de structures de semi-conducteurs composes sur des films d'oxyde a motifs | |
| WO2004102635A3 (fr) | Procedes de conservation de couches de substrats semi-conducteurs sous contrainte au cours d'un traitement cmos | |
| WO2006007394A3 (fr) | Couche tricanal contrainte pour dispositifs electroniques a base de semi-conducteur | |
| WO2002101818A3 (fr) | Procede d'isolation de dispositifs semi-conducteurs | |
| WO2006037933A3 (fr) | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees | |
| CA2475966A1 (fr) | Procede de fabrication de cristal | |
| WO2006017640B1 (fr) | Procédé de formation de matériaux de silicium en souche de conductivité thermique améliorée | |
| WO2010015301A8 (fr) | Passivation de structures semi-conductrices gravées | |
| WO2005065089A3 (fr) | Procede pour fabriquer un composant a semi-conducteurs, composant a semi-conducteurs forme selon le procede | |
| TWI257122B (en) | Semiconductor device and method for forming conductive path | |
| WO2011116762A3 (fr) | Procédé de fabrication d'une cellule solaire semi-conductrice | |
| TWI264766B (en) | Method for fabricating recessed gate structure | |
| TW200503271A (en) | Semiconductor device, manufacturing method thereof, and manufacturing method of metallic compound thin film | |
| TW200608459A (en) | Method for fabricating semiconductor device and semiconductor device | |
| WO2005122254A3 (fr) | Empilement de grilles et sequence d'attaque d'empilements de grille pour une integration de grilles metalliques | |
| WO2012046306A9 (fr) | Dispositif photovoltaïque et son procédé de fabrication | |
| WO2003061025A1 (fr) | Structure multicouches a compose semi-conducteur, dispositif a effet hall, et procede de fabrication de ce dispositif | |
| WO2003063227A3 (fr) | Procede de passivation de la surface d'un semi-conducteur iii-v | |
| TW200505003A (en) | Semiconductor structure having a strained region and method of fabricating the same | |
| TW357456B (en) | Method of manufacturing a trench storage capacitor embedded in a semiconductor substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
| AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
| RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: SUMITOMO CHEMICAL COMPANY, LIMITED |
|
| PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
| AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
| AX | Request for extension of the european patent |
Extension state: AL LT LV MK RO SI |
|
| RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 29/778 20060101ALN20060509BHEP Ipc: H01L 21/335 20060101ALI20060509BHEP Ipc: H01L 21/20 20060101AFI20060509BHEP |
|
| 17P | Request for examination filed |
Effective date: 20060724 |
|
| 17Q | First examination report despatched |
Effective date: 20061024 |
|
| AKX | Designation fees paid |
Designated state(s): DE FR GB |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20110210 |