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EP1018163A1 - Composant semi-conducteur comportant une zone de derive - Google Patents

Composant semi-conducteur comportant une zone de derive

Info

Publication number
EP1018163A1
EP1018163A1 EP98954124A EP98954124A EP1018163A1 EP 1018163 A1 EP1018163 A1 EP 1018163A1 EP 98954124 A EP98954124 A EP 98954124A EP 98954124 A EP98954124 A EP 98954124A EP 1018163 A1 EP1018163 A1 EP 1018163A1
Authority
EP
European Patent Office
Prior art keywords
region
semiconductor component
layer
conductivity type
sic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98954124A
Other languages
German (de)
English (en)
Inventor
Heinz Mitlehner
Michael Stoisiek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19741928A external-priority patent/DE19741928C1/de
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1018163A1 publication Critical patent/EP1018163A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/251—Lateral thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • the invention relates to a semiconductor component that conducts electricity in the lateral direction. Regardless of its configuration as a MOS transistor, IGBT, thyristor or diode, its drift zone should occupy a substantially smaller area at a predetermined blocking voltage than the drift zone of the corresponding component known from the prior art.
  • a semiconductor device with the specified in claim 1 given characteristics has this property. Refinements and advantageous developments of the semiconductor component according to the invention are the subject of the dependent claims.
  • Smart Power ICs can be, for example, due to the much smaller area of the Lei ⁇ produce stungChleiter devices considerably cheaper or inte- integrate a larger number of components with the same blocking ability on a smaller chip area.
  • FIG. 1 shows a first exemplary embodiment of a SiC-MOS transistor in plan view and in cross section
  • FIG. 2 shows a second exemplary embodiment of a SiC-MOS transistor in plan view and in cross section
  • FIG. 3 shows an embodiment of an IGBT
  • Figure 4 shows an embodiment of a thyristor
  • Figure 5 shows an embodiment of a diode
  • FIG. 6 shows the respective semiconductor structure after execution of individual steps of a method for producing the SiC-MOS transistor shown in FIG. 1.
  • the SiC-MOS transistor which is not shown to scale in FIG. 1, is mirror-symmetrical with respect to the axis 3 which is perpendicular to a main surface 1 of the substrate 2, a thermally grown, typically 1-3 ⁇ m thick Si0 2 layer 4 doped to s rom considerden in the lateral direction MOS transistor of the p + Si substrate 2 (dopant concentration> 10 18 - 10 19 cm "3)
  • the thickness d SlC dielectrically isolated which the Si0. 2 - Layer 4 partially covering SiC layer 6 and bordered by an SiO 2 zone 5 is, for example, d SlC ⁇ 1-2 ⁇ m.
  • SiC layer 6 has two n + -doped regions 7/8 (dopant concentration> 10 18 cm “3 ), a source electrode 9 contacting the outer region 7 and a drain electrode 10 contacting the inner region 8.
  • a source-side region 7 and the only weakly electron-conducting drift zone 12 covered by an SiO 2 insulator layer 11 (“intermediate oxide”) there is a p + -doped region 13 (dopant concentration “10 17 cm ” 3 ) Insulator layer 11 embedded and connected via contact holes with conductor connections 14.
  • the gate electrode If the gate electrode is acted upon 14 with a positive potential, the p-type region 13 becomes impoverished. At the same time, an n-type channel is formed on its gate-side surface, via which the electrons flow from the source electrode 9 into the drift zone 12 and further to the drain electrode 10. as soon as the potential difference built up between the source and drain electrodes 9/10 exceeds the component-specific threshold voltage In the area of the drift zone 12, the current thus flows through the SiC-MOS transistor in the lateral direction indicated by the arrows.
  • d SlC «3 x 10 corresponds to 13 cm 2 . This ensures that the drift zone 12 very quickly becomes depleted of charge carriers and that the electric field strength in the blocked state of the SiC-MOS transistor is approximately constant over the entire width l d of the drift zone 12.
  • the further components present in a high-voltage smart power IC can be integrated into the region of the Si substrate 2 not covered by the SiC layer 6 and can be interconnected via interconnect metallizations and with the connections of the SiC MOS Transistor are connected.
  • the component shown in the left part is a conventional Si-MOS transistor with a gate electrode 16 embedded in the Si0 2 layer 4 and two n + -doped regions 17/18, which are spaced apart from one another in the substrate 2 .
  • Electrons have a significantly smaller mobility in SiC than in silicon, which is disadvantageous due to the switch-on resistance of the corresponding SiC component. Since, in particular, high-blocking MOS transistors should have a turn-on resistance that is as small as possible, it is proposed to implement only the voltage-absorbing part of the transistor in SiC, and the gate-controlled channel region in Si.
  • FIG. 2 shows the corresponding component consisting of an Si-MOSFET and an SiC drift path in a top view and in cross section.
  • the finger-shaped component in the zx plane is again mirror-symmetrical with respect to the axis labeled 3.
  • the electron-conducting channel is formed on the surface of the p-conducting Si substrate 2 between the two n + -doped regions 19/20.
  • the source electrode 9 contacting the region 20 is conductively connected to the p-doped, source-side region 13 of the SiC layer 6 arranged on the substrate 2 in a dielectrically insulated manner, the source electrode 9 simultaneously forming the first main current contact of the component.
  • the source-side region 13 is followed by the weakly electron-conducting SiC drift zone 12, which absorbs the reverse voltage, and the p + -doped SiC region 8, which is contacted by the drain electrode 10.
  • the drain electrode 10 forms the second main current contact of the component.
  • the source-side region 13 of the SiC layer 6 consists of a multiplicity of p + -doped partial regions 13 'which are spaced apart from one another in the z direction, an n + - between adjacent partial regions 13' in each case doped SiC-terminal region 21 (doped concentration "10 18-10 19 cm” 3) is arranged, while the p + doped portions 13 are 'a comb-shaped conductor line system 22 with the source electrode 9 in combination, the n +. -doped connection areas 21 contacted by the comb electrode 23 assigned to the region 19 of the Si-MOS transistor.
  • the cross section of the IGBT shown in FIG. 3 in mirror symmetry with respect to the axis 3 essentially differs from the SiC-MOS transistor described in section a) in that the drain electrode 10 has a p + -doped region 24 ( Dopant concentration «10 18 - 10 19 cm “ 3 ) is contacted and the area 24 is preceded by an n-doped area 25 (dopant concentration «10 16 - 10 17 cm " 3 ) serving as an anti-punch zone.
  • the electrons flow from the source electrode 9 into the n + -doped region 7, via the channel forming on the gate-side surface of the p-doped region 13 into the weakly electron-conducting SiC drift zone 12, in the direction of the arrow further to the n-doped region 25, the p-doped region 24 and finally via the drain electrode 10.
  • the gate electrode 14 is again embedded in the SiO 2 layer 11 covering the drift zone 12 and is arranged above the source-side, p + -doped region 13.
  • the provided with an Si0 2 layer 4 substrate 2 consists of p + -doped silicon.
  • the SiC layer 6 of the thyristor shown in cross section in FIG. 4, arranged on the Si0 2 layer 4 of the p + -doped Si substrate 2, has the same sequence of regions 7/13/12/25/24 of different conductivity in the lateral direction like the SiC layer 6 of that described above IGBTs, a SiO 2 layer 11 again covering the weakly electron-conducting drift zone 12 arranged between a p-doped region 13 contacted by a gate electrode 14 'and the n-doped region 25.
  • the n + -doped region 7 is provided with a metallization 26 serving as a cathode, the p + -doped region 24 with an anode metallization 27.
  • the simplest construction of the semiconductor components according to the invention has the SiC diode shown in cross section in FIG. It essentially consists of a p + -doped Si substrate 2 provided with an Si0 2 passivation 4, an SiC layer 6 arranged on the Si0 2 layer 4, and an Si0 2 partially covering the SiC layer 6.
  • Layer 11 The field-absorbing, weakly electron-conducting SiC drift zone 12 is arranged between an n + -doped region 24 provided with a cathode metallization 27 and a p + -doped region 7 provided with an anode metallization 26.
  • the starting point of the method for producing the MOS transistor illustrated in FIG. 1, which is explained with reference to FIG. 6, is a p + -doped Si substrate 2 provided with a thermally grown SiO 2 layer 4 and an example (10) -oriented Si -Substrate 28, on the surface of an approximately 1-2 ⁇ m thick SiC layer 6, in particular by using the technique described in [3] was deposited from the gas phase under atmospheric pressure. Both substrates
  • the SiC layer 6 comes to lie on the Si0 2 passivation 4 of the highly doped substrate 2 (see FIG. 6b).
  • the Si serving as the carrier material for the SiC is completely removed by using a sequence of grinding, lapping and etching steps.
  • the semi- body, the SiC layer 6 is structured according to the Si0 2 etching mask used.
  • the necessary n + , p and p + implantations for defining the source and drain regions 7/13/8 are then carried out (see FIG. 6d), the MOS gate oxide and the gate electrode 14 are produced, an intermediate oxide 11 applied, contact holes etched and the conductor / electrode metallizations 9/10 applied and structured (see also the section "Process Flow" in [1] ) •
  • the semiconductor components shown in FIGS. 2 to 5 can also be produced in a corresponding manner, wherein the SiC can also be replaced, for example, by the GaAs having a high electrical breakdown field strength.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thyristors (AREA)
  • Thin Film Transistor (AREA)

Abstract

Dans le cas des cartes intelligentes de puissance à seuil élevé, les composants semi-conducteurs de puissance occupent souvent plus de la moitié de la surface totale de la puce. Pour pouvoir fabriquer les cartes intelligentes à moindre coût, il faut réduire la consommation en matériau et notamment la surface des zones de dérive des composants semi-conducteurs de puissance. Le carbure de silicium possède une intensité de champ de claquage environ 10 fois supérieure à celle du silicium. L'intégration des éléments d'absorption de tension d'un composant semi-conducteur en carbure de silicium permet de réaliser une zone de dérive nettement réduite pour une tension de blocage identique. Dans un transistor MOS-SiC à conduction latérale de courant, la couche SiC (6) qui a une épaisseur d'environ 1 à 2 mu m et est recouverte d'une couche SiO2 (11), est appliquée sur un substrat Si (2) en étant diélectriquement isolée. Deux zones SiC (7, 8) respectivement dopées n<+> servent de contacts de source ou de drain. Le canal conducteur d'électrons se forme à la surface d'une zone dopée p<+> (13) de la couche SiC (6), surface opposée l'électrode de grille (14). Cette zone (163) est liée, dans la direction latérale, à la zone de dérive SiC (12) présentant seulement une faible conduction d'électrons.
EP98954124A 1997-09-10 1998-09-07 Composant semi-conducteur comportant une zone de derive Withdrawn EP1018163A1 (fr)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE19739813 1997-09-10
DE19739813 1997-09-10
DE19741928 1997-09-23
DE19741928A DE19741928C1 (de) 1997-09-10 1997-09-23 Halbleiterbauelement
PCT/DE1998/002625 WO1999013512A1 (fr) 1997-09-10 1998-09-07 Composant semi-conducteur comportant une zone de derive

Publications (1)

Publication Number Publication Date
EP1018163A1 true EP1018163A1 (fr) 2000-07-12

Family

ID=26039867

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98954124A Withdrawn EP1018163A1 (fr) 1997-09-10 1998-09-07 Composant semi-conducteur comportant une zone de derive

Country Status (4)

Country Link
US (1) US6388271B1 (fr)
EP (1) EP1018163A1 (fr)
JP (1) JP2001516156A (fr)
WO (1) WO1999013512A1 (fr)

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US6011278A (en) * 1997-10-28 2000-01-04 Philips Electronics North America Corporation Lateral silicon carbide semiconductor device having a drift region with a varying doping level
JP4290905B2 (ja) * 2001-07-10 2009-07-08 Ｎｅｃ液晶テクノロジー株式会社 有機膜の平坦化方法
FR2876497B1 (fr) * 2004-10-13 2007-03-23 Commissariat Energie Atomique Revetement a base de mgo pour l'isolation electrique de substrats semi-conducteurs et procede de fabrication
JP4876418B2 (ja) * 2005-03-29 2012-02-15 富士電機株式会社 半導体装置
EP2033212B1 (fr) * 2006-06-29 2013-10-16 Cree, Inc. Procédé de fabrication d'un dispositif pmos de carbure de silicium
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US7728402B2 (en) * 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
EP2631951B1 (fr) 2006-08-17 2017-10-11 Cree, Inc. Transistors bipolaires haute puissance à grille isolée
US8835987B2 (en) * 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
JP2010141244A (ja) * 2008-12-15 2010-06-24 Mitsumi Electric Co Ltd 半導体装置
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8629509B2 (en) * 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8541787B2 (en) * 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US8389348B2 (en) * 2010-09-14 2013-03-05 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
WO2013036370A1 (fr) 2011-09-11 2013-03-14 Cree, Inc. Module d'alimentation à haute densité de courant comprenant des transistors à topologie améliorée
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
GB201819570D0 (en) * 2018-11-30 2019-01-16 Univ Surrey Multiple-gate transistor

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Also Published As

Publication number Publication date
JP2001516156A (ja) 2001-09-25
WO1999013512A1 (fr) 1999-03-18
US6388271B1 (en) 2002-05-14

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