EP0929041B1 - Method and arrangement for operating a bus system - Google Patents

Description

The present invention relates to a method according to the preamble of claim 1 and an arrangement according to the preamble of claim 17.

Such a method or an arrangement is essentially in the US 5533204 described.

Bus systems for microprocessors, in particular for microcontrollers, in which a bus system is provided for the connection of peripheral units to a processor core are, for. B. off Electronics Report 10a, October 1990 , known. There is shown on page 58 ff., In particular on page 59 and the accompanying figure, the basic structure of such a microprocessor. The described microprocessor consists of a central processing unit (core processor) and various peripheral units (serial I / O, timer, DMA controller). All units are interconnected via an internal bus (inter-module bus). Furthermore, a bus control unit (system interface) is provided, which connects an external connectable bus with the internal bus.

The access to a connected to this bus peripheral unit is usually such that the accessing functional unit, this is usually the central processing unit or another bus master, the addresses of the peripheral unit to be addressed applies to the address bus and applies the data to be transferred to the data bus , By means of control signals, the data transmission then takes place in various ways. In a bus system which operates in demultiplex mode, the address signals are simultaneously transmitted to associated address lines. In bus systems that operate in multiplex mode, a part of the address can be placed on the data bus and these are temporarily stored by a memory in the peripheral unit. The remainder of the address is then transferred to the address lines of the address bus.

If the respective address is present, the associated peripheral unit is selected and the corresponding data is applied to the data bus by the central processing unit or the addressed peripheral unit, depending on whether it is written or read. During the actual data transmission, the following addresses must constantly be present on the address bus in order to ensure a valid data transmission.

Are very fast central processing units used, such. As Risc processors, however, often the transmission speed is not sufficiently high on such buses. Ever higher transmission rates are thus sought.

From the DE 43 17 567 A1 a generic method for operating a bus system and an arrangement for carrying out the method is known. The bus system described there has a master unit, which via a bus with a Slave unit communicates under control of a bus control unit. In the presence of multiple master units, the bus control unit controls the bus arbitration, that is, the allocation of the bus to one of the master units, as well as the control of the data transmission in case of a timeout. The actual data transmission is then carried out in the respective active master unit and the slave unit addressed by it. In this case, the properties of a Buszyklusses such. As the data width, access to data or control area, wait cycle, time-out, etc., encoded transfer.

However, as the on-chip integration of microcontroller or microprocessor systems becomes more complex, communication between the various components of the system becomes a critical factor in the performance of the entire system. Such a bus system typically involves more and more superordinate units (master units) and subordinate units (slave units). The communication of these so-called multi-master units via the bus with the various slave units or peripheral units is thus becoming increasingly complicated. This necessitates a smarter and more flexible protocol for operating the bus and the units involved in the bus system.

Based on this prior art, it is therefore an object of the present invention to provide a method and an arrangement for operating a bus system, which enables a more flexible data transmission between the units connected to the bus system.

• in der ersten Konfiguration die Datenübertragung aufgeteilt wird in einen Anforderungsdatentransfer und in einen Antwortdatentransfer, und daß in der Zeit zwischen Anforderungsdatentransfer und Antwortdatentransfer der Bus freigegeben wird für die Datenübertragungen weiterer übergeordneten Einheiten und untergeordneten Einheiten, und daß in der zweiten Konfiguration der Bus zwischen Anforderungsdatentransfer und Antwortdatentransfer nicht freigegeben ist, und daß
• mindestens eine der am Bussystem beteiligten Einheiten eine Logikschaltung zum Anfordern, Ablehnen und Auswählen der Datenübertragung in der ersten Konfiguration oder in der zweiten Konfiguration aufweist.

This object is achieved by providing the claimed in the characterizing parts of claims 1 and 18 features. Accordingly, it is provided that

• in the first configuration, the data transfer is divided into a request data transfer and a response data transfer, and in the time between request data transfer and response data transfer the bus is released for the data transfers of further superordinate units and subordinate units, and in the second configuration the bus between request data transfer and Reply data transfer is not released, and that
• at least one of the units involved in the bus system has a logic circuit for requesting, rejecting and selecting the data transmission in the first configuration or in the second configuration.

Embodiments and developments are characteristics of the other dependent claims.

Figur 1

ein prinzipielles Blockschaltbild einer erfindungsge- mäßen Anordnung;

Figur 2

einen zeitlichen Verlauf verschiedener Signale auf den Signalleitungen des erfindungsgemäßen Bussystems;

Figur 3

ein vorteilhaftes Ausführungsbeispiel für die Imple- mentierung des erfindungsgemäßen Bussystems;

Figur 4

ein weiteres vorteilhaftes Ausführungsbeispiel für die Implementierung des erfindungsgemäßen Bussystems.

The invention will be explained in more detail with reference to the embodiments specified in the figures of the drawing. It shows:

FIG. 1

a schematic block diagram of an inventive arrangement;

FIG. 2

a time course of various signals on the signal lines of the bus system according to the invention;

FIG. 3

an advantageous embodiment for the imple- mentation of the bus system according to the invention;

FIG. 4

a further advantageous embodiment of the implementation of the bus system according to the invention.

FIG. 1 shows a schematic block diagram of a bus system according to the invention. The bus system has a higher-level unit 1 and a lower-level unit 2. Hereinafter, the superordinated unit 1 is referred to as a master unit and the subordinate unit 2 as a slave unit. The master unit 1 can by a central processing unit such. B. a Risc processor are displayed. The slave unit can be realized, for example, by any type of peripheral unit, memory unit, or the like. In this case, a peripheral unit can be designed both as a slave peripheral unit and as a master peripheral unit. It would also be conceivable that a slave unit 2 is also formed by a central processing unit or by a co-processor.

As in FIG. 1 indicated, several master units 1 and several slave units 2 may be involved in the bus system. Such systems, involving multiple master units on a single bus 3, are also referred to as multi-master bus systems. The number of master units 1 and slave units 2 is system-dependent and not further defined.

The master units 1 and the slave units 2 are connected to each other via a bus 3. The bus 3 includes a plurality of address lines, data lines and control lines. In addition, a bus control unit 4 is provided between the master units 1 and the slave units 2, which performs an arbitration and control of the bus 3.

6 denotes a data bus and 5 denotes an address bus. The data bus 6 is operated bidirectionally between master units 1 and slave units 2. The address bus 5, however, is typically operated unidirectionally between master units 1 and slave units 2 and the bus control unit 4. In addition, the bus 3 has a plurality of control lines 9 ... 22, via which the data transmission is controlled. Furthermore, the bus system has a clock line 7 and at least one reset line 8.

The following is a more detailed description of the bus lines of the bus system and the signals transmitted to it:

System signals: Clock line 7:

Clock signal (CLK signal); via the clock line 7, the bus clock can be coupled into each of the units involved in the bus system. The bus clock can be used as a reference for the timing of the signal processes via the bus 3. Ie. The bus 3 can be allocated to only one of the master units 1 via the bus control unit 4 at one clock period.

Reset line 8:

Reset signal (RES signal); The generated reset signal can be used to reset the units involved in the bus system. During the startup phase, the reset signal may be asynchronous, while in normal operation it is activated in synchronism with the clock signal. However, the deactivation of the reset signal typically always takes place isochronously.

Signals of the bus control unit 3: Control line 19:

Bus request signal (REQ signal); With the bus request signal, a master unit 1 requests the bus 3 at the beginning of a bus cycle for a data transmission with a slave unit 2. Are several master units 1 involved in the bus system, then each of the master units 1 has a separate line to the bus control unit 4.

Control line 20:

Bus grant signal (GNT signal); With this allocation signal, an allocation unit 23 within the bus control unit 4 informs the master unit 1 when it is authorized to access the bus 3 and when it can start the data transfer.

Control line 21:

Lock signal; With this so-called blocking signal, a master unit can perform 1 consecutive bus cycles without the data transmission being interrupted by one or more other master units 1.

Control line 22:

Slave select signal (SEL signal); The slave select signal is used to select a slave unit 2. For this purpose, each addressable via the bus 3 as a slave unit 2 unit has a signal input, in which the slave select signal to select the respective slave unit 2 at a data transmission can be coupled.

Address and data signals: Address bus 5:

Address signal (A signal); the address signals on the address bus 5 are driven by the master unit 1 involved in a data transmission. These address signals are then coupled into an address decoder 24 of the bus control unit 3. Starting from this address signal, the slave select signal is then generated for selecting the corresponding addressed slave unit 2. In this case, not all address lines are used to generate the slave select signal, but typically only the necessary number of upper address lines.

In addition, a partial address can be directly coupled via a part of the address lines 5 into the corresponding slave unit 2. The address width of the address bus 5 can be 8, 16, 32 bits. For the sake of simplicity, it is assumed below that the address bus 5 has an address width of 32 bits. This address is coupled into the address decoder 24 while the necessary for internal addressing number (2 to n) bits are coupled directly into the slave unit 2.

Data bus 6:

Data signal (D signal); the data signals on the data bus 6 are bidirectionally driven by either the master unit 1 or the slave unit 2. The data direction depends on whether during a bus cycle the master unit 1 writes data to the data bus 6 (write mode) or reads out data from the data bus 6 (read mode). The number of data lines 6 of the data bus or the data bus width may be 8, 16, 32 or 64 bits, depending on the system implementation. Hereinafter, it is assumed that the data bus 6 has a data bus width of 32 bits.

Control signals: Control line 9 (ID bus):

TAG signal; To perform a data transfer transfer, the master unit 1 sends a so-called identification signal (TAG signal) to the addressed slave unit 2. This identification signal is used to address the correct bus participant for the response. This ensures that each of the master units 1 is only involved in a maximum of one data transfer at a time. The Bus width of the ID bus thus also limits the maximum number of master units 1 involved in the bus system. In the present case, this is a 4-bit ID bus. This means that a maximum of 16 master units 1 can be involved in the bus system.

Control line 10 (operation code bus):

Operation code signal (OPC signal); With the operation code signal 1 additional characteristics of a bus cycle are transmitted coded by the master unit. Such features may include, for example, the size of the transmitted data unit (8/16/32/64 bits), wait cycles, shared data transfer in request data transfer and response data transfer (shared blocks), duration of the interruption between request data transfer and response data transfer, acknowledge signals, ect. be. The control lines of the operation code bus 10 are driven by the respective master involved in the data transfer. That is, in a shared data transfer and the addressed slave unit 2 can drive the operation code bus 10, in which case the slave unit 2 acts as a master.

The designated with 10 operation code bus may, depending on the scope of the coded operation code signals consist of several individual signal lines, z. B. from four individual lines (4 bits).

Control line 11:

Abort signal; This abort signal can be used to undo or abort an already started data transfer.

Control line 12:

Supervisor signal (SVM signal); This monitoring signal distinguishes whether the master unit involved in the data transmission 1 is operated in the so-called supervisor mode or in user mode. The user mode and the supervisor mode are two different levels of access: registers and addresses that have supervisor mode access can not be written or read in user mode. In this case, an error message must be output. Registers and addresses that have user-mode access can be easily described or read in supervisor mode. The supervisor mode is therefore higher than the user mode. The current bus master thus signals with the SVM signal in which of these modes it is currently working.

Control line 13 (ACK bus):

Acknowledge code signal (ACK signal); This confirmation signal is generated by the slave unit 2 involved in a data transfer. This slave unit 2 indicates via the acknowledgment signal whether, for example, valid data is available, whether data has been processed, whether waiting cycles have been inserted, whether error conditions have occurred during a current bus cycle, etc. The acknowledgment signals on the control lines 13 are typically transmitted in coded form , In the present case, the ACK bus 13 is 2 bits wide.

Control line 14:

Ready signal (RDY signal); the confirmation signal on the control line 14 is driven by the slave unit 2 involved in a data transmission and marks the end of the corresponding data transmission. In the case that the data transmission via wait cycles, that is not via shared blocks, takes place, the control line 14 can also be set inactive.

Control line 15:

No split signal; This signal, which is driven by the master unit 1, can be used for data transmission by wait cycles be forced, ie the data transfer is then not in split blocks.

Control lines 16, 17:

Write / Read signals (WR / RD signals); With the read signal or the write signal, a master unit 1 indicates, at the beginning of a bus cycle of the slave unit 2 addressed via the slave select signal 22, whether data is transmitted from or to this slave unit within this bus cycle. The read / write lines 16, 17 are driven by the master unit 1 involved in the data transmission.

In an advantageous specific embodiment, a special read / change / write mode can also be provided here. The slave unit 2 is notified of the execution of such a special data transfer by read-write control lines 16, 17. It can then protect the bits that have not been changed. For example, if only one bit has been changed, only that bit is written back so that interim changes in the other bits are not lost.

Control line 18:

Time-out signal (TOUT signal); via this time-out signal, the bus control unit 4 aborts an already started data transmission between the master unit 1 and the slave unit 2, for example because of an inadmissibly long occupancy of the bus access for the system. If the time-out signal is set active, the master unit 1 and slave unit 2 involved in the data transmission must set their actively-driven signal lines inactive or switch them off. The time of the bus occupation determining the shutdown, ie the number of clock cycles, can be fixed or variable in the bus control unit 4.

The elements of the bus system and their function are explained in more detail below.

In the present example, a plurality of master units 1 and slave units 2 are involved in the bus system. The master unit 1 thus has a master interface and the slave unit 2 has a slave interface to the bus 3. However, it would also be possible that a master unit 1 acts as a slave unit 2 or a slave unit 2 also acts as a master unit 1. Such units are referred to as master / slave units and have a master-slave interface to the bus 3. The use of master-slave units instead of master units 1 is particularly advantageous since this requires only a slightly greater implementation effort, but considerably increases the functionality or flexibility of this master unit 1.

Master units 1 and slave units 2 communicate with each other via the address bus 5 and via the control signals on the control lines 10, 16, 17, 21 (from master to slave) and via the control signal on the control line 13 (from slave to master).

The maximum address bus width typically depends on the system memory. A master unit 1 must be connected to all address lines of the address bus 5. On the other hand, a slave unit 2 only has to be connected to these address lines of the address bus 5, which it requires for the respectively internal decoding of the address signal. In the present example, the slave unit 2 needs only 4 bits, i. H. four address lines, for decoding the respective address signal.

The maximum data width of the data bus is determined by the maximum size of the largest data type over the data bus 6 is to be transmitted during a data transmission. Typical data types are, for example, 1 byte (8 bits), 1 half word (16 bits), 1 word (32 bits), 1 double word (64 bits). The minimum data width is determined by the data size of the central processing unit. It is also possible, in particular for the data transfer of small amounts of data, for example to peripheral units, to reduce the number of data lines of the data bus 6 to these slave units 2. However, the reduction of the data lines in the address of the addressed slave unit 2 must be taken into account.

A data transmission on the data bus 6 always takes place between a master unit 1 and a slave unit 2. After allotment of the bus 3 by the bus control unit 4, the master unit 1 selects the slave unit 2 required for data transmission via an address which is transmitted on the address bus 5 will, off. The decoding of this address can be done centrally via the address decoder 24 in the bus control unit 4 or decentralized in a special address decoder in the slave unit 2. Each unit addressable as slave unit 2, i. H. possibly also a master unit 1 (for example a so-called master-slave unit) must provide an input for coupling in the select signal for the control line 22.

The bus 3 can be operated such that the addresses on the address bus 5 in non-multiplexed operation or on the address bus 5 and data bus 6 in multiplexed operation are transferable. The selection of the transmission of the addresses in the multi-bit mode and / or in the demultiplex mode is typically performed by the bus control unit 4 or the corresponding master unit 1. In the present embodiment, however, it is assumed that the bus 3 is operated in the demultiplex mode.

The bus control unit 4 typically includes an internal arbiter 23 and an address decoder 24. However, it would also be conceivable that the arbitration unit 23 and / or address decoder 24 is arranged in one of the superordinate master units 1 or slave units 2.

The bus control unit 4, the signals of the address bus 5 and control signals of the control lines 13, 14, 18 and the clock signal of the clock line 7 and a reset signal of the reset line 8 are supplied. The arbitration unit 23 controls the allocation of the bus 3 (arbitration) via the control lines 19, 20. For this purpose, the bus control unit 4 or arbitration unit 23 is connected to each of the master units 1 via a respective signal pair of the control lines 19, 20.

The arbitration unit 23 additionally has a prioritization logic. This is particularly important in a multi-master bus system of great importance. The prioritization logic in the arbitration unit 23 decides which master unit 1 can access the bus 3 with which priority.

In addition, the bus control unit 4 may have a time-out controller 25 and a reset controller 26.

The time-out controller 25 is activated via the ready signal of the control line 14. Via a so-called time-out mechanism, a bus operation of the units involved in a data transmission can be aborted in a known manner.

About the reset controller 26 all address, data and control lines 5, 6, 9 ... 22 of the bus 3 can be set to a predetermined value. It would also be possible for the reset controller 26 is arranged in one of the master units 1 or one of the slave units 2.

In addition, the bus system may include means for power management 27. These means for power management are particularly important in systems that rely on a local power supply, such as a battery or a rechargeable battery, of particular importance. The means for power management 28 may have multiple modes of operation. The simplest operating mode is sleep mode. In sleep mode, the signal lines of bus 3 are simply switched off. In the present example this is done via the bus control unit 4. Another possibility is the slow-down mode. In slow-down mode, the power consumption of all units involved in the bus system is shut down, thus preventing unwanted charging or discharging of the bus lines. In particular, in slow-down mode, the frequency with which the bus signals change their state is reduced. This leads to reduced power consumption. The tension remains unchanged. Energy consumption is thus significantly reduced in both modes.

Furthermore, the bus system contains a default master. The default master is typically formed by one of the master units 1. The default master receives the bus access in the event that no one else requests the bus 3. In this case, the default master ensures that corresponding "empty transfers" take place on the bus 3. Among other things, this serves to reduce the power consumption.

The provision of a default master has the advantage that in the case of a later intended data transfer, the default master can perform a data transfer transfer without a request signal via the control line 19. In this way, a whole clock cycle can be saved. typically, For example, the default master is the central processing unit (CPU). However, it would also be conceivable that the last involved in a data transfer master unit 1 each as the default master reserves the access to the bus 3.

According to the invention, the newly introduced bus system can be operated by means of two fundamentally new and different operating modes. In the first mode, the data transmission is split-split, while in the second mode, data transmission is not in split blocks (non-split-transfer) according to the prior art.

In the case of split transfer, the data transfer is subdivided into two transfer blocks, the so-called request transfer and the so-called reply transfer. In the request transfer, information such as the destination address, data size, master identification (master ID) is transmitted from a master unit 1 to the addressed slave unit 2. This request transfer typically takes only one clock cycle. The request transfer and the response transfer are separated by at least one bus cycle.

In this meantime, the addressed slave unit 2 internally collects the requested data and prepares it for the response transfer. In this intermediate time between request transfer and response transfer, the bus is again available to other units participating in the bus system. This means that at least one additional data transfer can be carried out in this intermediate time.

During the response transfer then the addressed slave unit 2 takes control of the bus 3 and thus acts as a master. The slave unit 2 then sends as master the requested data to that indicated by the TAG signal Master unit 1, which requested the transfer. This master unit 1 thus acts as a slave. The TAG signal in this case has the essential task that the receiving unit can recognize the response transfer on the bus 3 as destined for it, since in the meantime the bus 3 was enabled and other master units 1 could have access to the bus.

This change of master and slave and the release of the bus 3 in the meantime between the request transfer and the corresponding response transfer for other participating in the bus system units is thus characteristic of the split transfer.

The response transfer of the slave unit 2 functioning as the master can be interrupted at any time and resumed at a later time. At the time of the interruption of the data transmission, for example, a data transmission from another master unit 1 and slave unit 2 can take place. So that the data transmission can be properly continued after an interruption, both the master unit 1 and the responding slave unit 2 must be able to detect an interruption as such. In addition, both units 1, 2 must be able to understand which of the data have already been sent and which are not yet, so that after the interruption, the data transmission can be continued easily at the end of the last sent data block. The end of a data transfer is indicated by a special code on the OPC bus 10. If a data transfer is not interrupted, it can also be locked at any time by a lock signal.

It is of course also conceivable that several split-transfer data transfers are open at the same time because the corresponding slave units 2 collect the data in parallel. It is also conceivable that individual slave units 2 have multiple split transfers open. The priority for the processing of the individual split transfers depends on several criteria and the system requirements. In the present example, each slave unit 2 can have only one split transfer open. The priority is set so that the first request is also processed first. There are also methods available to cancel the processing of open split transfers or to start with new conditions.

Another possibility that a data transmission can not take place or can not be continued, for example, that the addressed slave unit 2 is locked or the corresponding register can not provide the data in the desired speed. Typically, though not necessarily, one master unit and one slave unit 2 each have only a single shared data transfer in progress.

In non-split transfer, the data transfer can be carried out, for example, in blocks of defined length or in individual transfers. In both cases, a dynamic number of wait cycles (wait-states) is supported. The new bus system is preferably operated in addition to the different operating modes. The different methods for operating the bus system can be operated alone or alternately depending on the requirements of the bus system. In this way, the new bus system gets the highest possible flexibility.

The data transmission according to the invention by means of split transfer and non-split transfer will be explained in more detail below on the basis of a signal-time diagram. In FIG. 2 the time course of various signals for a data transfer in split-transfer is shown.

FIG. 2 shows the transfer of four contiguous data units (32 bits) from a slave unit 2 to a master unit 1. As a reference for the timing on the bus 3, the clock signal CLK is used on the clock signal line 7. Before and after a data transfer on the bus 3, ie in the first clock cycle and in the ninth clock cycle, the bus 3 is in the waiting state.

In the second clock cycle, the bus control unit 4 of the master unit 1 to the bus 3. The master unit 1 starts the data transmission and drives various control signals on the control lines 9, 10, 16, 17, 21 and the address bus 5. During the second clock cycle, the address information on the address bus 5 is centrally in the slave unit 2 or decentralized in the Bus controller 4 or decoded in the address decoder 24. Via the control lines 10, the request of a split transfer in 4 blocks is sent via the OPC signal (SBTR4 = split block transfer request (4 transfers)) to a slave unit (addr 1). The master unit 1 is characterized by a TAG signal (ID). Thereafter, the bus 3 is released again for the third clock cycle.

In the third clock cycle, the addressed slave unit 2 confirms the request of the master unit 1 for a split data transmission by means of an ACK signal (SPT = Split Transfer) on the control line 13.

In the fourth clock cycle, the slave unit 2 requested for the split transfer now functions as the master. However, this does not necessarily assume that this slave unit 2 already has the requested amount of data. At the beginning of the fourth clock cycle, the slave unit 2 starts the address bus 5 and the signals on the corresponding control lines 10, 11, 12 16 drive. The data will be according to the pipeline architecture driven by one cycle. These are therefore several consecutive writes. The slave unit 2 then starts the response transfer via the OPC signal (SBR = split-block-response), which indicates to the corresponding designated master unit 1 that the data response is being sent immediately. The master unit 1 is characterized by the TAG signal (ID). At the same time, the control line 16 is set active with the write signal.

It would also be possible for the reply transfer of the sending slave unit 2 to take place at a later time if, for example, a higher-priority data transfer is to be processed beforehand.

In the fifth and sixth clock cycle, the first two data blocks (Data 1, Data 2) are sent via the data lines 6. However, the sending slave unit 2 does not yet have to have the entire amount of data to be sent. At this time, only the first two data blocks need to be in the write register of the slave unit. Via the ACK signal (NSC = No Special Condition), the receiving master unit 1 confirms the correct receipt of the data or signaled error conditions.

In the seventh clock cycle, the third data block (Data 3) is sent. At the same time, the slave unit 2 terminates the response transfer to the former master unit 1 via an OPC signal (SBRE = split-block-response-end). This signal denotes the last transfer of the reply transfer. The data in the following bus cycle are thus the last ones to be sent.

In the eighth clock cycle, the fourth and last data block (Data 4) is transmitted and the bus 3 is released again in the ninth clock cycle.

In FIG. 2 the pipelining system is particularly easy to recognize. In the fourth clock cycle, the address and the signals on the control lines 9, 10, 16, 17 are output. Data transfer for this cycle occurs one clock cycle later.

In FIG. 2 the master unit 1 requests a data transfer with split-transfer. However, it would also be conceivable that the addressed slave unit 2 rejects the data transfer in the split transfer and converts it into a data transfer of several individual data transfers. This is done via the appropriate ACK code.

Another possibility arises when the master unit 1 requests a data transfer in the non-split transfer and the addressed slave unit 2, however, rejects this non-split transfer and determines a data transfer in the split transfer.

Finally, it is also possible that the master unit 1 via a special control bit (no-split signal) on the control line 15 forces a data transfer in non-split transfer. Furthermore, the slave unit 2 has the opportunity to reject these transfers due to other priorities.

In order to be able to meet these requirements, the master units 1 and slave units 2 according to the invention must have a logic circuit 28. This logic circuit 28 may request, reject and select data transmission in split-transfer or non-split transfer. This logic circuit 28 also includes means for timing the data transmission.

In the present exemplary embodiment, the subordinate units 2 have a buffer memory device 29. The Buffer size should be chosen so large that the data response transfers can be dealt with at optimal speed.

The buffer memory 29 is necessary when a data transfer is aborted during the data transfer by the abort signal. After aborting, the previous data must be available again.

FIG. 3 shows an example of an advantageous implementation of the bus system according to the invention.

The bus system according to the invention is implemented here as a so-called system-on-chip on a semiconductor device 100. At 130 is in FIG. 3 the bus is called. A total of seven master units 110... 116 and one slave unit 120 are connected to the bus 130. The slave unit 120 is realized here by a peripheral unit. The master units 110 ... 116 are formed in the present example as master-slave units and each have a master-slave interface M / SI / F on.

In the present example, the first master unit 110 is a memory unit. The master unit 111 is a processor unit, for example, a central processing unit (CPU) or a Riscprozessor. The master unit 112 is another processor unit, for example, this processor unit may be formed by a co-processor. The master unit 113 is a peripheral unit. The master unit 114 is here a DMA unit (direct memory access). The master unit 115 is a bus bridge unit connected to an external bus 101 here. The master unit 116 represents an external bus control unit. The external bus control unit 116 thus forms the interface between internal bus 130 and an external connected bus, which is not here is shown. The control of the data transmission via the bus 130 as well as the control and arbitration of the units 110... 116, 120 connected to the bus 130 are performed by a bus control unit 140.

FIG. 4 shows a further advantageous embodiment of the implementation of the bus system according to the invention.

With 200 here is an integrated circuit designated. The integrated circuit 200 includes a bus 230. The bus 230 includes an address bus 250 and a data bus 260. The other control lines of the bus 230 are shown here only schematically and not further quantified. In the example of FIG. 4 On the bus 230 three master units 210 ... 212 and a slave unit 220 are connected. The slave unit 220 is formed here by a peripheral unit.

The master unit 210 is formed by the central processing unit. The central processing unit includes a core device 210a. An address register 210b and a data register 210c are connected to the core device 210a via bidirectionally operated signal lines. The master unit 211 is a memory device that may be formed, for example, by an on-chip memory or a so-called embedded memory. This memory device 211 may be formed as RAM, ROM, SRAM, etc. It would also be conceivable that the memory 211 is formed as a buffer memory device. The master unit 212 is designed as an external bus controller.

The bus control of the internally formed bus 230 is performed by the bus control unit 240. The external bus control unit 212 forms the interface between internal bus 230 and an external bus 202. The external bus 202 has an address bus 203, a data bus 204 and a Control bus 205 on. The external bus may connect the semiconductor device 200 to external units such as an external memory 201 or the like.

The invention is particularly advantageous when used in a microprocessor or microcomputer.

Claims (27)

1. Method of operating a bus system comprising

   (1) at least one primary unit (1),

   (2) at least one secondary unit (2),

   (3) a bus (3) between the primary unit (1) and the secondary unit (2) having at least one address bus (5), at least one data bus (6) and at least one control line (9..22) and

   (4) at least one bus control unit (4) controlling the bus (3) and controlling at least one data transmission between a primary unit (1), allocated to the bus, and the secondary unit (2) addressed by this primary unit (1),

   (5) the data transmission being carried out in a first configuration or in a second configuration,
   and

   (a) in the first configuration, the data transmission being split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus (3) being cleared for the data transmissions of other primary units (1) and second units (2), and

   (b) in the second configuration, the bus (3) not being cleared between the request data transfer and the response data transfer,
   a control signal on at least one of the control lines (10) being used to specify the mode in which the primary unit accesses the bus (3), characterized in that, by means of a second configuration signal on at least one of the control lines (10), the secondary unit (2) rejects the data transfer, specified by the primary unit (1), in the first configuration or in the second configuration and performs the data transfer in the second and/or in the first configuration.
2. Method according to Claim 1, characterized in that

   (a1) for the request data transfer in the first configuration, the primary unit (1) allocated for bus access addresses a secondary unit (2) as a master and requests a data transfer from this addressed secondary unit (2), and

   (a2) for the response data transfer in the first configuration, the addressed secondary unit (2) at least partially collects the data set intended for the response data transfer and then sends, as a master, the data set collected to the primary unit (1) which has requested the data transfer.
3. Method according to one of the preceding claims, characterized in that, by means of a first configuration signal on at least one of the control lines (10), the primary unit (1) specifies that the data transmission is carried out in the first configuration.
4. Method according to one of the preceding claims, characterized in that, by means of a third configuration signal on at least one of the control lines (15), the primary unit (1) enforces a data transfer in the first configuration or in the second configuration.
5. Method according to one of the preceding claims, characterized in that each of the primary units (1) carries out a maximum of one data transmission at the same time in each case.
6. Method according to one of the preceding claims, characterized in that the bus control unit (4) controls the allocation of the bus (3) to one of the primary units (1).
7. Method according to one of the preceding claims, characterized in that the data transmission takes place in the second configuration during wait states.
8. Method according to one of the preceding claims, characterized in that the bus operations of the address cycle and the data cycle are processed using the pipelining method.
9. Method according to one of the preceding claims, characterized in that a protection bit on at least one of the control lines (16, 17) can be used by a secondary unit (2) involved in a data transmission to prevent write access to the corresponding register of this secondary unit (2) occurring at the same time as read access is occurring.
10. Method according to one of the preceding claims, characterized in that a further control signal on at least one of the control lines (10) is used to specify the data length transmitted.
11. Method according to one of the preceding claims, characterized in that an acknowledge signal on at least one of the control lines (13) is used by the secondary unit (2) to acknowledge a data transmission.
12. Method according to one of the preceding claims, characterized in that a first status signal on at least one of the control lines (13) is used by the secondary unit (2) to indicate whether data are available for processing or whether data are currently being processed.
13. Method according to one of the preceding claims, characterized in that a second status signal on at least one of the control lines (13) is used by the secondary unit (2) to indicate whether any wait states are being inserted and/or how many wait states are being inserted.
14. Method according to one of the preceding claims, characterized in that a third status signal on at least one of the control lines (12) is used by the secondary unit (2) to indicate whether successive bus cycles have been carried out without interruption or whether any error states have occurred.
15. Method according to one of the preceding claims, characterized in that an abort signal on at least one of the control lines (11) is used by the bus control unit (4) to abort a data transmission after a predetermined time.
16. Method according to one of the preceding claims, characterized in that in a request signal and a grant signal on at least one of the control lines (19, 20) are in each case and by the bus control unit (4) to specify the allocation of the primary units (1) to the bus (3).
17. Circuit arrangement comprising

    (1) at least one primary unit (1),

    (2) at least one secondary unit (2),

    (3) a bus (3) between the primary unit (1) and the secondary unit (2) having at least one address bus (5), at least one data bus (6) and at least one control line (9..22) and

    (4) at least one bus control unit (4) controlling the bus (3) and controlling at least the data transmission between a primary unit (1), allocated to the bus, and the secondary unit (2) addressed by this primary unit (1),

    (5) it being possible for the data transmission to be carried out in the first configuration or in the second configuration, and (a) in the first configuration, the data transmission being split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus (3) being cleared for the data transmissions of other primary units (1) and second units (2), and

    (b) in the second configuration, the bus (3) not being cleared between the request data transfer and the response data transfer,

    a control signal on at least one of the control lines (10) being used to specify the mode in which the primary unit accesses the bus (3), characterized in that, by means of a second configuration signal on at least one of the control lines (10), the secondary unit (2) rejects the data transfer, specified by the primary unit (1), in the first configuration or in the second configuration and performs the data transfer in the second and/or in the first configuration.
18. Circuit arrangement according to Claim 17, characterized in that at least one of the units (1, 2) linked to the bus system has a logic circuit (28) for requesting, rejecting and selecting the data transmission in the first configuration or in the second configuration.
19. Circuit arrangement according to Claim 17 or 18, characterized in that, for a data transmission in the first configuration, both the allocated primary unit (1) and the addressed secondary unit (2) have means for timing the data transmission.
20. Circuit arrangement according to one of Claims 17 to 19, characterized in that the secondary unit (2) contains at least one buffer memory device (29).
21. Circuit arrangement according to Claim 20, characterized in that the memory size of the buffer memory device (29) is at least large enough to deal with a transfer at an optimum rate.
22. Circuit arrangement according to one of Claims 17 to 21, characterized in that at least two primary units (1) are provided and the bus control unit (4) has means for prioritizing (23) the primary units (1), the means for prioritizing (23) specifying the priority of the primary units (1) accessing the bus (3).
23. Circuit arrangement according to one of Claims 17 to 22, characterized in that at least one of the primary units (1) has a master/slave interface.
24. Circuit arrangement according to one of Claims 17 to 23, characterized in that the bus (3) can be operated in such a way that the addresses can be transmitted on the address bus (5) in non-multiplexed mode or on the address bus (5) and data bus (6) in multiplexed mode.
25. Circuit arrangement according to one of Claims 17 to 24, characterized in that at least one central processing unit is provided as a primary unit (1).
26. Circuit arrangement according to one of Claims 17 to 25, characterized in that one of the primary units (1) is provided as a default master, the default master being allocated to the bus if no other primary unit is requesting the bus (3).
27. Circuit arrangement according to one of Claims 17 to 26, characterized in that the circuit arrangement is a component of a microprocessor or a microcomputer.

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