EP0758108A3 - Current mirror arrangement - Google Patents
Current mirror arrangement Download PDFInfo
- Publication number
- EP0758108A3 EP0758108A3 EP96202214A EP96202214A EP0758108A3 EP 0758108 A3 EP0758108 A3 EP 0758108A3 EP 96202214 A EP96202214 A EP 96202214A EP 96202214 A EP96202214 A EP 96202214A EP 0758108 A3 EP0758108 A3 EP 0758108A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- transistor
- connection
- des
- kollektoranschluß
- dessen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/265—Current mirrors using bipolar transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Beschrieben wird eine Stromspiegelanordnung mit
- wenigstens einem einen ersten Leitungstyp aufweisenden Eingangstransistor, dessen Emitteranschluß mit einer Stromzuführung verbunden ist und dessen Kollektoranschluß einen Eingangsstrom führen kann,
- wenigstens einem den ersten Leitungstyp aufweisenden Ausgangstransistor, dessen Emitteranschluß mit der Stromzuführung und dessen Basisanschluß mit dem Basisanschluß des Eingangstransistors verbunden ist und dessen Kollektoranschluß ein Ausgangsstrom entnehmbar ist,
- sowie einem den ersten Leitungstyp aufweisen Bügeltransistor, dessen Emitteranschluß mit den Basisanschlüssen des Eingangstransistors und des Ausgangstransistors und dessen Basisanschluß mit dem Kollektoranschluß des Eingangstransistors verbunden und dessen Kollektoranschluß mit einem Bezugspotential gekoppelt ist.
- at least one input transistor having a first line type, the emitter connection of which is connected to a current supply and the collector connection of which can carry an input current,
- at least one output transistor having the first conductivity type, the emitter connection of which is connected to the current supply and the base connection of which is connected to the base connection of the input transistor and the collector connection of which an output current can be drawn,
- and a first transistor type having a bow transistor, the emitter connection of which is connected to the base connections of the input transistor and of the output transistor and the base connection of which is connected to the collector connection of the input transistor and the collector connection of which is coupled to a reference potential.
Um in allen Betriebszuständen eine definierte Belastung der Stromzuführung zu erhalten, umfaßt die Stromsp iegelanordnung erfindungsgemäß
- einen Steuertransistor von einem zweiten, dem ersten Leitungstyp entgegengesetzten Leitungstyp, wobei der Steuertransistor mit seinem Kollektoranschluß an den Kollektoranschluß des Eingangstransistors und mit seinem Emitteranschluß über eine Emitterstromquelle an das Bezugspotential angeschlossen und einem Basisanschluß des Steuertransistors eine Steuerspannung zum Steuern des Ausgangsstromes zuführbar ist,
- einen Widerstand, über den der Kollektoranschluß des Bügeltransistors mit dem Bezugspotential gekoppelt ist, sowie
- einen weiteren Transistor vom zweiten Leitungstyp, dessen Emitteranschluß mit dem Emitteranschluß des Steuertransistors, dessen Basisanschluß mit dem Kollektoranschluß des Bügeltransistors und dessen Kollektoranschluß mit der Stromzuführung verbunden ist.
- a control transistor of a second line type opposite to the first line type, the control transistor having its collector terminal connected to the collector terminal of the input transistor and its emitter terminal connected to the reference potential via an emitter current source and a control voltage for controlling the output current being able to be fed to a base terminal of the control transistor,
- a resistor via which the collector connection of the bow transistor is coupled to the reference potential, and
- a further transistor of the second conductivity type, the emitter connection of which is connected to the emitter connection of the control transistor, the base connection of which is connected to the collector connection of the bow transistor and the collector connection of which is connected to the current supply.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19529059A DE19529059A1 (en) | 1995-08-08 | 1995-08-08 | Current mirror arrangement |
| DE19529059 | 1995-08-08 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0758108A2 EP0758108A2 (en) | 1997-02-12 |
| EP0758108A3 true EP0758108A3 (en) | 1997-03-19 |
| EP0758108B1 EP0758108B1 (en) | 1999-12-01 |
Family
ID=7768936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP96202214A Expired - Lifetime EP0758108B1 (en) | 1995-08-08 | 1996-08-07 | Current mirror arrangement |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5682094A (en) |
| EP (1) | EP0758108B1 (en) |
| JP (1) | JPH09139636A (en) |
| DE (2) | DE19529059A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19930381A1 (en) * | 1999-07-01 | 2001-01-04 | Philips Corp Intellectual Pty | Current mirror arrangement |
| WO2020110959A1 (en) * | 2018-11-26 | 2020-06-04 | 株式会社村田製作所 | Current output circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3813607A (en) * | 1971-10-21 | 1974-05-28 | Philips Corp | Current amplifier |
| US4260945A (en) * | 1979-04-06 | 1981-04-07 | Rca Corporation | Regulated current source circuits |
| US4525682A (en) * | 1984-02-07 | 1985-06-25 | Zenith Electronics Corporation | Biased current mirror having minimum switching delay |
| US4525683A (en) * | 1983-12-05 | 1985-06-25 | Motorola, Inc. | Current mirror having base current error cancellation circuit |
| EP0173367A1 (en) * | 1984-08-22 | 1986-03-05 | Philips Electronics Uk Limited | Battery economising circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3952257A (en) * | 1974-10-29 | 1976-04-20 | Rca Corporation | Current proportioning circuits |
| US4045694A (en) * | 1975-09-26 | 1977-08-30 | Rca Corporation | Current divider |
| JPS605085B2 (en) * | 1980-04-14 | 1985-02-08 | 株式会社東芝 | current mirror circuit |
| JPS60165112A (en) * | 1984-02-08 | 1985-08-28 | Toshiba Corp | Current mirror circuit |
| US4814724A (en) * | 1986-07-15 | 1989-03-21 | Toko Kabushiki Kaisha | Gain control circuit of current mirror circuit type |
| US4771228A (en) * | 1987-06-05 | 1988-09-13 | Vtc Incorporated | Output stage current limit circuit |
| US4961046A (en) * | 1988-08-19 | 1990-10-02 | U.S. Philips Corp. | Voltage-to-current converter |
| DE68910428T2 (en) * | 1988-08-19 | 1994-05-11 | Philips Nv | Voltage / current converter. |
| JPH0535350A (en) * | 1991-07-26 | 1993-02-12 | Nec Yamagata Ltd | Constant current source |
| US5311146A (en) * | 1993-01-26 | 1994-05-10 | Vtc Inc. | Current mirror for low supply voltage operation |
-
1995
- 1995-08-08 DE DE19529059A patent/DE19529059A1/en not_active Withdrawn
-
1996
- 1996-08-05 JP JP8205976A patent/JPH09139636A/en active Pending
- 1996-08-05 US US08/692,146 patent/US5682094A/en not_active Expired - Fee Related
- 1996-08-07 DE DE59603762T patent/DE59603762D1/en not_active Expired - Fee Related
- 1996-08-07 EP EP96202214A patent/EP0758108B1/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3813607A (en) * | 1971-10-21 | 1974-05-28 | Philips Corp | Current amplifier |
| US4260945A (en) * | 1979-04-06 | 1981-04-07 | Rca Corporation | Regulated current source circuits |
| US4525683A (en) * | 1983-12-05 | 1985-06-25 | Motorola, Inc. | Current mirror having base current error cancellation circuit |
| US4525682A (en) * | 1984-02-07 | 1985-06-25 | Zenith Electronics Corporation | Biased current mirror having minimum switching delay |
| EP0173367A1 (en) * | 1984-08-22 | 1986-03-05 | Philips Electronics Uk Limited | Battery economising circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| DE59603762D1 (en) | 2000-01-05 |
| DE19529059A1 (en) | 1997-02-13 |
| JPH09139636A (en) | 1997-05-27 |
| EP0758108B1 (en) | 1999-12-01 |
| US5682094A (en) | 1997-10-28 |
| EP0758108A2 (en) | 1997-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69508720T2 (en) | DRIVER CIRCUIT FOR BRIDGE CIRCUIT WITH A BOOTSTRAP DIODE EMULATOR | |
| DE69434112T2 (en) | Power supply apparatus | |
| DE69508745T2 (en) | REGULATOR FOR A DC MOTOR | |
| DE69019784T2 (en) | Switched bridge arrangement. | |
| EP2026376A3 (en) | Electrical supply unit for plasma systems | |
| DE68915894T2 (en) | Voltage / current converter. | |
| DE2639555A1 (en) | ELECTRIC INTEGRATED CIRCUIT IN A SEMICONDUCTOR CHIP | |
| DE10213254A1 (en) | Load operating system and method therefor | |
| EP0758108A3 (en) | Current mirror arrangement | |
| DE2506196C2 (en) | DC switching device to increase the peak current | |
| EP0854574A3 (en) | Driver circuit | |
| EP1094605A3 (en) | Circuit arrangement for controlling a load with reduced stray radiation | |
| WO1996014725A1 (en) | Device for operating a gas discharge lamp | |
| DE69018870T2 (en) | Bipolar transistor circuit with distortion compensation. | |
| DE3731130C2 (en) | Voltage / current converter arrangement | |
| DE69500873T2 (en) | Device for converting bipolar optical signals into unipolar optical signals | |
| DE69012433T2 (en) | Circuit arrangement. | |
| DE69317531T2 (en) | Universal signal converter | |
| DE2900338A1 (en) | INVERTER | |
| EP0682305B1 (en) | Circuit device for generating a reference current | |
| EP0809169A3 (en) | Circuit for generating a voltage reference which can be enabled and disabled | |
| US4308578A (en) | Inverter device | |
| DE2728945C3 (en) | Semiconductor switching unit with 4-electrode PNPN switches | |
| DE60217776T2 (en) | driver circuits | |
| EP0793159A3 (en) | Circuit for generation of a supply voltage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT |
|
| AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB IT |
|
| 17P | Request for examination filed |
Effective date: 19970919 |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| 17Q | First examination report despatched |
Effective date: 19990127 |
|
| GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
| GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
| AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IT |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED. Effective date: 19991201 |
|
| REF | Corresponds to: |
Ref document number: 59603762 Country of ref document: DE Date of ref document: 20000105 |
|
| RAP4 | Party data changed (patent owner data changed or rights of a patent transferred) |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V. Owner name: PHILIPS CORPORATE INTELLECTUAL PROPERTY GMBH |
|
| GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) |
Effective date: 20000121 |
|
| ET | Fr: translation filed | ||
| PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
| 26N | No opposition filed | ||
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20010824 Year of fee payment: 6 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20010831 Year of fee payment: 6 |
|
| PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20011015 Year of fee payment: 6 |
|
| REG | Reference to a national code |
Ref country code: GB Ref legal event code: IF02 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20020807 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20030301 |
|
| GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20020807 |
|
| PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20030430 |
|
| REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |