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EP0328819A3 - Making of doped regions using phosphorus and arsenic - Google Patents

Making of doped regions using phosphorus and arsenic Download PDF

Info

Publication number
EP0328819A3
EP0328819A3 EP88311511A EP88311511A EP0328819A3 EP 0328819 A3 EP0328819 A3 EP 0328819A3 EP 88311511 A EP88311511 A EP 88311511A EP 88311511 A EP88311511 A EP 88311511A EP 0328819 A3 EP0328819 A3 EP 0328819A3
Authority
EP
European Patent Office
Prior art keywords
arsenic
phosphorus
making
doped regions
introduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88311511A
Other languages
German (de)
French (fr)
Other versions
EP0328819A2 (en
Inventor
Hideki Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=17963929&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0328819(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to EP00100837A priority Critical patent/EP1011129A3/en
Publication of EP0328819A2 publication Critical patent/EP0328819A2/en
Publication of EP0328819A3 publication Critical patent/EP0328819A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

The present invention provides a method of manufacturing semiconductor devices having impurity regions that are more shallow and which exhibit less lateral diffusion than devices manufactured in accordance with prior art technques. The method comprising the introduction of arsenic into a substrate (11). After the introduction of arsenic, phosphorus is introduced to the same portion (16) of the substrate (11). The introductions of arsenic and phosphorus may be accomplished using diffusion or ion implantation techniques.
EP88311511A 1987-12-04 1988-12-05 Making of doped regions using phosphorus and arsenic Withdrawn EP0328819A3 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00100837A EP1011129A3 (en) 1987-12-04 1988-12-05 Method for manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP307010/87 1987-12-04
JP62307010A JPH01147829A (en) 1987-12-04 1987-12-04 Manufacture of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
EP00100837A Division EP1011129A3 (en) 1987-12-04 1988-12-05 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
EP0328819A2 EP0328819A2 (en) 1989-08-23
EP0328819A3 true EP0328819A3 (en) 1989-11-29

Family

ID=17963929

Family Applications (2)

Application Number Title Priority Date Filing Date
EP00100837A Withdrawn EP1011129A3 (en) 1987-12-04 1988-12-05 Method for manufacturing semiconductor device
EP88311511A Withdrawn EP0328819A3 (en) 1987-12-04 1988-12-05 Making of doped regions using phosphorus and arsenic

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP00100837A Withdrawn EP1011129A3 (en) 1987-12-04 1988-12-05 Method for manufacturing semiconductor device

Country Status (4)

Country Link
US (1) US5814541A (en)
EP (2) EP1011129A3 (en)
JP (1) JPH01147829A (en)
KR (1) KR930000607B1 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US5096840A (en) * 1990-08-15 1992-03-17 At&T Bell Laboratories Method of making a polysilicon emitter bipolar transistor
JP3144000B2 (en) * 1990-11-28 2001-03-07 セイコーエプソン株式会社 Semiconductor device and method of manufacturing the same
US6180494B1 (en) * 1999-03-11 2001-01-30 Micron Technology, Inc. Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
KR100440078B1 (en) * 1999-12-28 2004-07-15 주식회사 하이닉스반도체 Manufacturing method of semiconductor device
JP2003031797A (en) * 2001-07-12 2003-01-31 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
US6750482B2 (en) 2002-04-30 2004-06-15 Rf Micro Devices, Inc. Highly conductive semiconductor layer having two or more impurities
US20040121524A1 (en) * 2002-12-20 2004-06-24 Micron Technology, Inc. Apparatus and method for controlling diffusion
US7297617B2 (en) * 2003-04-22 2007-11-20 Micron Technology, Inc. Method for controlling diffusion in semiconductor regions
KR100657142B1 (en) * 2005-06-03 2006-12-13 매그나칩 반도체 유한회사 Contact structure for pixel shrink of image sensor and manufacturing method
US8110469B2 (en) 2005-08-30 2012-02-07 Micron Technology, Inc. Graded dielectric layers
US8753243B2 (en) 2006-08-15 2014-06-17 United Technologies Corporation Ring gear mounting arrangement with oil scavenge scheme
US9976437B2 (en) 2006-08-15 2018-05-22 United Technologies Corporation Epicyclic gear train
CN102315121A (en) * 2010-07-02 2012-01-11 上海镭芯微电子有限公司 High-frequency transistor manufacture method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2056168A (en) * 1979-08-01 1981-03-11 Gen Instrument Corp Method of fabricating P-N junction with high breakdown voltage
GB2088129A (en) * 1980-11-20 1982-06-03 Suwa Seikosha Kk An integrated circuit mosfet and a method of making the same
EP0137645A2 (en) * 1983-08-30 1985-04-17 Fujitsu Limited Method of forming a shallow N-type region

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Publication number Priority date Publication date Assignee Title
JPS51135362A (en) * 1975-05-19 1976-11-24 Matsushita Electronics Corp Method of manufacturing silicon semiconductor element
JPS5327372A (en) * 1976-08-27 1978-03-14 Hitachi Ltd Production of s emiconductor device
JPS53147473A (en) * 1977-05-27 1978-12-22 Mitsubishi Electric Corp Production of mis type semiconductor device
US4333099A (en) * 1978-02-27 1982-06-01 Rca Corporation Use of silicide to bridge unwanted polycrystalline silicon P-N junction
JPS5519857A (en) * 1978-07-28 1980-02-12 Nec Corp Semiconductor
US4276688A (en) * 1980-01-21 1981-07-07 Rca Corporation Method for forming buried contact complementary MOS devices
JPS5736844A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Semiconductor device
US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
JPS592191A (en) * 1982-06-29 1984-01-07 Fujitsu Ltd Recognizing and processing system of handwritten japanese sentence
JPS59135767A (en) * 1983-01-24 1984-08-04 Hitachi Ltd Semiconductor device and manufacture thereof
JPS60132373A (en) * 1983-12-20 1985-07-15 Toshiba Corp Manufacture of semiconductor device
US4666557A (en) * 1984-12-10 1987-05-19 Ncr Corporation Method for forming channel stops in vertical semiconductor surfaces
JPS61137369A (en) * 1984-12-10 1986-06-25 Hitachi Ltd Manufacturing method of semiconductor device
JPS6212125A (en) * 1985-07-10 1987-01-21 Fujitsu Ltd Manufacture of semiconductor device
JPS6237967A (en) * 1985-08-12 1987-02-18 Sony Corp Manufacture of semiconductor device
JPS62193118A (en) * 1986-02-19 1987-08-25 Sanyo Electric Co Ltd Manufacture of semiconductor device
JPH0732192B2 (en) * 1987-05-26 1995-04-10 日本電気株式会社 Method for manufacturing semiconductor device
JPH03109736A (en) * 1989-09-25 1991-05-09 Sony Corp Manufacture of semiconductor device
EP0430166A3 (en) * 1989-12-01 1993-05-12 Seiko Instruments Inc. Method of doping impurity into semiconductor films and patterned semiconductor strip
US5376577A (en) * 1994-06-30 1994-12-27 Micron Semiconductor, Inc. Method of forming a low resistive current path between a buried contact and a diffusion region
US5525552A (en) * 1995-06-08 1996-06-11 Taiwan Semiconductor Manufacturing Company Method for fabricating a MOSFET device with a buried contact
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2056168A (en) * 1979-08-01 1981-03-11 Gen Instrument Corp Method of fabricating P-N junction with high breakdown voltage
GB2088129A (en) * 1980-11-20 1982-06-03 Suwa Seikosha Kk An integrated circuit mosfet and a method of making the same
EP0137645A2 (en) * 1983-08-30 1985-04-17 Fujitsu Limited Method of forming a shallow N-type region

Also Published As

Publication number Publication date
EP1011129A3 (en) 2000-12-06
US5814541A (en) 1998-09-29
KR930000607B1 (en) 1993-01-25
JPH01147829A (en) 1989-06-09
EP0328819A2 (en) 1989-08-23
KR890011027A (en) 1989-08-12
EP1011129A2 (en) 2000-06-21

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