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EP0168121B1 - Méthode et dispositif d'accès à la mémoire dans les systèmes à multi-processeurs - Google Patents

Méthode et dispositif d'accès à la mémoire dans les systèmes à multi-processeurs Download PDF

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Publication number
EP0168121B1
EP0168121B1 EP85300858A EP85300858A EP0168121B1 EP 0168121 B1 EP0168121 B1 EP 0168121B1 EP 85300858 A EP85300858 A EP 85300858A EP 85300858 A EP85300858 A EP 85300858A EP 0168121 B1 EP0168121 B1 EP 0168121B1
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EP
European Patent Office
Prior art keywords
data
buffer
processor
location
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP85300858A
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German (de)
English (en)
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EP0168121A1 (fr
Inventor
Paul K. Rodman
Joseph L. Ardini
David B. Papworth
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Prime Computer Inc
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Prime Computer Inc
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Priority to AT85300858T priority Critical patent/ATE64020T1/de
Publication of EP0168121A1 publication Critical patent/EP0168121A1/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Definitions

  • This invention is in the field of data processing and, in particular, relates to a method and apparatus for the resolution of memory access demands in multiple processor systems.
  • processors In many advanced data processing systems, a number of independent processors can have access to a main memory shared by the system. When a processor wishes only to read a particular memory location or even rewrite a specified location, access can be controlled sequentially with little cost in performance. However, it is also common for processors to perform an operation known as a read-modify-write (RMW) operation or the like. This operation involves reading data out of a selected memory location, processing the data read out, and writing modified data back into the specified location.
  • RMW read-modify-write
  • the problem of handling multiple access requests can become acute when one of the independent processors is carrying out instructions on a string of data, such as moving a string of ASCII-coded data. Since the 8-bit ASCII words (representing language characters, punctuation, etc.) are smaller than the typical 16 bit (or 32 bit) registers around which advanced systems are designed, a modification which involves changing less than the full 16 (or 32) bits often is not controlled by the system hardware.
  • a 32-bit wide memory register common to a number of processors can store two data blocks consisting of an integer value (i.e., a fortran *2 integer) on one side (the upper 16 bits) and two ASCII characters on the other side (the lower 16 bits).
  • an integer value i.e., a fortran *2 integer
  • ASCII characters on the other side
  • the lower 16 bits the integer value
  • a first processor wished to replace the ASCII characters only, it would need to read the entire register, modify the contents to keep the integer value on one side while changing the characters on the other side and then write the modified 32-bits into the memory. Since this RMW operation cannot occur instantaneously, a second processor might write a new entry into part of the register in the interim (i.e., to replace the integer value) and this data would be lost if the first processor was allowed to enter its modification without any controls.
  • the solution to date has been to exclude the second processor in one fashion or another while the first processor performs a RMW operation.
  • a computer system having a plurality of processors which can access one or more main memories via a buffer memory is disclosed in US A-3984818 (Gnadeberg et al).
  • a multiprocessor data processing system includes a main memory having a plurality of addressed locations, at least a first and a second processor each of which can independently read, modify and write data at the said addressed locations, and buffer means for storing data prior to transmission to the main memory, and is characterised in that the buffer means is content-associative, and in that the system further comprises: control means coupled to the processors, to the main memory, and to the buffer means for controlling the said read and write operations, the control means using the buffer means to store data from an addressed location accessed by the first processor for a Read-Modify-Write operation, the control means issuing a locking instruction for the said addressed location during the pendency of the Read-Modify-Write operation, and in response to a Write operation by the second processor at the said addressed location during the pendency of the Read-Modify-Write operation, the control means altering the normal sequence of memory write operations, whereby multiple processors can concurrently access and write at the same main memory addressed location.
  • Such a system may be used particularly in data processing systems which employ write-through buffers to control the movement of data between the processors and main memory.
  • a buffer is used to store a series of write instructions from a processor until the memory bus is cleared.
  • a content associative buffer can be used to permit a processor seeking to read data to poll the buffer for latest data.
  • the content-associative buffer also permits the controller to control new entries whenever data is undergoing a RMW operation.
  • a field in microcode is provided for the issuance of a directive whenever a read-modify-write sequence is initiated by a processor.
  • the directive i.e., "TAKE A LOCK”
  • TAKE A LOCK is dumped into the write buffer at the appropriate address with a tag bit denoting the operation as a lock -- not a write, as well as another tag bit identifying the processor.
  • processors seeking to merely read data from the same location will not be impeded and such other processors, in fact, can also write new data for insertion into the memory location.
  • microcode instructions further prevent the overwriting of the second processor's data by the first processor, thereby reversing the typical process wherein a second write command to same address in write buffer overrides any data residing there.
  • uninterrupted processing essentially is maintained for the two processors. This technique can be applied as well to the case of three or more processors by extrapolation.
  • Fig. 1 a general block diagram of the memory access system 10 is shown including at least two processors 12 and 14 connected to a common memory 18 via a memory bus 16 which includes a data path 16a, an address path 16b, and a command path 16c.
  • a memory bus 16 which includes a data path 16a, an address path 16b, and a command path 16c.
  • the common memory 18 is typically a high speed MOS memory of about one megabyte although the access system could also be implemented with different types of memories or memories of different sizes.
  • controller 20 Interposed between the processors 12, 14 and the memory 18 is a controller 20 and a locking content-associative write buffer 22.
  • the controller 20 is similar in most aspects to conventional controllers used to control access to memory locations.
  • the controller 20 is implemented by a combination of hardware and firmware (or microcode).
  • controller 20 can include microcode instructions for identifying RMW requests for addressing and formatting the buffer 20, and for issuing the necessary directives as described below to lock particular addresses, and to transfer data back and forth between the processors 12, 14, the memory 18 and the buffer 22.
  • Implementation of the buffer 22 can be achieved with commercially available components or individualized designs by those skilled in the art.
  • the content-associative structure is an address-organised buffer accessed by applying the address word. In one preferred embodiment, the structure contains four addressed entries.
  • the structure of the buffer 22 is shown in more detail in Fig. 2.
  • the buffer includes a plurality of address blocks A, B, etc.
  • Each address in buffer 22 corresponds to a memory location in the main memory 18.
  • Associated with each address are two sixteen-bit strings of data A1 ... A16 and A17 ... A32, a validity bit for each string V1, V2, a lock bit L, and at least one bit for identifying the processor that issues the lock directive ID. (For the case of two processors, only one bit is typically needed to distinguish between processors; however, for three or more processors, additional bits would be needed).
  • Each of the two sixteen-bit strings of data stored in buffer 22 is called a "data block".
  • the two data blocks make up a memory data word. In the illustrated embodiment, data is transferred as a block or set of two blocks. Sixteen-bit blocks are the minimum size for a data transmission.
  • the structure described above is intended for use in a system where the data path of the memory bus can accomodate thirty-two bit wide data transmissions and the operating system is designed to assure the integrity of sixteen-bit block transmissions as well.
  • the teachings herein can also be applied to sixteen-bit data transmissions and eight-bit data block designs as well.
  • Figs. 3a through 3d The operation of the memory access scheme is shown schematically in Figs. 3a through 3d.
  • a single entry in buffer 22 is shown in its initial state containing data from any one of the processors connected to the system.
  • controller 20 sets the lock bit (i.e., to a "1" value) and the validity bits V1 and V2 are initialized as well (i.e., to a " 0 ⁇ " value) indicating that one of the first or second data blocks is being modified.
  • the processor performing the modification is also identified at the same time by the identification bit ID (i.e., set to " 0 ⁇ " for CPU 0 ⁇ ).
  • controller 20 Since the buffer entry in Figs. 3a-3d is associated with an address as shown in Fig. 2, this "content-associative" characteristic is used to advantage by controller 20. If during the RMW of the CPU 0 ⁇ , another processor seeks to execute a write instruction for a particular memory location, controller 20 polls the buffer 22 for the address associated with that location. If the address is not listed in the buffer 22, the processor is allowed to write through the buffer 22 into memory 18.
  • the controller recognizes the address sought as a locked address and takes the necessary steps to preserve this new data while the RMW operation is being completed. For example, if as shown in Fig. 3c, were to write new data for the first data block, the validity bit V1 associated with that block would be set (i.e., to a "1" value) indicating that this new data is to be saved at the expense of any modified data subsequently written by CPU 0 ⁇ . (It is assumed that proper programming prevents the second processor from seeking to change that portion of the data in the buffer that is being modified by the first processor). When the first processor completes its modification of data as shown in Fig.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Hardware Redundancy (AREA)
  • Memory System (AREA)

Claims (12)

  1. Système de traitement de données à multiprocesseur comprenant une mémoire principale (18) comportant une pluralité d'emplacements adressés, au moins un premier et un second processeur (12,14), chacun pouvant indépendamment lire, modifier, et écrire des données aux emplacements adressés, et des moyens tampons (22) pour stocker les données avant leur transmission à la mémoire principale (18), caractérisé en ce que les moyens tampons sont adressables par le contenu et an ce que le système comprend de plus :
    des moyens de commande (20) couplés aux processeurs (12,14), à la mémoire principale (18) et aux moyens tampons (27) pour commander lesdites, opérations de lecture et d'écriture,
    les moyens de commande (20) utilisant les moyens tampons pour stocker les données d'un emplacement adressé auquel a accédé le premier processeur pour une opération de lecture-modification-écriture, les moyens de commande (20) aboutissant à une instruction de verrouillage de l'emplacement adressé durant l'opération de lecture-modification-écriture et, en réponse à une opération d'écriture par le second processeur, à l'emplacement adressé durant l'opération de lecture-modification-écriture, les moyens de commande modifiant la séquence normale des opérations d'écriture en mémoire,
    les processeurs multiples pouvant accéder et écrire concurremment au même emplacement adressé de la mémoire principale.
  2. Système de traitement de données suivant la revendication 1 caractérisé en ce que les moyens de commande (20) sont constitués :
    de moyens pour contrôler les moyens tampons adressables par le contenu (22) pour les adresses de données à écrire dans la mémoire principale et pour, au lieu de cela écrire des données dans les moyens tampons adressables par le contenu (22), lorsque l'adresse est trouvée dans les moyens tampons (22).
  3. Système de traitement de données suivant la revendication 1 caractérisé en ce que chacun des mots de données adressables par le contenu des moyens tampons adressables par le contenu (22) sont constitués de plus d'au moins deux blocs de données séparés.
  4. Système de traitement de données suivant la revendication 9 caractérisé en ce que les moyens de commande (22) sont de plus constitués de moyens pour écrire de nouvelles données indépendemment dans l'un des deux blocs de données séparés, et de moyens pour identifier ces données comme de nouvelles données.
  5. Système de traitement de données suivant la revendication 4 caractérisé en ce que les moyens de commande (22) sont de plus constitués de moyens pour préserver les nouvelles données de préférence aux instructions d'écriture ultérieures.
  6. Système de traitement de données suivant l'une quelconque des revendications 3 à 5 caractérisé en ce que les moyens tampon (22) ont une structure de données pour chacune de leurs entrées comprenant :
    i) un bloc adresse pour stocker une adresse qui identifie un emplacement mémoire devant être lu par un premier processeur,
    ii) au moins deux blocs de données séparés associés à chaque bloc d'adresse
    iii) un bloc de verrouillage
    iV) un bloc de validation associé à chacun des blocs de données séparés
    et en ce que les moyens de commande (20) sont conçus:
    a) pour le verrouillage d'une adresse particulière, de façon que les données entrées par un second processeur ne puissent être transmises à la mémoire lorsque le premier processeur lit, modifie, et écrit de nouvelles données
    b) pour stocker et valider de nouvelles données entrées dans un des blocs de données, à partir du second processeur alors que l'adresse d'entrée est verrouillée, et pour préserver les données entrées dans le bloc, de préférence aux données modifiées écrites par le premier processeur,
    c) pour déverrouiller l'adresse particulière, lorsque le premier processeur a terminé sa modification et a écri de nouvelles données à entrer à cette adresse, et
    d) pour transmettre les données déverrouillées à partir des moyens tampons (22) vers les emplacements de la mémoire principale.
  7. Système suivant la revendication 6 caractérisé en ce que les moyens de commande du tampon (22) comportent de plus des moyens pour identifier le processeur qui provoque le verrouillage d'une adresse particulière.
  8. Système suivant la revendication 6 caractérisé en ce que les moyens tampons (22) comprennent de plus un tampon possédant une pluralité d'emplacements d'entrées, qui peuvent être verrouillées par au moins l'un des processeurs.
  9. Méthode pour régler les différentes demandes concurrentes d'accès à l'emplacement d'une mémoire principale, comportant une pluralité de blocs de données, dans un système de traitement de données comprenant au moins un premier processeur et un second processeur et une mémoire tampon avec une pluralité d'emplacements adressés, chacun d'eux possédant une pluralité de blocs de données, caractérisée en ce que la mémoire tampon est adressable par le contenu et en ce que ladite méthode comprend les étapes consistant à :
    A. déterminer le moment ou un premier processeur réalise une opération de lecture-modification-écriture sur des données à partir d'un emplacement de mémoire principale, et à associer un emplacement adressé dans la mémoire tampon à l'emplacement mémoire principal,
    B. verrouiller l'emplacement mémoire tampon.
    C. stocker toute nouvelle donnée produite par un second processeur pour des blocs de données particuliers de l'emplacement de la mémoire principale à l'emplacement mémoire tampon verrouillé
    d. mettre au rebus les données modifiées du premier processeur adressées aux blocs de données particuliers de l'emplacement mémoire tampon verrouillé, dans lequel les blocs des nouvelles données du second processeur on été précédemment stockées.
    E. stocker les données modifiées du premier processeur dans des blocs de données de l'emplacement mémoire tampon verrouillé, lesquels blocs restent non modifiés par les nouvelles données du second processeur, puis déverrouiller l'emplacement mémoire tampon, et
    F. décharger à partir de l'emplacement mémoire tampon les données modifiées et les nouvelles données stockées respectivement par les premier et second processeurs dans l'emplacement mémoire principal.
  10. Méthode suivant la revendication 9 caractérisée en ce que l'étape de verrouillage de l'emplacement mémoire tampon comprend de plus la modification d'une valeur stockée dans un bloc de verrouillage associé à l'emplacement de mémoire tampon.
  11. Méthode suivant la revendication 9, caractérisée en ce que l'étape de stockage de nouvelles données dans le bloc de données, comprend de plus la modification d'une valeur stockée dans un bloc de validation associé au bloc de données de la mémoire tampon.
  12. Méthode suivant la revendication 11, caractérisée en ce que l'étape de mise au rebus de données modifiées comprend de plus l'étape de mise au rebus de données lorsque la valeur stockée dans le bloc de validation a été modifiée.
EP85300858A 1984-02-10 1985-02-08 Méthode et dispositif d'accès à la mémoire dans les systèmes à multi-processeurs Expired - Lifetime EP0168121B1 (fr)

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Application Number Priority Date Filing Date Title
AT85300858T ATE64020T1 (de) 1984-02-10 1985-02-08 Verfahren und vorrichtung zum speicherzugriff in mehrprozessorsystemen.

Applications Claiming Priority (2)

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US06/578,797 US4561051A (en) 1984-02-10 1984-02-10 Memory access method and apparatus in multiple processor systems
US578797 1984-02-10

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EP0168121A1 EP0168121A1 (fr) 1986-01-15
EP0168121B1 true EP0168121B1 (fr) 1991-05-29

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JP (1) JPS60237567A (fr)
AT (1) ATE64020T1 (fr)
CA (1) CA1223973A (fr)
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US4561051A (en) 1985-12-24
DE3582962D1 (de) 1991-07-04
JPS60237567A (ja) 1985-11-26
ATE64020T1 (de) 1991-06-15
CA1223973A (fr) 1987-07-07
EP0168121A1 (fr) 1986-01-15

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