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EP0000480A1 - Method of passivating semiconductor elements by applying a silicon layer - Google Patents

Method of passivating semiconductor elements by applying a silicon layer Download PDF

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Publication number
EP0000480A1
EP0000480A1 EP78100268A EP78100268A EP0000480A1 EP 0000480 A1 EP0000480 A1 EP 0000480A1 EP 78100268 A EP78100268 A EP 78100268A EP 78100268 A EP78100268 A EP 78100268A EP 0000480 A1 EP0000480 A1 EP 0000480A1
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Prior art keywords
silicon
semiconductor elements
layer
semiconductor element
applying
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EP78100268A
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German (de)
French (fr)
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EP0000480B1 (en
Inventor
Jürgen Krausse
Wilhelm Ladenhauf
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Siemens AG
Siemens Corp
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Siemens AG
Siemens Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Definitions

  • a protective layer at least at the points at which the pn junctions occur at the surface, by vapor deposition of silicon 8, for example, 0.1 / can also be thicker, for example, or. / um.
  • the areas of the semiconductor element that are not to be vaporized are covered before vapor deposition.
  • a further protective layer 9 can be applied to the vapor-deposited silicon layer 8, which can consist, for example, of normal rubber or another protective lacquer.
  • the evaporated silicon layer 8 can contain dopants such as boron or phosphorus to adjust the specific resistance. A content of the dopants mentioned is obtained in that one or more of these substances are vaporized with the silicon.
  • the layer 8 can also contain one or more metals such as aluminum to adjust the specific resistance. The metals can also be built into the silicon by vapor deposition. The potential relationships at the edge of the semiconductor element can be adjusted by changing the specific resistance of layer 8.
  • the layer 8 can be doped with phosphorus and have a specific resistance of 10 8 ohm cm.
  • the silicon layer 8 was in a vacuum evaporation system at a pressure of about 6.5. 10-4 PA ( 5.10 -6 Torr) evaporated.
  • a silicon block can be used as the silicon source.
  • the silicon can be evaporated using an electron beam. With an acceleration voltage of 8 kV and a current of around 0.5 A, a vapor deposition rate of 0.25 ⁇ m / min was achieved. It can also be increased, for example, to 0.5 ⁇ m / min and above by increasing the energy of the electron beam.
  • the silicon can also be evaporated by an ion beam, by direct current flow or by inductive heating. It is also possible to evaporate the silicon by radiant heat.
  • the layer 8 can also consist of several successively vapor-deposited layers, each with different properties. A change in the specific resistance via the thickness and an influence on the potential relationships on the edge surface of the semiconductor element are thus obtained.
  • the evaporated silicon layer is annealed.
  • the annealing takes place at a temperature between room temperature and the crystallization temperature of the silicon.
  • the crystallization temperature of the silicon is between 700 and 900 K.
  • the annealing is carried out at a temperature which is below the melting temperature of the material used for contacting, for example soft solder, or another metallization.
  • the reverse current in the reverse direction and the reverse current in the tilting direction of the semiconductor element can be drastically reduced by the annealing.
  • FIG. 2 shows that the reverse current for a certain type of semiconductor without annealing was 2. 10 3 nA.
  • the blocking current for three test specimens was at 280 ° C, the blocking current for three ashamed specimens was between 3 and 5.10 1 nA. After 23 and 41 hours of tempering at 280 ° C, further reductions in the blocking currents were observed.
  • Evaporation of the silicon itself can be carried out at room temperature.
  • the temperature of the subsequent heat treatment can then be selected so that the desired reduction in the blocking currents is achieved without, for example, components which have already been contacted being affected. This makes it possible to passivate chips that have already been soldered and contacted, so that no masking or selective etching of the chips is required.
  • FIG. 3 in which the shape of the space charge zone is shown when the pn junction 7 is stressed in the reverse direction.
  • the boundaries 11, 12 of the space charge zone 10 run parallel to the pn junctions, for example. If there is a blocking load for a long time, the space charge zone widens in that the boundary 12 of the space charge zone 10 at the edge of the semiconductor element shifts in the direction of the pn junction 6. At the same time, the boundary 11 of the space charge zone 10 moves away from the pn junction 7, but only to a much weaker extent, since the zone 4 is more heavily doped than the zone 3.
  • the expansion of the space charge zone is shown in dashed lines in the figure.
  • the reverse current increases until the so-called punch-through effect occurs at the edge when the pn junction 6 is reached, where the pn junction 7 loses its ability to block.
  • the widening also takes place at the pn junction 6 when the semiconductor element is loaded with a voltage in the reverse direction, that is to say the tilting direction.
  • the space charge zone 10 no longer widens at the edge. This can be done, for example, using the known photoelectric method for examining the space charge zones Determine the edge of a semiconductor element. This tet that the reverse currents do not increase, in other words that the characteristics remain stable in the reverse direction.
  • the invention has been described in connection with a semiconductor element for a thyristor. However, it can also be used in diodes, transistors and other semiconductor components. It can be used equally for mesa or planar structures. It is essential that silicon is evaporated onto at least the region in which the pn junctions occur on the surface of the semiconductor element.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Die Erfindung bezieht sich auf ein Verfahren zum Passivieren der Oberflächen von Halbleiterelementen. Auf die Oberfläche von Halbleiterelementen aufgedampfte Siliciumschichten (8) stabilisieren die Kennlinien der Halbleiterelemente dauerhaft. Zur Absenkung der Sperrströme werden diese Siliciumschichten getempert. Dadurch wurde eine dauerhafte Absenkung des Sperrströmniveaus erreicht. Die Erfindung kann bei allen Halbleiterbauelementen angewendet werden.The invention relates to a method for passivating the surfaces of semiconductor elements. Silicon layers (8) vapor-deposited on the surface of semiconductor elements permanently stabilize the characteristics of the semiconductor elements. These silicon layers are annealed to reduce the reverse currents. This resulted in a permanent reduction in the blocking current level. The invention can be applied to all semiconductor components.

Description

Figure imgb0001
Figure imgb0001

Figure imgb0002
auf das Halbleiterelement aufgebrachten Metallisierung liegen, zu tempern. Besonders günstige Ergebnisse lassen sich erzielen, wenn in sauerstoffhaltiger Atmosphäre getempert wird.
Figure imgb0002
metallization applied to the semiconductor element, to anneal. Particularly favorable results can be achieved if tempering is carried out in an oxygen-containing atmosphere.

Die Erfindung wird an Hand eines Ausführungsbeispiels in Verbindung mit den Fig. 1 und 3 und an Hand eines Diagramms (Fig. 2) näher erläutert:

  • In Fig. 1 ist das Halbleiterelement eines Thyristors im Schnitt dargestellt. Es hat vier Zonen, von denen die kathodenseitige Emitterzone mit 1, die kathodenseitige Basiszone mit 2, die innere Basiszone mit 3 und die anodenseitige Emitterzone mit 4 bezeichnet ist. Zwischen den genannten Zonen liegen pn-Übergänge 5, 6, 7. Das Halbleiterelement besteht aus Silicium und die genannten Zonen sind in üblicher Weise je nach Verwendungszweck des Halbleiterbauelements dotiert.
The invention is explained in more detail using an exemplary embodiment in conjunction with FIGS. 1 and 3 and using a diagram (FIG. 2):
  • In Fig. 1, the semiconductor element of a thyristor is shown in section. It has four zones, of which the cathode-side emitter zone is denoted by 1, the cathode-side base zone by 2, the inner base zone by 3 and the anode-side emitter zone by 4. There are pn junctions 5, 6, 7 between the zones mentioned. The semiconductor element consists of silicon and the zones mentioned are doped in a conventional manner depending on the intended use of the semiconductor component.

Auf den Rand des Halbleiterelements wird wenigstens an den Stellen, an denen die pn-Übergänge an die Oberfläche treten, eine Schutzschicht 8 aus Silicium aufgedampft, die beispielsweise 0,1 /um oder auch dicker sein kann, beispielsweise. /um. Die nicht zu bedampfenden Flächen.des Halbleiterelements werden vor dem Bedampfen abgedeckt. Zur Erhöhung der dielektrischen Überschlagsfastigkeit und zur Verbesserung des mechanischen Schutzes kann auf die aufgedampfte Siliciumschicht 8 eine weitere Schutzschicht 9 aufgebracht werden, die beispielsweise aus normalem Kautschuk oder einem anderen Schutzlack bestehen kann.On the edge of the semiconductor element, a protective layer at least at the points at which the pn junctions occur at the surface, by vapor deposition of silicon 8, for example, 0.1 / can also be thicker, for example, or. / um. The areas of the semiconductor element that are not to be vaporized are covered before vapor deposition. To increase the dielectric flashover resistance and to improve the mechanical protection, a further protective layer 9 can be applied to the vapor-deposited silicon layer 8, which can consist, for example, of normal rubber or another protective lacquer.

Die aufgedampfte Siliciumschicht 8 kann zur Einstellung des spezifischen Widerstands Dotierstoffe wie zum Beispiel Bor oder Phosphor enthalten. Einen Gehalt an den genannten Dotierstoffen erhält man dadurch, daß mit dem Silicium einer oder mehrere dieser Stoffe verdampft werden. Die Schicht 8 kann zur Einstellung des spezifischen Widerstands auch ein oder mehrere Metalle wie zum Beispiel-Aluminium enthalten. Die Metalle können ebenfalls durch Aufdampfen mit dem Silicium in dieses eingebaut werden. Mit Änderung des spezifischen Widerstands der Schicht 8 lassen sich die Potentialverhältnisse am Rand des Halbleiterelements einstellen. So kann die Schicht 8 beispielsweise mit Phosphor dotiert sein und einen spezifischen Widerstand von 108 Ohm cm haben.The evaporated silicon layer 8 can contain dopants such as boron or phosphorus to adjust the specific resistance. A content of the dopants mentioned is obtained in that one or more of these substances are vaporized with the silicon. The layer 8 can also contain one or more metals such as aluminum to adjust the specific resistance. The metals can also be built into the silicon by vapor deposition. The potential relationships at the edge of the semiconductor element can be adjusted by changing the specific resistance of layer 8. For example, the layer 8 can be doped with phosphorus and have a specific resistance of 10 8 ohm cm.

Die Siliciumschicht 8 wurde in einer Vakuum-Bedampfungsanlage bei einem Druck von ca. 6,5 . 10-4 PA (5 . 10-6 Torr) aufgedampft. Als Siliciumquelle kann beispielsweise ein Siliciumblock verwendet werden. Das Silicium kann mittels eines Elektronenstrahls verdampft werden. Mit einer Beschleunigungsspannung von 8 kV und einem Strom von rund 0,5 A wurde eine Aufdampfrate von 0,25 µm/min erzielt. Sie läßt sich durch Erhöhung der Energie des Elektronenstrahls auch beispielsweise auf 0,5 µm/min und darüber steigern.The silicon layer 8 was in a vacuum evaporation system at a pressure of about 6.5. 10-4 PA ( 5.10 -6 Torr) evaporated. For example, a silicon block can be used as the silicon source. The silicon can be evaporated using an electron beam. With an acceleration voltage of 8 kV and a current of around 0.5 A, a vapor deposition rate of 0.25 µm / min was achieved. It can also be increased, for example, to 0.5 μm / min and above by increasing the energy of the electron beam.

Das Silicium kann auch durch einen Ionenstrahl, durch direkten Stromdurchfluß oder durch induktive Erhitzung verdampft werden. Es ist auch möglich, das Silicium durch Strahlungswärme zu verdampfen.The silicon can also be evaporated by an ion beam, by direct current flow or by inductive heating. It is also possible to evaporate the silicon by radiant heat.

Die Schicht 8 kann auch aus mehreren nacheinander aufgedampften Schichten mit jeweils verschiedenen Eigenschaften bestehen. Damit erhält man eine Änderung des spezifischen Widerstands über die Dicke und eine Beeinflussung der Potentialverhältnisse an der Randfläche des Halbleiterelements.The layer 8 can also consist of several successively vapor-deposited layers, each with different properties. A change in the specific resistance via the thickness and an influence on the potential relationships on the edge surface of the semiconductor element are thus obtained.

Anschließend an das Bedampfen des Halbleiterelements wird die aufgedampfte Siliciumschicht getempert. Das Tempern findet bei einer Temperatur zwischen Zimmertemperatur und der Kristallisationstemperatur des Siliciums statt. Die Kristallisationstemperatur des Siliciums liegt nach Literaturangaben zwischen 700 und 900 K. Bei bereits kontaktierten Halbleiterelementen wird das Tempern bei einer Temperatur vorgenommen, die unterhalb der Schmelztemperatur des zum Kontaktieren verwendeten Materials, zum Beispiel Weichlot, oder einer anderen Metallisierung liegt. Durch das Tempern lassen sich der Sperrstrom in Sperrichtung und der Sperrstrom in Kipprichtung des Halbleiterelements drastisch absenken. In Fig. 2 ist dargestellt, daß der Sperrstrom bei einem bestimmten Halbleitertyp ohne das Tempern bei 2. 103 nA lag. Nach einer Temperzeit von drei Stunden bei 260 °C lag der Sperrstrom für drei Meßexemplare bei 280 °C lag der Sperrstrom für drei Haßexemplare zwischen 3 und 5.101 nA. Nach 23 und 41 Stunden Temperzeit bei 280 °C wurden weitere Absenkungen der Sperrströme beobachtet.Subsequent to the vapor deposition of the semiconductor element, the evaporated silicon layer is annealed. The annealing takes place at a temperature between room temperature and the crystallization temperature of the silicon. According to the literature, the crystallization temperature of the silicon is between 700 and 900 K. In the case of semiconductor elements which have already been contacted, the annealing is carried out at a temperature which is below the melting temperature of the material used for contacting, for example soft solder, or another metallization. The reverse current in the reverse direction and the reverse current in the tilting direction of the semiconductor element can be drastically reduced by the annealing. FIG. 2 shows that the reverse current for a certain type of semiconductor without annealing was 2. 10 3 nA. After an annealing time of three hours at 260 ° C, the blocking current for three test specimens was at 280 ° C, the blocking current for three hatred specimens was between 3 and 5.10 1 nA. After 23 and 41 hours of tempering at 280 ° C, further reductions in the blocking currents were observed.

Das Aufdampfen das Siliciums selbst kann bei Zimmertemperatur durchgeführt werden. Die Temperatur der anschließenden Wärmebehandlung kann dann so gewählt werden, daß die gewünschte Absenkung der Sperrströme erreicht wird, ohne daß zum Beispiel bereits kontaktierte Bauelemente in Mitleidenschaft gezogen werden. Damit ist es möglich, bereits aufgelötete und kontaktierte Chips zu passivieren, so daß keine Maskierung oder kein selektives Ätzen der Chips erforderlich ist.Evaporation of the silicon itself can be carried out at room temperature. The temperature of the subsequent heat treatment can then be selected so that the desired reduction in the blocking currents is achieved without, for example, components which have already been contacted being affected. This makes it possible to passivate chips that have already been soldered and contacted, so that no masking or selective etching of the chips is required.

Halbleiterelemente, die durch Aufdampfen einer Siliciumschicht und nachfolgendes Tempern passiviert wurden, wiesen eine überraschend gute Stabilität der Kennlinien bei niedrigem Stromniveau auf. Dies galt sowohl für die Sperrkennlinien in Rückwärtsrichtung bei Dioden und Transistoren als auch für die Sperrkennlinien in Rückwärtsrichtung und Kipprichtung bei Thyristoren. Bei Thyristoren trat auch der sogenannte Yoshida-Effekt nicht mehr auf, der eine drastische Erhöhung der Sperrströme nach vorhergehender Durchlaßbelastung bewirkt.Semiconductor elements, which were passivated by vapor deposition of a silicon layer and subsequent annealing, showed a surprisingly good stability of the characteristics at a low current level. This was true both for the blocking characteristics in the reverse direction for diodes and transistors as well as for the blocking characteristics in the reverse direction and tilting direction for thyristors. The so-called Yoshida effect no longer occurred in thyristors, which causes a drastic increase in the reverse currents after the forward load.

Die Stabilität der Kennlinien läßt sich anschaulich an Hand der Fig. 3 erklären, in der die Gestalt der Raumladungszone dargestellt ist, wenn der pn-Übergang 7 in Sperrichtung beansprucht ist. Zu Anfang der Sperrbelastung verlaufen die Grenzen 11, 12 der Raumladungszone 10 zum Beispiel parallel zu den pn-Übergängen. Liegt längere Zeit Sperrbelastung an, so weitet sich die Raumladungszone dadurch auf, daß sich die Grenze 12 der Raumladungszone 10 am Rand des Halbleiterelements in Richtung auf den pn-Übergang 6 verschiebt. Gleichzeitig entfernt sich die Grenze 11 der Raumladungszone 10 vom pn-Übergang 7, jedoch nur in erheblich schwächerem Maße, da die Zone 4 stärker als die Zone 3 dotiert ist. Die Aufweitung der Raumladungszone ist in der Fig. gestrichelt dargestellt. Mit größer werdender Aufweitung der Raumladungszone nimmt der Sperrstrom zu, bis mit Erreichen des pn-Ubergangs 6 am Rand der sogenannte Punch-Through-Effekt eintritt, wo der pn-Übergang 7 seine Sperrfähigkeit verliert. Die Aufweitung findet auch am pn-Übergang 6 statt, wenn das Halbleiterelement in der umgekehrten Richtung, das heißt der Kipprichtung, mit einer Spannung belastet wird.The stability of the characteristic curves can be clearly explained with reference to FIG. 3, in which the shape of the space charge zone is shown when the pn junction 7 is stressed in the reverse direction. At the beginning of the blocking load, the boundaries 11, 12 of the space charge zone 10 run parallel to the pn junctions, for example. If there is a blocking load for a long time, the space charge zone widens in that the boundary 12 of the space charge zone 10 at the edge of the semiconductor element shifts in the direction of the pn junction 6. At the same time, the boundary 11 of the space charge zone 10 moves away from the pn junction 7, but only to a much weaker extent, since the zone 4 is more heavily doped than the zone 3. The expansion of the space charge zone is shown in dashed lines in the figure. As the space charge zone widens, the reverse current increases until the so-called punch-through effect occurs at the edge when the pn junction 6 is reached, where the pn junction 7 loses its ability to block. The widening also takes place at the pn junction 6 when the semiconductor element is loaded with a voltage in the reverse direction, that is to say the tilting direction.

Mit der Passivierungsschicht-gemäß der Erfindung weitet sich die Raumladungszone 10 am Rand nicht mehr auf. Dies läßt sich beispielsweise mit der bekannten lichtelektrischen Methode zur Untersuchung der Raumladungszonen am Rand eines Halbleiterelements feststellen. Dies

Figure imgb0003
tet, daß sich die Sperrströme nicht erhöhen, mit andsren Worten, daß die Kennlinien in Sperrichtung stabil bleiben.With the passivation layer according to the invention, the space charge zone 10 no longer widens at the edge. This can be done, for example, using the known photoelectric method for examining the space charge zones Determine the edge of a semiconductor element. This
Figure imgb0003
tet that the reverse currents do not increase, in other words that the characteristics remain stable in the reverse direction.

Die Erfindung wurde in Verbindung mit einem Halbleiterelement für einen Thyristor beschrieben. Sie läßt sich jedoch auch bei Dioden, Transistoren und anderen Halbleiterbauelementen verwenden. Sie ist gleichermaßen für Mesa- oder Planarstrukturen verwendbar. Wesentlich ist, daß auf mindestens denjenigen Bereich, in dem die pn-Übergänge an die Oberfläche des Halbleiterelements treten, Silicium aufgedampft wird.The invention has been described in connection with a semiconductor element for a thyristor. However, it can also be used in diodes, transistors and other semiconductor components. It can be used equally for mesa or planar structures. It is essential that silicon is evaporated onto at least the region in which the pn junctions occur on the surface of the semiconductor element.

Claims (4)

1. Verfahren zum Passivieren von Halbleiterelementen durch Aufbringen einer Siliciumschicht, dadurch gekennzeichnet, daß das Siliciumaufgedampft wird und dann die aufgedampfte Schicht (8) getem-. pert wird.1. A method for passivating semiconductor elements by applying a silicon layer, characterized in that the silicon is evaporated and then the evaporated layer (8) getem-. pert is. 2. Verfahren nach Anspruch 1, dadurch g e - kennzeichnet, daß die Schicht(8)bei Temperaturen zwischen der Raumtemperatur und der Kristallisationstemperatur des aufgedampften Siliciums getempert wird.2. The method according to claim 1, characterized g e - indicates that the layer (8) is annealed at temperatures between room temperature and the crystallization temperature of the vapor-deposited silicon. 3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Schicht(8) bei Temperaturen getempert wird, die unterhalb der Schmelztemperatur einer auf das Halbleiterelement aufgebrachten Metallisierung liegen.3. The method according to claim 1 or 2, characterized in that the layer (8) is annealed at temperatures which are below the melting temperature of a metallization applied to the semiconductor element. 4. Verfahren nach einem der Ansprüche 1 bis 3, da- durch gekennzeichnet, daß in sauerstoffhaltiger Atmosphäre getempert wird.4. The method according to any one of claims 1 to 3, characterized in that annealing is carried out in an oxygen-containing atmosphere.
EP78100268A 1977-07-05 1978-06-28 Method of passivating semiconductor elements by applying a silicon layer Expired EP0000480B1 (en)

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DE19772730367 DE2730367A1 (en) 1977-07-05 1977-07-05 PROCESS FOR PASSIVATING SEMICONDUCTOR ELEMENTS
DE2730367 1977-07-05

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US4561171A (en) * 1982-04-06 1985-12-31 Shell Austria Aktiengesellschaft Process of gettering semiconductor devices
AT384121B (en) * 1983-03-28 1987-10-12 Shell Austria Method for gettering of semiconductor components
EP0543257A3 (en) * 1991-11-13 1994-07-13 Siemens Ag Method of manufacturing a power-misfet

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US5213670A (en) * 1989-06-30 1993-05-25 Siemens Aktiengesellschaft Method for manufacturing a polycrystalline layer on a substrate
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Also Published As

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CA1111149A (en) 1981-10-20
EP0000480B1 (en) 1981-08-12
DE2730367A1 (en) 1979-01-18
DE2730367C2 (en) 1988-01-14
IT1096857B (en) 1985-08-26
GB1587030A (en) 1981-03-25
US4322452A (en) 1982-03-30
IT7825181A0 (en) 1978-06-30
JPS6158976B2 (en) 1986-12-13
JPS5417672A (en) 1979-02-09

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