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DK0657044T3 - Method of operating a computer system with at least one microprocessor and at least one coprocessor - Google Patents

Method of operating a computer system with at least one microprocessor and at least one coprocessor

Info

Publication number
DK0657044T3
DK0657044T3 DK93917544.4T DK93917544T DK0657044T3 DK 0657044 T3 DK0657044 T3 DK 0657044T3 DK 93917544 T DK93917544 T DK 93917544T DK 0657044 T3 DK0657044 T3 DK 0657044T3
Authority
DK
Denmark
Prior art keywords
coprocessor
microprocessor
operating
computer system
computer
Prior art date
Application number
DK93917544.4T
Other languages
Danish (da)
Inventor
Klaus Buchenrieder
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of DK0657044T3 publication Critical patent/DK0657044T3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
DK93917544.4T 1992-08-28 1993-08-11 Method of operating a computer system with at least one microprocessor and at least one coprocessor DK0657044T3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4228761 1992-08-28

Publications (1)

Publication Number Publication Date
DK0657044T3 true DK0657044T3 (en) 1996-03-25

Family

ID=6466703

Family Applications (1)

Application Number Title Priority Date Filing Date
DK93917544.4T DK0657044T3 (en) 1992-08-28 1993-08-11 Method of operating a computer system with at least one microprocessor and at least one coprocessor

Country Status (5)

Country Link
EP (1) EP0657044B1 (en)
DE (1) DE59301609D1 (en)
DK (1) DK0657044T3 (en)
ES (1) ES2083296T3 (en)
WO (1) WO1994006077A1 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
WO2002029600A2 (en) 2000-10-06 2002-04-11 Pact Informationstechnologie Gmbh Cell system with segmented intermediate cell structure
DE19647181A1 (en) * 1996-11-14 1998-05-20 Siemens Ag Integrated circuit designed for processing software programs
DE19651075A1 (en) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like
DE19651527A1 (en) * 1996-12-11 1998-06-25 Siemens Ag Computer arrangement and method for carrying out a sequence of program instructions
DE19704728A1 (en) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Method for self-synchronization of configurable elements of a programmable module
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US6438737B1 (en) * 2000-02-15 2002-08-20 Intel Corporation Reconfigurable logic for a computer
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
WO2003025770A2 (en) * 2001-09-07 2003-03-27 Pact Xpp Technologies Ag Reconfigurable system
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
GB0215034D0 (en) * 2002-06-28 2002-08-07 Critical Blue Ltd Architecture generation method
GB0215033D0 (en) 2002-06-28 2002-08-07 Critical Blue Ltd Instruction set translation method
AU2003286131A1 (en) * 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
EP1537486A1 (en) 2002-09-06 2005-06-08 PACT XPP Technologies AG Reconfigurable sequencer structure
KR20050085545A (en) * 2002-12-12 2005-08-29 코닌클리즈케 필립스 일렉트로닉스 엔.브이. Modular integration of an array processor within a system on chip

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4694416A (en) * 1985-02-25 1987-09-15 General Electric Company VLSI programmable digital signal processor
US4829380A (en) * 1987-12-09 1989-05-09 General Motors Corporation Video processor
US5301344A (en) * 1991-01-29 1994-04-05 Analogic Corporation Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets

Also Published As

Publication number Publication date
WO1994006077A1 (en) 1994-03-17
EP0657044A1 (en) 1995-06-14
ES2083296T3 (en) 1996-04-01
DE59301609D1 (en) 1996-03-21
EP0657044B1 (en) 1996-02-07

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