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DE69926084D1 - Taktphasenregelsystem, integrierte schaltung und entwurfsverfahren dafür - Google Patents

Taktphasenregelsystem, integrierte schaltung und entwurfsverfahren dafür

Info

Publication number
DE69926084D1
DE69926084D1 DE69926084T DE69926084T DE69926084D1 DE 69926084 D1 DE69926084 D1 DE 69926084D1 DE 69926084 T DE69926084 T DE 69926084T DE 69926084 T DE69926084 T DE 69926084T DE 69926084 D1 DE69926084 D1 DE 69926084D1
Authority
DE
Germany
Prior art keywords
control system
integrated circuit
clock control
design process
process therefor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69926084T
Other languages
English (en)
Other versions
DE69926084T2 (de
Inventor
Masayoshi Tojima
Hiromasa Nakajima
Masahiro Oohashi
Yasuo Kohashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69926084D1 publication Critical patent/DE69926084D1/de
Application granted granted Critical
Publication of DE69926084T2 publication Critical patent/DE69926084T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Dram (AREA)
  • Record Information Processing For Printing (AREA)
  • Pulse Circuits (AREA)
DE69926084T 1998-12-15 1999-12-15 Taktphasenregelsystem, integrierte schaltung und entwurfsverfahren dafür Expired - Fee Related DE69926084T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP35655098 1998-12-15
JP35655098 1998-12-15
PCT/JP1999/007043 WO2000036512A1 (en) 1998-12-15 1999-12-15 Clock phase adjustment method, and integrated circuit and design method therefor

Publications (2)

Publication Number Publication Date
DE69926084D1 true DE69926084D1 (de) 2005-08-11
DE69926084T2 DE69926084T2 (de) 2006-05-04

Family

ID=18449594

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69926084T Expired - Fee Related DE69926084T2 (de) 1998-12-15 1999-12-15 Taktphasenregelsystem, integrierte schaltung und entwurfsverfahren dafür

Country Status (7)

Country Link
US (2) US6556505B1 (de)
EP (1) EP1156420B1 (de)
JP (1) JP3542967B2 (de)
KR (1) KR100431384B1 (de)
DE (1) DE69926084T2 (de)
TW (1) TW461073B (de)
WO (1) WO2000036512A1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023833B1 (en) 1999-09-10 2006-04-04 Pulse-Link, Inc. Baseband wireless network for isochronous communication
US7088795B1 (en) 1999-11-03 2006-08-08 Pulse-Link, Inc. Ultra wide band base band receiver
CN100462433C (zh) 2000-07-07 2009-02-18 维西根生物技术公司 实时序列测定
US7035246B2 (en) * 2001-03-13 2006-04-25 Pulse-Link, Inc. Maintaining a global time reference among a group of networked devices
US20020178427A1 (en) * 2001-05-25 2002-11-28 Cheng-Liang Ding Method for improving timing behavior in a hardware logic emulation system
JP2003068077A (ja) * 2001-08-28 2003-03-07 Mitsubishi Electric Corp 半導体記憶装置
US7177288B2 (en) * 2001-11-28 2007-02-13 Intel Corporation Simultaneous transmission and reception of signals in different frequency bands over a bus line
US6845424B2 (en) * 2002-01-31 2005-01-18 Intel Corporation Memory pass-band signaling
US7198197B2 (en) * 2002-11-05 2007-04-03 Rambus, Inc. Method and apparatus for data acquisition
KR100468776B1 (ko) * 2002-12-10 2005-01-29 삼성전자주식회사 클락 지터의 영향을 감소시킬 수 있는 동기식 반도체메모리장치
KR100592188B1 (ko) * 2003-10-20 2006-06-23 (주)씨앤에스 테크놀로지 에스디램 엑세스를 위한 데이터 인터페이스장치
JP4502644B2 (ja) * 2004-01-07 2010-07-14 株式会社リコー メモリ制御装置
JP4757583B2 (ja) 2005-09-20 2011-08-24 エルピーダメモリ株式会社 出力制御信号発生回路
US7266021B1 (en) * 2005-09-27 2007-09-04 Lsi Corporation Latch-based random access memory (LBRAM) tri-state banking architecture
JP4425243B2 (ja) * 2005-10-17 2010-03-03 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
WO2008076790A2 (en) 2006-12-14 2008-06-26 Rambus Inc. Multi-die memory device
US7864623B2 (en) * 2008-05-22 2011-01-04 Elpida Memory, Inc. Semiconductor device having latency counter
KR100949272B1 (ko) * 2008-07-10 2010-03-25 주식회사 하이닉스반도체 반도체 소자와 그의 구동 방법
WO2010080176A1 (en) 2009-01-12 2010-07-15 Rambus Inc. Mesochronous signaling system with multiple power modes
JP5427564B2 (ja) * 2009-11-20 2014-02-26 パナソニック株式会社 メモリインターフェース回路、及びメモリデバイスのドライブ能力調整方法
JP6342065B2 (ja) * 2015-04-08 2018-06-13 三菱電機株式会社 回路設計支援装置及び回路設計支援方法及び回路設計支援プログラム
US10241538B2 (en) * 2017-02-22 2019-03-26 Integrated Device Technology, Inc. Resynchronization of a clock associated with each data bit in a double data rate memory system
JP6784626B2 (ja) * 2017-03-24 2020-11-11 キヤノン株式会社 記録装置、制御方法、及びプログラム
JP6784631B2 (ja) * 2017-03-30 2020-11-11 キヤノン株式会社 記録再生装置、記録再生装置の制御方法、及び、プログラム

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258660A (en) 1990-01-16 1993-11-02 Cray Research, Inc. Skew-compensated clock distribution system
JP2956228B2 (ja) * 1991-01-16 1999-10-04 富士通株式会社 デジタル回路のタイミングチェック方式
US5571236A (en) * 1992-08-28 1996-11-05 Sumitomo Electric Industries, Ltd. Diamond wire drawing die
JP3458406B2 (ja) * 1993-04-02 2003-10-20 松下電器産業株式会社 インターフェース回路
JP3256597B2 (ja) * 1993-06-21 2002-02-12 株式会社東芝 自動配置設計方法および自動配置設計装置
JPH0773118A (ja) * 1993-09-02 1995-03-17 Toshiba Corp 遅延時間補償装置
JPH07248847A (ja) 1994-03-11 1995-09-26 Fujitsu Ltd クロック信号調整方法および装置
JPH08123717A (ja) 1994-10-25 1996-05-17 Oki Electric Ind Co Ltd 半導体記憶装置
US5577236A (en) * 1994-12-30 1996-11-19 International Business Machines Corporation Memory controller for reading data from synchronous RAM
JPH08221315A (ja) * 1995-02-15 1996-08-30 Hitachi Ltd 情報処理装置
JP2853985B2 (ja) * 1995-12-28 1999-02-03 株式会社グラフィックス・コミュニケーション・ラボラトリーズ クロック位相調整回路およびクロック位相調整方法
US5946712A (en) * 1997-06-04 1999-08-31 Oak Technology, Inc. Apparatus and method for reading data from synchronous memory
US5917761A (en) * 1997-11-06 1999-06-29 Motorola Inc. Synchronous memory interface
JP4079507B2 (ja) * 1998-05-12 2008-04-23 富士通株式会社 メモリ制御システムおよびメモリ制御方法
JP2000067577A (ja) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000311028A (ja) * 1999-04-28 2000-11-07 Hitachi Ltd 位相制御回路、半導体装置及び半導体メモリ

Also Published As

Publication number Publication date
EP1156420B1 (de) 2005-07-06
EP1156420A4 (de) 2004-03-17
KR20020008109A (ko) 2002-01-29
EP1156420A1 (de) 2001-11-21
DE69926084T2 (de) 2006-05-04
KR100431384B1 (ko) 2004-05-14
US6853589B2 (en) 2005-02-08
WO2000036512B1 (en) 2000-10-05
WO2000036512A1 (en) 2000-06-22
TW461073B (en) 2001-10-21
US20030179625A1 (en) 2003-09-25
US6556505B1 (en) 2003-04-29
JP3542967B2 (ja) 2004-07-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee