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DE3673775D1 - Verfahren zur bildung von kontakten und gegenseitigen verbindungen fuer integrierte schaltungen. - Google Patents

Verfahren zur bildung von kontakten und gegenseitigen verbindungen fuer integrierte schaltungen.

Info

Publication number
DE3673775D1
DE3673775D1 DE8686903952T DE3673775T DE3673775D1 DE 3673775 D1 DE3673775 D1 DE 3673775D1 DE 8686903952 T DE8686903952 T DE 8686903952T DE 3673775 T DE3673775 T DE 3673775T DE 3673775 D1 DE3673775 D1 DE 3673775D1
Authority
DE
Germany
Prior art keywords
integrated circuits
forming contacts
mutual connections
mutual
connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686903952T
Other languages
English (en)
Inventor
Adam Metz
John Szluk
Wilburn Miller
Joseph Drury
Andrew Sullivan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Application granted granted Critical
Publication of DE3673775D1 publication Critical patent/DE3673775D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8686903952T 1985-06-12 1986-06-02 Verfahren zur bildung von kontakten und gegenseitigen verbindungen fuer integrierte schaltungen. Expired - Lifetime DE3673775D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/743,849 US4648175A (en) 1985-06-12 1985-06-12 Use of selectively deposited tungsten for contact formation and shunting metallization
PCT/US1986/001202 WO1986007491A1 (en) 1985-06-12 1986-06-02 Process for forming contacts and interconnects for integrated circuits

Publications (1)

Publication Number Publication Date
DE3673775D1 true DE3673775D1 (de) 1990-10-04

Family

ID=24990441

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686903952T Expired - Lifetime DE3673775D1 (de) 1985-06-12 1986-06-02 Verfahren zur bildung von kontakten und gegenseitigen verbindungen fuer integrierte schaltungen.

Country Status (5)

Country Link
US (1) US4648175A (de)
EP (1) EP0225920B1 (de)
JP (1) JPH088224B2 (de)
DE (1) DE3673775D1 (de)
WO (1) WO1986007491A1 (de)

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DE3683679D1 (de) * 1985-04-26 1992-03-12 Fujitsu Ltd Verfahren zur herstellung einer kontaktanordnung fuer eine halbleiteranordnung.
US4701423A (en) * 1985-12-20 1987-10-20 Ncr Corporation Totally self-aligned CMOS process
US4796081A (en) * 1986-05-02 1989-01-03 Advanced Micro Devices, Inc. Low resistance metal contact for silicon devices
JPH0622245B2 (ja) * 1986-05-02 1994-03-23 富士ゼロックス株式会社 薄膜トランジスタの製造方法
US4740483A (en) * 1987-03-02 1988-04-26 Motorola, Inc. Selective LPCVD tungsten deposition by nitridation of a dielectric
US4755478A (en) * 1987-08-13 1988-07-05 International Business Machines Corporation Method of forming metal-strapped polysilicon gate electrode for FET device
US4822749A (en) * 1987-08-27 1989-04-18 North American Philips Corporation, Signetics Division Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
US4937657A (en) * 1987-08-27 1990-06-26 Signetics Corporation Self-aligned metallization for semiconductor device and process using selectively deposited tungsten
JPH01256125A (ja) * 1988-04-05 1989-10-12 Hitachi Ltd 半導体集積回路装置の製造方法
US4897150A (en) * 1988-06-29 1990-01-30 Lasa Industries, Inc. Method of direct write desposition of a conductor on a semiconductor
US4944682A (en) * 1988-10-07 1990-07-31 International Business Machines Corporation Method of forming borderless contacts
US4920403A (en) * 1989-04-17 1990-04-24 Hughes Aircraft Company Selective tungsten interconnection for yield enhancement
US4874713A (en) * 1989-05-01 1989-10-17 Ncr Corporation Method of making asymmetrically optimized CMOS field effect transistors
US5021363A (en) * 1989-09-07 1991-06-04 Laboratories Incorporated Method of selectively producing conductive members on a semiconductor surface
YU247189A (en) * 1989-12-27 1991-10-31 Biro Rijeka Ing Silicon heating element
JP2892421B2 (ja) * 1990-02-27 1999-05-17 沖電気工業株式会社 半導体素子の製造方法
US5107321A (en) * 1990-04-02 1992-04-21 National Semiconductor Corporation Interconnect method for semiconductor devices
US5231042A (en) * 1990-04-02 1993-07-27 National Semiconductor Corporation Formation of silicide contacts using a sidewall oxide process
US5219784A (en) * 1990-04-02 1993-06-15 National Semiconductor Corporation Spacer formation in a bicmos device
US5223456A (en) * 1990-05-02 1993-06-29 Quality Semiconductor Inc. High density local interconnect in an integrated circit using metal silicide
US5254874A (en) * 1990-05-02 1993-10-19 Quality Semiconductor Inc. High density local interconnect in a semiconductor circuit using metal silicide
US5118639A (en) * 1990-05-29 1992-06-02 Motorola, Inc. Process for the formation of elevated source and drain structures in a semiconductor device
JP2895166B2 (ja) * 1990-05-31 1999-05-24 キヤノン株式会社 半導体装置の製造方法
EP0463373A3 (en) * 1990-06-29 1992-03-25 Texas Instruments Incorporated Local interconnect using a material comprising tungsten
KR100209856B1 (ko) * 1990-08-31 1999-07-15 가나이 쓰도무 반도체장치의 제조방법
JP2675713B2 (ja) * 1991-05-10 1997-11-12 株式会社東芝 半導体装置及びその製造方法
US5242851A (en) * 1991-07-16 1993-09-07 Samsung Semiconductor, Inc. Programmable interconnect device and method of manufacturing same
US5185294A (en) * 1991-11-22 1993-02-09 International Business Machines Corporation Boron out-diffused surface strap process
DE4309898B4 (de) * 1992-03-30 2005-11-03 Rohm Co. Ltd. Verfahren zur Herstellung eines Bipolartransistors mit einer Polysiliziumschicht zwischen einem Halbleiterbereich und einem Oberflächenelektrodenmetall
FI101911B1 (fi) * 1993-04-07 1998-09-15 Valtion Teknillinen Sähköisesti moduloitava terminen säteilylähde ja menetelmä sen valmistamiseksi
KR970007819B1 (en) * 1993-10-21 1997-05-17 Hyundai Electronics Ind Contact forming method of semiconductor device
JP2978736B2 (ja) * 1994-06-21 1999-11-15 日本電気株式会社 半導体装置の製造方法
JP2720827B2 (ja) * 1994-07-05 1998-03-04 日本電気株式会社 半導体装置の製造方法
DE4424420A1 (de) * 1994-07-12 1996-01-18 Telefunken Microelectron Kontaktierungsprozeß
US5510296A (en) * 1995-04-27 1996-04-23 Vanguard International Semiconductor Corporation Manufacturable process for tungsten polycide contacts using amorphous silicon
US5721146A (en) * 1996-04-29 1998-02-24 Taiwan Semiconductor Manufacturing Company Ltd Method of forming buried contact architecture within a trench
US6136616A (en) * 1998-02-11 2000-10-24 Advanced Micro Devices Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength
US6329219B1 (en) * 1999-12-22 2001-12-11 Scientific Imaging Technologies, Inc. Method of processing a semiconductor device
US6509282B1 (en) * 2001-11-26 2003-01-21 Advanced Micro Devices, Inc. Silicon-starved PECVD method for metal gate electrode dielectric spacer
US7812441B2 (en) 2004-10-21 2010-10-12 Siliconix Technology C.V. Schottky diode with improved surge capability
TWI278090B (en) 2004-10-21 2007-04-01 Int Rectifier Corp Solderable top metal for SiC device
US7834376B2 (en) 2005-03-04 2010-11-16 Siliconix Technology C. V. Power semiconductor switch
US9419092B2 (en) * 2005-03-04 2016-08-16 Vishay-Siliconix Termination for SiC trench devices
US8368165B2 (en) 2005-10-20 2013-02-05 Siliconix Technology C. V. Silicon carbide Schottky diode
EP2047514A4 (de) * 2006-07-31 2010-12-01 Vishay Siliconix MOLYBDÄNSPERRMETALL FÜR SiC-SCHOTTKYDIODE UND HERSTELLUNGSVERFAHREN
US8614106B2 (en) 2011-11-18 2013-12-24 International Business Machines Corporation Liner-free tungsten contact
US10490558B2 (en) * 2017-05-31 2019-11-26 Qualcomm Incorporated Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells

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US3632436A (en) * 1969-07-11 1972-01-04 Rca Corp Contact system for semiconductor devices
US3699646A (en) * 1970-12-28 1972-10-24 Intel Corp Integrated circuit structure and method for making integrated circuit structure
US4106051A (en) * 1972-11-08 1978-08-08 Ferranti Limited Semiconductor devices
US4152823A (en) * 1975-06-10 1979-05-08 Micro Power Systems High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS5210673A (en) * 1975-07-15 1977-01-27 Matsushita Electronics Corp Manufacturing method of silicon semi-conductor device
US4101349A (en) * 1976-10-29 1978-07-18 Hughes Aircraft Company Integrated injection logic structure fabricated by outdiffusion and epitaxial deposition
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
US4128439A (en) * 1977-08-01 1978-12-05 International Business Machines Corporation Method for forming self-aligned field effect device by ion implantation and outdiffusion
US4333099A (en) * 1978-02-27 1982-06-01 Rca Corporation Use of silicide to bridge unwanted polycrystalline silicon P-N junction
US4239559A (en) * 1978-04-21 1980-12-16 Hitachi, Ltd. Method for fabricating a semiconductor device by controlled diffusion between adjacent layers
JPS5519857A (en) * 1978-07-28 1980-02-12 Nec Corp Semiconductor
US4249968A (en) * 1978-12-29 1981-02-10 International Business Machines Corporation Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
JPS5660063A (en) * 1979-10-23 1981-05-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
US4276688A (en) * 1980-01-21 1981-07-07 Rca Corporation Method for forming buried contact complementary MOS devices
US4330931A (en) * 1981-02-03 1982-05-25 Intel Corporation Process for forming metal plated regions and lines in MOS circuits
US4374700A (en) * 1981-05-29 1983-02-22 Texas Instruments Incorporated Method of manufacturing silicide contacts for CMOS devices
US4441247A (en) * 1981-06-29 1984-04-10 Intel Corporation Method of making MOS device by forming self-aligned polysilicon and tungsten composite gate
US4445266A (en) * 1981-08-07 1984-05-01 Mostek Corporation MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance
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US4584207A (en) * 1984-09-24 1986-04-22 General Electric Company Method for nucleating and growing tungsten films

Also Published As

Publication number Publication date
WO1986007491A1 (en) 1986-12-18
EP0225920A1 (de) 1987-06-24
US4648175A (en) 1987-03-10
JPS62503138A (ja) 1987-12-10
JPH088224B2 (ja) 1996-01-29
EP0225920B1 (de) 1990-08-29

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., PAT.-ANWAELTE, 8910 LANDSBERG

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL INC., DAYTON, OHIO, US

8328 Change in the person/name/address of the agent

Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., 8910 LANDSBERG FIENER, J., PAT.-ANWAELTE, 8948 MINDELHEIM

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN