DE2940439C2 - Circuit arrangement for converting digital chrominance signals into digital hue signals and saturation signals - Google Patents

Description

7 * = egg arc tan -

2 »

are stored, wöbe! S the saturation signals, T * the hue signals and A "and Y ' the converted chrominance signals of the selected quadrant and c, and C _{1 are} constant factors, and d) an inversion controlled by the quadrant recognition stage (11) -Stage (13) which is connected to the color tone signal outputs of the table memory (12; 12 '), the circuit elements - * performing the following functions:

2) Compare the chrominance signals to be converted (X; Y) rr..i specifiable limits (X _n Il: YJl) in the quadrant detection stage (11) in order to determine the quadrant in which the chrominance signals to be converted (X: Y) and to mark the digital quadrant ID numbers of the - ■ *> determined quadrants:

ß) bttragsmäßlgc difference in the Transformatlons circuit (10) between the converted chrominance signals (A ", Y) and the limit values (A '' / 2; yjl) for determining the selected on the quadrant of the second Farbkoordinatcn system (8 ) related, converted chrominance signals (A "; Yl:

- '? ; ·) Addressing the Taoellen-Spelchers (12; ti ') by the chrominance signals (A "; Yl converted in the transformailons circuit (10) and reading out the associated saturation signals (S) and the hue signals (T *) of the selected quadrant;

δ) inverting the hue signals (7 "*) of the selected quadrant in the inverting stage (13),

if the determined quadrant is the second or fourth quadrant Isi, and

* ' ε) Determination of the color tone signals (D from the Quadranteri identification numbers marked in the quadrant recognition stage (11) and the color tone signals (T *) of the selected quadrant read from the table memory (12; 12'), wherein the quadrant identification numbers represent the most significant bits and the read-out color tone signals (T *) of the selected quadrant represent the lowest value bits of the color tone signals (T) to be determined.

f; 2. Circuit arrangement according to claim I, characterized in that the transforming circuit

! ■> (10) as an inverter controlled by the most significant bits of the digital chrominance signals (A "; Y)

<ί | for whose nlederwerilgc bits is designed.

tj | 3. Circuit arrangement according to claim 1 or 2, characterized in that

SI a) between the transformer circuit (10) and the table memory (12 ') a controllable

ii Shift stage (46) for shifting positions de: converted chrominance signals (A ". Y ') arranged-

I net is.

% _t b) a controllable correction stage (52) for the saturation signal outputs of the table memory (12 ')

5 ^5? Saturation signals (S) are connected downstream in order to reverse the shifting of positions, and

κ c) the control inputs of the shift stage (46) and the correction stage (52) with a control generator

■ '■, (48) are connected to which the converted chrominance signals (A "; ΥΊ is applied.

The invention relates to a circuit arrangement for converting digital chrominance signals of a V ^ right-angled color coordinate system In digital hue signals and saturation signals of a polar color coordinate system using a Dlgltal Spelcher according to patent P 29 23 477.

IjI <> ■ * The main patent describes a circuit arrangement for recognizing colors in which a coordinate

? -. Naientransfomiatlon of chrominance signals in hue signals and saturation signals is applied. In

This circuit arrangement is before the color recognition within an urban space color recognition spaces

Door dle / u recognizable larbcn in a colored area gcgrcn / l. By using the appropriate Idcntlflkailonssymbolc

ί ^; for clic color recognition spaces are stored in a color recognition spelcher, which are

i; len-Tripcl are addressable. During the actual color recognition, the call with a punki- and zelien-0— wise optoelectronic scanning of the colored curses to be analyzed, obtained color components

;, Trlpel continuously records the addresses of the color recognition spelcher, whereby the identification symbols stored there

]} ^: ', bole read out and the affiliation of the scanned colors to the delimited color recognition spaces

;."; is detected.

.K The color component triples can correspond to the three primary color measurement values, the chrominance and luminance

Ά nance signals or the hue and saturation signals.

S The primary color measurement signals are the right-angled coordinates of the RGB color space and the chrominance

ψ _{ mlnance and luminance signals the corresponding right-angled coordinates of the chrominance / luminance

?? Color space. The hue, saturation and luminance signals represent the cylinder coordinates of the hue / saturation

H gungs / Lumlnanz-Farbraumes, the hue signals the angle, the saturation signals the radii and

i'ff the luminance signals form the third coordinates.

γι For coordinate transformation of chrominance signals In hue signals and saturation signals is in

provided ϊβ the main patent, an analog-working function generator. Such analog function generators

But Jl are complex, unstable and have only a low working speed.

i | From DE-OS 26 40 833 it is also known to add a Dlgltal memory by means of color component traps

rf. address.

: The Irfi claim 1 specified invention is therefore based on the object of a circuit arrangement for

p Conversion of digital chrominance signals of a right-angled color coordinate system into digital 2 "

j | Hue signals and saturation signals of a polar color coordinate system using a digital

indicate fj memory, ut with the high operating speed and accuracy is _achieved; those with a ώ. small storage capacity for the Diglul-Spelcher used.

i; The invention is based on the Fi g. 1 to 5 explained in more detail.

g: It shows> 5

i | Flg. 1 a spatial representation of the chrominance / luminance color space and the hue / saturation / luminance

p nanz color space;

I FI g. 2 a projection of the color spaces;

l | Flg. 3 an execution hall! for a digital transformallons circuit;

k? 4 shows a further exemplary embodiment for a digital transformer circuit; m \

'§. Flg. 5 shows an exemplary embodiment for a correction stage.

| j To explain the coordinate transformation, FIG. 1 shows a right-angled (Cartesian) XYZ coordinate

% natensystem 1 with the coordinate zero point P ₀ - In the ATZ coordinate system 1, the chrominance

U Luminance color space 2 spanned. An arbitrarily assumed color point F has the color coordinates X, Y and Z.

y. The color coordinates X and Y correspond to the chrominance signals and the color coordinate Z to the luminance ■>?

ij signal. The chrominance-luminance color space 2 is limited by the color coordinates X _n , Y _n and Z _n.

i | In the right-angled ATZ coordinate system 1 is a cylindrical 7 "5Z. Coordinate system 3 with the coordinate

fa dinaten-zero point P ' _o inscribed, which In the ATZ coordinate system! the color coordinates A; / 2, Y _n Il and 0

5 has. The angle Γ corresponds to the color ion signal T, the radius S to the saturation signal S and the coordinate

ί 5 nate L to the luminance signal L, which is identical to the luminance signal in the chrominance luminance color space 2 ⁴ "

<?; The color location F projected in the XY-Vbznt is in the A ^- T-Ko .rdlnatensystem 8 by the color coordinates A "

! £ and Y ' and in the polar TS coordinate system 4' indicated by the angle T and the radius S.

; j To determine the angle T and the radius S of a color locus F , In the circuit arrangement

H was first determined by examining the X and Y color coordinates. In which quadrants the color location F " ¹ ^

; ' ^: falls and the relevant quadrant identification number is marked, whereby the actual coordinate conversion

[In advantageous catfish to a main quadrant, in the exemplary embodiment to quadrant 0, limited

Therefore, the '"arbkoordlnatenA" and Y', in the circuit arrangement of the magnitude to be examined color point F without addition of a sign from the corresponding color coordinates X and Y determined ⁵ "are. Thereafter, from the color coordinates A", the radii and Y '5 or . the sought saturation signals 5 according to the equation:

S = ο

(D

and the associated angle T * is initially based on the main quadrant 0 (angle 0 to 90) according to the equation:

7 * = Q arc tan - (2)

calculated. In the embodiment, .S 'and / * have a resolution of 4 BIl, so that a total of sixteen radii S and sixteen angles T * per quadrant can be distinguished, 2 are indicated for the main quadrant 0.

The angle T or the digital hue signals T sought for all four quadrants (angle 0 ^J to 360 ⁼ ) result from the calculated angle T * a 4 bits and the preceding nwklertep. Quadrant identification number of 2 bits, so that with a word length of 6 bits, a total of sixty-four angles or hue signals T can be distinguished.

If, for example, the angle T * = HLLL (45 °) and the digital quadrant identification number /.// (quadrant I) were determined, the actual angle T = UIIIlLL (135 °) results. In Flg. 2 some characteristic angles T are given as 6-Blt words, namely LLLLLL ± 0 °; LUILLL & 45 "; LIILLLL * W; LHHLLL s 135 °; HLLLLL & 180 °; HLHLLL & 225 ° and HIILLLL £ 270 °.

· <Flg. 3 shows an embodiment for a digital coordinate transformation circuit for converting the digital chrominance signals X and Y into the digital hue signals T and the digital saturation signals! 5. The coordinate transformation circuit consists of an inversion stage 10, a quadrant recognition stage 11, a table memory 12 and a further inversion stage 13. The digital chrominance signals X and Y may be shown in the embodiment example! a word length of 8 bits each

ίο have, with the individual bits denoted with small letters and their values are indicated by indices. With the 8-sheet resolution, the end values in the ΛΎ-coordinate system are 1 X _n = Y "= 255 and thus XJ2 = Y" / 2 = m.

The most significant bits (MSB) χ, and>', of the chrominance signals X and Y on lines 14 and 15 are logical in an exclusive OR gate 16 and an inverter 17 of the quadrant recognition stage U.

i 'evaluated. The output signals t, and ι, the Quudrantcn-Erkcnnungsstufc 11 on the lines 18 and 19 form the digital quadrant identification numbers a 2-Blt of those quadrants in which the to be examined

Farboue F fall. The output signals t, and /, .are at the same time the most significant bits of the bits to be determined

digital hue signals T.

As from Flg. 2 lsi, the values X 2: 128 and X < 128 provide information about whether the

- "Searching color location F right (quadrant 0; III) or left (quadrant I; II) of the!" axis and the values Y > 128 and Y <128 the corresponding statement as to whether the color location Γ is above (quadrant 0; I) or below (Quadrant II; III) the A "axis. The relevant quadrants are determined by examining the most significant Sits (MSE) .ν, and v- according to the following table:

: * XZ 128 α .ν- = // (quadrant 0 or III)

X < 128 - .v = L (quadrant I or II) (<»

>'S 128 A _r = // (quadrant 0 or I) Y < 128 A_r = L (quadrant II or IU)

. '»These relationships are evaluated in the exclusive-OR gate 16 and the inverter 17 of the quadrant recognition level W according to the following truth table:

MSB Q-K no. quadrant Λ- I- H '* H H L /. O L Il // /. I. L L L Il Il H L Il H III

L. Ii Il I. I.

In the inversion stage 10 according to Flg. 2 the digital color coordinates Λ "and Y 'of the A") "coordinate

natensystems 8 determined in terms of amount without the addition of a sign.

For this purpose, the remaining bits (LSB) x "to x _{s of} the digital chrominance signal X In are transferred to a first group of seven exclusive OR gates 20 to 26 and the corresponding remaining bits y ₀ to y _t des digital chrominance signal Y is given to a second group of a further seven exclusive-OR gates 27 to 33. All exclusive-OR gates 20 to 26 of the first group are connected to an inverter 34,

^{5 (1} in which ύζι most significant bit (MSB) x _{7 of} the digital chrominance signal X is inverted. All E exclusive-OR gates 27 to 33 of the second group are connected to a further inverter 35, which the most significant bit (MSB) ν, of the digital chrominance signal Y inverted. The Bltsx '"blsx' ₆ at the outputs of the exclusive OR gates 20 to 26 or the bits v '" to y \ at the outputs of the exclusive OR gates 27 to 33 form the digital color coordinates A ″ and Y ′ of the shifted ATT ′ coordinate system 8 according to FIG. 2.

■ "By means of the exclusive-OÜER gates 20 to 26 or 27 to 33 is carried out one of the most significant bits (MSB) χ. V- or controlled inversion or Nlchllnvertierung all least significant bits (LSB) X ₀ to X ₆ and y _a to y "of the digital chrominance signals .V and)" according to the tables:

(II)

If, for example, the most significant bit X ₁ = L, the corresponding color point F is in quadrant I or II, and the color coordinates A ″ are calculated according to Fig. 2 according to the relationship X '= X- 127 Bits (MSB) and inversion of all lower-order bits (ISB) is implemented.

V7 \ ^J until .Vi, yi y L. Xn until -Vi, L. y _n to Vh H Xu H Hi to »,

If, on the other hand, ν, = //, the color point / is in quadrant 0 or III, and the associated color coordinates A "result from equations A" - 128 .V, which in the digital Herelch by omitting the most significant bit ( MSB) and synchronization of all necessary bits (LSB) is solved. Bit y _{7 is} evaluated in the same way.

The digital color coordinates A '' and) 'ä 7 Bi! call the I4-Blt addresses of the table memory 12 via the lines 36. In the table memory 12 with a storage capacity of 16 K χ 8 there is a 4-bit color tone value T * (/ "to /,) and a 4-leaf saturation value S (s ₀ to s, were) stored after the specified equations (1) and (2) for the main quadrant ^ expects!. Thus, the A may depending 'K' Wertekomblnatlonen sixteen digital Saetti supply values S and sixteen digital tone values T "in each quadrant of the table memory 12 can be retrieved.

The hue values T * read out from the table memory 12 form the low-value bits (/ "to t _t ) _{and the quadrant identification numbers f / 4} and /,) obtained in the quadrant recognition stage 11, the high-value bits of the digital hue signals sought T with a word length of 6 bits.

If the chromaticity point to be examined F lies in quadrant I or HI, the digital hue signals 7 "* are inverted in the inverting stage 13, which is connected to the output 37 of the table memory 12. The inverting stage 13 consists of four exclusive-OR gates 39 to 42, which are controlled by the output signal ι, the quadrant recognition stage U via a further inverter 43.

The controlled inversion ensures that the color tone signals T * rise steadily from 0 to 63 or the angles from 0 to 36ö ⁼ from quadrant to quadrant.

4 shows a further embodiment of a coordinate transformation circuit.

While the table memory 12 in the embodiment according to FIG. 3 a capacity of 16Kx8 bits has, the table memory 12 'in Flg. 4 a lower capacity, e.g. B. from I Kx8 bit. The lesser one Capacity has the advantage, among other things, that the access tent is shorter and thus the working speed of the Koordlnatentransformatlons circuit is larger.

While the color coordinates A "and>" obtained in the Invcrlierungs-Sufe 10 are still available as twice 7-sheet information, in the small table memory 12 'only two 5-sheet addresses can be selected. In this case the least significant bits of the color coordinates A "and Y 'must be ignored, but this would lead to an inaccurate conversion of coordinates. To improve the accuracy, especially when calculating the digital hue signals T from small color coordinate values X ' and) ", a controllable shift stage (46) (shifter) is connected upstream of the table memory 12' an upward position shift of the color coordinates A "and Y 'is carried out according to a multiplication by a factor" a ", whereby the number of positions, by which the shift is carried out, of value areas A, B and C for the digital color coordinates A" and Y' After a position shift, the table memory 12 'is no longer addressed by the color coordinates A "and K', but by the enlarged color coordinates X" = aX ' and Y "= aY' . In this case, the digital hue signals T * and the saturation signals S result from the relationships:

.V = π ~ \ j (aX'Y + (αΥΫ

.ν =

and

'X'2 ₊ y:

7 * = Q arc tan

aY aX "

(13)

The digital color coordinates A "and Y ' are shifted up by two places (o = 4). The least significant bits .v' _o and .τ ', as well as>·'“and> · ', are evaluated. The more significant ·. Bits x ' _t and .v' ₅ as well as y \ and> ■ 'are not taken into account because they are 0 anyway.

In the value range B, the shifting circuit 46 establishes the following connection:

The value areas A, B and C are shown in Flg. 2 entered for quadrant I. Small ones fall into value area A. In value range B medium and in value range C large values of A "and Y '.
In value area A, the wear circuit 46 establishes the following connections:

(14)

ί.7 "TV tJ7

Kr, ^ - κ ·,

κ., """^ r ₁ (15)

K ₁ "K ₁₁

The digital color coordinates A "and Γ are shifted up one place Ui = 2). In this case, only the low-value bits y ' _B and y' _{o of} the color coordinates are lost. Their high-value bits v '" and y \ can be disregarded because they are 0.

In the value range C, the following connections are established by the Vcrschlebe circuit 46:

Y ₁ ,

X ", - X '\, Λ 5 A ~ R A "j X " 7 X ¹ S X \ Λ ", - x \ A ", A ""

r ₄ Γ.-

κ, r,

K, Y '"

K, K ₁ ,

■ "> The digital color coordinates A" and K 'are switched straight through (a = 1) and the low-value bits

| έ .v'o and ν ', as well as y' _D and /, discarded.

ff Ais shifting stage 46 can, for example, be an integrated four-blade fan of the type Am25S10 from the company

$ Advanced Micro Devices, Inc. use. These blocks are made up of 2-blt link commands I ₁

^l i; i and! ■ ', controlled to a control input 47 according to the following table:

Range of values shift Dispatch error A. 2 x H L B. I x L H C. ü L L

The value clusters A, B and C can be replaced by the bits x '"x \. .v '", y' ₄ . y \ and y '"of the digital color coordinates, V and Y' are defined. These bits address a read-only memory 48 (PROM) after the bits \\ and y \ In have been linked in an OR gate 49 via the address inputs 50. The shift commands I 'and V _{1 are} stored in the read-only memory 48 depending on the word areas A. B and C saved. This ^s "Move commands arrive via a line 51 to the Steer! Ngängc 47 of Verschicbe stage 46th

As can be seen from the given equations (12) and (13), digital saturation signals c 5 result for the value ranges A and B, which are too large by the factor "</" and must be corrected. For this reason, the output 38 of the table memory 12 'is followed by a corresponding correction stage 52, which is also _{controlled by the shift commands K, and ^ 1} on the lines 51 via the control inputs 53 - ^s >. The correction stage 52 carries out a downward shift in places which corresponds to a division by the factor "α".

The correction level 52 can either be used as a shifting level (shifter), which is in your system of action Corresponds to defeat level 46, or according to Flg. 5 be formed.

Instead of the table memory 12 in Fig. 3 with a capacity of 16K χ8 bits or the table memory 12 'in FIG. 4 with a capacity of 1 K 8 bits, two separate table memories each with 16 K 4 bits or 1 K χ 4 bits could of course also be used, the digital color tone signals 7 "and the digital satellite signals S are stored in the second table memory are.

In this case, a variant of the coordinate transformation circuit shown in FIG. Then, however, the lower-order bits .v ' _e and .v', as well as y ' _B and y', of the color coordinates X ' and Y' would have to be discarded, which makes the coordinate calculation less precise. The variant would have the advantage that a correction

the S'üLUgungs-Slgnalc S could be omitted. The rounding of the result could be programmed with In the wide table space.

An advantageous Ausl'ührungsfoim the correction stage 52 shows ^Q: lg. 5.

The Korektursiufe 52 consists essentially of four controllable gates 54 and 57 and one programmable read only memory 58 (PROM).

The gates 54 to 57 (e.g. of the type SN74LSM4 from Tcx'-s Instruments) are connected to the outputs 38 of the table memory 12 'in connection. The gates have 3-staic outputs. whose states voii ei.iem Free-sound input 59 are controlled so that the lines at a log. »/.« At the Frelschali entrance 59 switched through (output nlcderohmlg) and with a log. »//« are blocked (output high resistance).

The read-only memory 58 (e.g. of the type SN74S288) with a capacity of 32x8 bits also has 3-state in Outputs, the states of which are controlled by a free-switching input 61. Since both the gates and Even the read-only memory has 3-Siate outputs, the output lines can be connected directly will.

The F-'cstwertspelcher 58 has two memory areas each 16 bits, in each of which the data of the table memory 12 'divided by a = 4 or o = 2 and possibly rounded off are stored. These data are selected via ι j four of the 5-Blt-Address-Elngillnge 60, which are connected to the outputs 38 of the table memory 12 '. The memory area is selected via the fifth address input 60 '.

The control inputs 53 of the correction stage 52, at which the shift commands V ₁ and V ₂ appear, are available via an OR gate 63 with the Frelschalt input 59 of the gates 54 to 57 and via an inverter 64 with the FrcUrhali FlngiinB ή! dns read-only memory 58 In connection. The address input 60 'of the read-only memory 58 2 "is supplied with the shift command V _x as a control bit.

The operation of the correction stage 52 is as follows. In the event that no position shift has taken place in the shift circuit 46 (see Table 17; V _x = V ₁ = L), the gates 54 to 57 are switched through and there is no correction of those read out from the table memory 12 ' digital Süttlgungs-Signal S * instead. If, however, a position shift by “1” or “2” has been carried out in the shift circuit 46 (Table 17: V ₁ = H or L: V ₁ = L or H), the gates 54 to 57 are blocked and the outputs 62 of the read-only memory 58 is effective. Then the digital saturation signals S * read out from the table memory 12 'address the read-only memory 58 and the shift command V, at the address input 60' decides as a control bit whether the divided by the factor "2" or "4" and thus corrected saturation signals 5 are read from the read-only memory 58. . '"

In addition 5 sheets of drawings

Claims (1)

Patent claims: 1. Circuit arrangement for converting digital chrominance signals of a right-angled color coordinate system into digital hue signals and saturation signals of a polar color coordinate system using a digital memory according to Patent P 29 23477, characterized by a) a transformation circuit (10) to which the digital chrominance signals (X; Y) are applied, b) a quadrant recognition stage (11) to which the high-quality bits of the digital chrominance 1 »signals (X; Y) are applied, c) an addressable table memory (12; 12 "), the address inputs of which are connected to the outputs of the transformer circuit (10) and in which the saturation signals and hue signals of a selected quadrant as a function of converted chrominance signals ( A "; Y ') of the selected quadrant according to the functions: