DE2648149A1 - Multiple pulse rectifier control circuit - has timing cycle monitoring device preventing cycle from falling below minimum value - Google Patents

Abstract

The rectifier is controlled by the mains supply and generates quickly variable d.c. currents of very different intensities from a polyphase a.c. mains through ignition angle controlled thyristors. Ignition pulses are applied to the thyristors, whose phase relation to the mains voltage is determined by control pulses in accordance with a control voltage. A timing cycle monitoring device (18) has a timing element to which control pulses are applied. The device (18) has a limit monitoring device which prevents the timing cycle determined by the above time element from falling below a minimum value, thus holding it at the limit value.

Description

Control circuit for line-commutated converters

The invention relates to a control circuit for line-commutated, multi-pulse Power converters for generating quickly variable direct currents of very different types Size from a multi-phase AC network via firing angle controlled thyristors, which ignition pulses are supplied, their phase relation to the AC mains voltage Control impulses depending on a control voltage is specified.

With such a direct current generation via ignition angle controlled Thyristors often encounter difficulties resulting in very high currents for a short time lead, which damage both the thyristors and the consumers or can destroy. To avoid this, they are mostly very fast-acting Upstream fuses. These fuses generally provide adequate protection against damage, but result in an increased susceptibility to failure. To avoid this it is known (see e.g. DT-OS 1 638 377), monitoring devices in the control circuit to be provided for the converters, which trigger the thyristors in the ignition angle ranges exclude should, in which currents too high could flow, or counter-ignition of thyristors is possible. These monitoring devices are sufficient however, in many cases this does not work, or results in too great a narrowing of the ignition angle range, especially when large changes in consumer or load resistance are possible, as is often the case with controllable DC drives, for example.

It is also known to limit overcurrents (see e.g. DT OS 2 042 107), disturbances of the direct current via a target / actual value comparison balance; Since overflowed by a corresponding ignition of a thyristor However, this does not affect the subsequent ignitions at the earliest via a current measurement can, high peak currents of individual half-waves of the AC mains voltage do not avoid this.

It is an object of the invention to control the power converters to enable which overcurrents also during the running time of individual half-waves the AC mains voltage is safely prevented, even if the load resistance is high changes, the setpoint control voltage is changed abruptly or e.g.

Interfering pulses are introduced via the control voltage supply.

This object is achieved in that a cycle time monitoring device is provided with a timing element to which the control pulses are fed Cycle time monitoring device has a limit value monitoring, which the undershoot a smallest cycle time specified by the timer is prevented and this the cycle time a constant cycle time corresponding to the limit value holds.

If the monitoring device is set up with digital switching elements, the result is a particularly interference-free circuit that is immune to external voltage fluctuations is largely independent. It is advantageous here if the timing element is a monostable Is a flip-flop which is flipped into the astable switching state by the control pulses and after the specified smallest cycle time in the stable switching state tilts back.

The monostable multivibrator can enable a control pulse with AND elements be connected in such a way that it only emits an enable signal as long as the flip-flop is in the stable switching state.

The control circuit is particularly advantageous for a converter with anti-parallel connected thyristors to generate Direct currents, the size and polarity of which can be changed via a control voltage - as is usual, for example, when controlling reversing drives - if this is the case both the thyristors for rectifying the positive half-waves, as well as the Thyristors for rectifying the negative half-waves of the mains AC voltage a separate timing element is assigned for cycle time monitoring.

In all of these cases, the running time of the invention arranged timer prevents a sudden increase in the current, wherein the maximum current rise through a corresponding choice of the running time of the timer adapted to the highest permissible current during a half-cycle of the AC mains voltage can be. This can increase the current - as is generally desired for drives is - so limited that there is a targeted increase in current results, with the new current setpoint, according to an optimal adaptation is reached after 2 to n half-waves. Has proven to be particularly advantageous in the Application for controlling drives with DC motors a dimensioning of the Time element proved, in which the smallest predetermined by this time element Cycle time corresponds to about 50 to 80 t0 of the cycle time that a constant ignition angle setting has the consequence. This results in a delayed maximum current increase - E.g. from current value zero to full load after 2 to 5 half waves of the mains alternating voltage - one that is largely independent of the motor EMF and that is quick to react and yet impact-free Control of the drive, a significantly reduced interference load on the AC network and for the control in the particularly critical phase of a sudden start-up absolute stability, as the controller then works in saturation.

Full effectiveness can be found in controls with rapid current reversal - e.g. for reversing drives, also for converter circuits with circular current - Achieve this when the cycle time monitoring device has a device, which, if there is no control pulse, prevents a follow-up pulse as soon as this starting from the rear zero crossing of the half-waves of the alternating voltage to be rectified would have a follow-up time which is smaller than the predetermined smallest Cycle time and a control pulse as soon as the follow-up time of the smallest Corresponds to cycle time. This can be achieved if the input is the monostable Trigger stage is connected to the output of a synchronous clock generator, which at the end of each half-cycle of the AC mains voltage delivers a pulse and the monostable flip-flop toggles into the astable state, but the flip-flop after the setting by one Control pulse leaves unaffected.

In this way it can be avoided that a thyristor, which - e.g. before the commutation - did not receive an ignition pulse suddenly with an ignition or glitch is triggered, which could cause a large current spike.

This circuit can also be used for this with little additional effort ensure that even with a strong inductive load or large back EMF in which a current through a thyristor continues for a long time after the voltage zero crossing the corresponding half-wave can flow for counter-ignition via another thyristor is prevented. This becomes possible if the control pulses to generate the Direct currents from the positive and negative half-waves of the mains alternating voltage two similarly connected and constructed pulse monitoring devices One release device each are provided and these two monitoring devices are linked in such a way that when a control pulse is released by one of the release devices until the end of the respective half-cycle of the AC mains voltage the other release device receives a blocking signal. As release devices can use the provided AND-terms with one additional separate each Serve input.

Further details and advantageous developments of the invention are described in more detail with reference to the exemplary embodiments shown in the drawing. 1 shows the basic structure of a network-guided according to the invention multi-phase converter, Fig. 2 shows the circuit principle of a Cycle time monitoring device according to the invention Fig. 3a to 3f voltage and Current curves of the converter over several cycle times. FIG. 4 shows a diagram for the dimensioning of the timing element according to the invention and FIG. 5 the control circuit for a reversing converter.

In Fig. 1 are the main circuits of a three-pulse thyristor converter shown in simplified form, with the three phase connections 1, 2 and 3 of a three-phase network in a known manner via a thyristor 4, 5 and 6 to a common connection point 7 of the load are performed, which is here a DC motor 8, which with its other The end is e.g. at the center conductor 9 of the three-phase network. The control circuit 10 for the converter exists in a known way (see e.g. DT-OS 2 213 612) from a network synchronous clock 1L, a reference voltage generator 12, one Control pulse logic 13 and an ignition pulse distributor stage 14 clocks. In the reference voltage generator 12 is a mains-synchronous reference voltage, e.g. sawtooth cutting with three times Mains frequency generated, which is fed to a comparator 15, the control pulses supplies whose phase relation to the reference voltage as a function of a supplied Control voltage 16 is changed. These control pulses become the control pulse logic 13 and from there when an external ignition pulse release signal is applied 17 to the ignition pulse distributor stage 14 passed. In this Stage 14 then generates the ignition pulses for the individual thyristors, with these pulses from the control pulse logic 13 are obtained by selected control. The selection of the control impulses is done by means of synchronous impulse voltages from the Clock 11.

The control pulse logic 13 contains a cycle time monitoring device -18 according to the invention, which contains an analog working timing element such as a blocking oscillator, the the transmission of follow-up pulses under a predetermined minimum cycle time and only passes it on after the smallest cycle time has elapsed. Essential A digital one shown in FIG. 2 operates more independently of external influences Cycle time monitoring device. There the control pulses are sent to an input 20 an AND element 21, at the second input 22 of which the output 23 is a first monostable flip-flop 24 is at which a release signal in the stable state for the AND element 21 lies. The output of the AND element 21 is at the input of a second monostable flip-flop 25, which pulses with control in a known manner constant pulse length to the next stage. Becomes the second tipping stage 25 set on the leading edge of a control pulse from the AND element 21 gives they send a pulse to the input of the first monostable via a further output 26 Trigger stage 24 and tilts it into the astable state. This creates the AND element 21 blocked, but this no longer has any influence on the second flip-flop 25, which passes this control pulse on with a constant pulse width. The first tilt stage 23 is dimensioned such that it is only after a fixed or adjustable Time tilts back to the stable state, which corresponds to the smallest cycle time. If the leading edge of the next control pulse arrives during this time the and-member 21, this control pulse remains blocked until the first flip-flop tilts back, releases the AND element when a control pulse is applied and sets the second flip-flop again.

The cycle time of this next pulse then corresponds, independently from the arrival of the leading edge of the control pulse at input 20, which is fixed or adjustable smallest cycle time.

The effect of the cycle time monitoring can be seen from FIG. 3.

In Fig. 3a are the positive half waves 30 of the AC line voltage represented by their rear zero crossing 31 from pulses of the clock generator 11 a mains-synchronous sawtooth-shaped reference voltage 32 is generated. In the comparator 15 this is compared with a control voltage 33 (16) and a control pulse voltage Fig. 3c generated, a leading pulse edge 34 occurring as soon as the reference voltage 32 is smaller than the control voltage 33 and a trailing pulse edge 35 is formed when it gets bigger again. According to FIG. 3b, this takes place simultaneously with the steep rise of the sawtooth flank.

With the front flank 34 (as already explained with reference to FIG. 2) the two monostable flip-flops 24 and 25 set, the first flip-flop 24 at Set the second flip-flop 25, the AND element 21 by the output signal Fig. 3d blocks a predetermined time Tsp. In Fig. 3e, the output pulse voltage is the second flip-flop 25 shown, the pulses through this stage a constant Get pulse width. Due to the small control voltage 33 during the first three The clocks shown receive the corresponding thyristors firing pulses with a Ignition angle 36, with an opening only shortly before the zero crossing the Half-waves takes place. As a result, only small currents 37 flow in intermittent operation. Jumps now the control voltage - as shown in Fig. 3b after the third clock - high, becomes in the comparator the next leading edge 38 shortly after the leading edge of the previous one Pulse generated, whereby a control pulse without the cycle time monitoring device 39 would be passed, which the corresponding thyristor with an ignition angle 40 would ignite. This can, since, for example, the motor 8 previously had none or only a very small one Back-EMF could build up, lead to a very high current peak 41, which is a Damage or destruction of the thyristor, the motor, a fuse tripping and / or other disturbances.

Since, however, at the time of the arrival of the leading edge 38 at the AND element the blocking voltage 42 is applied, it remains ineffective and only arises when the voltage is tilted back 43 of the first flip-flop 24, which by setting the second flip-flop 25 afterwards is set again immediately. This renewed blocking of the AND element can result in the following front flank 44 does not have any effect either. This process is repeated until the cycle time, which is synchronous with the network (TN t 1200) shorter blocking time Tsp, which corresponds to the smallest cycle time, the phase position is balanced. During this time the respective ignition angle changes in such a way that that for each half-wave there is a larger current as shown in FIG. 3f.

Depending on the choice of the ratio of the smallest cycle time Tsp to the network-synchronous cycle time TN, the current rise can be limited to the maximum value even with the most unfavorable jump in the control voltage 33 such that, for example, only the nominal current flows at most to the next half-cycle or the nominal current is only reached after n half-cycles . The curve in FIG. 4 can serve as an aid for dimensioning the smallest cycle time Tsp. There the ratio of the slope time TSlope to TN is given, which in a converter according to FIG. 1 with a direct current motor corresponds approximately to the number of half-waves after which the nominal current is reached from an output current of zero. The curve corresponds to: The longer the smallest cycle time is selected - which must always be shorter than TN - the smoother and more stable the run-up of the current is, with interference pulses, which are introduced via the control voltage, for example, are largely masked out or, in the worst case, only cause disturbances that correspond to the limited current increase after a half-wave.

FIG. 5 shows the control pulse logic (13 according to FIG. 1) for a reversing converter shown with anti-parallel connected thyristors, e.g. for controlling Reversing drives are used for position control. This control pulse logic has two largely identical circuits. In each of these circuits is one with five separate inputs provided AND element 50 (51) with its output to the one Input of a flip-flop 52 (53) out, each with an output via a Capacitor 54 (55) at the set input of a monostable multivibrator 56 (57 (and with the second output is at the input of a further AND element 58 t59). Of the The negated output of this AND element is connected to the set input via a resistor 60 (61) another monostable flip-flop 62 (63), which with a exit is connected to one of the five inputs of the first AND element 50 (51). At the other inputs are each the connection for a network-synchronous clock signal 64 (65), the control pulse voltage from the associated comparator 66 (67), an external one Enable signal 68 (69), as well as the output of the flip-flop 53 (52) of the other circuit connected to which the capacitor 55 (54) is connected.

The AND element 50 (51) is then in each case by the leading edge of a Pulse of the control pulse voltage from the associated comparator 66 (67) opened, if a release signal at terminal 68 (69) and no blocking signal at the other inputs is present. The flip-flop 52 (53) is then set by such a leading edge and a set pulse is given to the flip-flop 56 (57) via the capacitor 54 (55). The set input of this flip-flop 56 (57) is via a parallel circuit 70 (71) a resistor with a diode at a positive voltage, thereby preventing is that when the flip-flop 52 (53) is reset, the flip-flop 56 (57) responds. This monostable multivibrator 56 (57) generates control pulses 74 of constant width, with which the ignition pulses via an ignition pulse distributor stage (14 according to FIG. 1) for the corresponding thyristors are generated.

These control pulses are generated simultaneously via a capacitor 72 (73) fed to the input of the monostable multivibrator 62 (63) via the resistor 60 (61) is located at the output of the AND element 58 (59). The leading edges of the control pulses 74 set the flip-flop 62 (63), whereas the trailing edge has one at the set input connected diode 75 (76) is made ineffective. The monostable multivibrator 62 (63) is dimensioned such that it can be set during a predetermined or adjustable Cycle time emits a blocking signal to the AND element 50 (51). This cycle time corresponds to the smallest cycle time Tsp.

an opening signal due to a rapid increase in the control voltage to the input of the AND element 50 (51), this remains ineffective until it is automatic Tilting back the tilting stage 62 (63). The change at each back zero passage The voltage generated clock pulse 77 is set by bypassing the AND element 50 (51) from terminal 64 via a capacitor 78 (79) to a reset input of the Flip-flop 52 (53) out, this regardless of this back to the initial state. The reset is done by the rear edge of the pulse, since the front edge Edge via a parallel circuit 80 (81) of a resistor at the reset input is suppressed with a diode. The clock pulse 77 is at the same time on the second Input of the AND element 58 (59), however, cannot open it because it is only with its trailing edge initiates a reset of the flip-flop 52 (53) and only when it is reset Flip-flop 52 (53) sends an enable signal to the second input of AND element 58 (59) got.

This arises, for example, from reversing the polarity of the control voltage on the comparator for a positive voltage (66) no more pulse voltage, but only on the comparator for a negative voltage (67), the AND element 52 always remains in its initial state.

In this case, no more control pulses can occur at output Zp, there is now an ignition of the opposing polarity thyristors via the control pulses at the output Z of the second circuit takes place.

n Likewise, the trigger stage 62 is no longer set, the blocking of the AND element by this flip-flop 62 is also omitted. Jumps the control voltage suddenly changes or an interference pulse arrives at input 66, this can cause a very high current peak with all the disadvantages already mentioned Have consequence. This is prevented in the circuit via the AND gate 58, which is in not set flip-flop 52 from this always a release signal receives, so that the clock pulses 77 via the second input of this AND element the Set tilt level 62. As a result, the AND element 50 is always blocked in an area which de; Ignition angle range for high currents corresponds. In the same way is also the circuit for generating the control pulses Z for negative DC voltages gun.

n To counter-ignition of the thyristors in the critical starting area to prevent the tax impulses on a locking ring 82 (83) of the AND element 50 (51).

The clock pulses 77 are relative to the clock pulses at the input 65 to shifted in phase by an electrical angle of 60 ° (see DT-OS 2 213 612), since the trailing zero crossing of the corresponding half-waves (Fig. 3a) corresponds to the corresponds to the front zero crossing of the EXalbvelLen with opposite polarity.

The same also applies to the pulse voltage from the corresponding Comparators for the same ignition angle.

With a strongly inductive load or a very large back EMF of the Motor, it is possible that even if the direction is not changed too quickly Control voltage of the previously ignited thyristor is still open when the ignition an oppositely directed thyristor takes place, causing very high currents in the converter arise that cause an immediate response of the fuse or destruction of a thyristor can cause.

Such a counter-ignition is implemented in the control pulse logic according to FIG. 5 by linking the two circuits.

For this purpose, the control pulse output 84 (85) of the flip-flops is in each case 52 (53) of the one circuit with a separate blocking input 87 (86) of the Un: song 51 (50) connected to the other circuit. Da dli! Flip-Fiop's 52, 53 after setting by a front impulse difference from the associated comparator (66, 67) until set for the arrival of the trailing edge of the associated clock pulse 77 remain, there is a blocking of the AND element 51 (50) for the opposite polarity DC voltage up to a range in which a controlled counter-ignition of the thyristors is not possible more is possible.

The Lrfindung is particularly for circuit current afflicted converter circuits Suitable for fast-reacting DC control drives, but can also be used for others Converter circuits offer the same advantages. She's not on three pulse, three-phase circuits, but also, in an equally advantageous manner, e.g. suitable for high-pulse or six-phase converter circuits. Especially at It can be advantageous to travel position control by alternately firing the thyristors with a control voltage of zero, a smaller alternating current will flow across the motor or by setting the comparators accordingly at zero control voltage to allow a bias current to flow in one direction, e.g. to calculate the weight of a part of the system. This means that at a control voltage Zero the converter is still working or thyristors are ignited. Want you can switch off the power supply via an external signal via an external release signal take place at the inputs 68, 69 of the AND element 50, 51 lies. This safe locking of the converter can also be used in other cases be advantageous, e.g. if the thyristor blinds or other parts of the system are switched off should be protected via an error signal.

L e r s e i t e

Claims (11)

Claims 1. Control circuit for line-commutated multi-pulse converters to generate rapidly variable direct currents of very different sizes a multi-phase alternating current network via firing angle controlled thyristors, which Ignition pulses are supplied, their phase relation to the AC mains voltage by control impulses is specified as a function of a control voltage, characterized in that that a cycle time monitoring device (18) with a timing element (24) is provided is to which the control pulses are supplied, the cycle time monitoring device (18) has a limit value monitoring system, which indicates that the Timing element prevents the smallest cycle time (Tsp) and this prevents the cycle time keeps constant to a cycle time corresponding to the limit value. 2. Control circuit according to claim 1, characterized in that the Timing element is a monostable multivibrator (24, 62, 63) which is controlled by the control pulses is tilted into the astable switching state and according to the specified smallest Cycle time (Tsp) tilts back into the stable switching state. 3. Control circuit according to claim 2, characterized in that a Output of the monostable multivibrator (24, 62, 63) connected to a control pulse release is and the output (23) emits a release signal, so.lange the flip-flop in stable switching state. 4. Control circuit according to claim 3, characterized in that the Control pulse release is a logical AND element (21, 50, 51), a first input (20, 66, 67) of the AND element the control pulses are fed to a second Input (22) the output (23) of the monostable multivibrator (24, 62, 63) is and the pulse voltage at the output of the AND element (21, 50, 51) via a further flip-flop (25, 56, 57) the output of the cycle time monitoring device and the input of the monostable flip-flop (24, 62, 63) are supplied. 5. Control circuit according to one of claims 1 to 4, characterized in that that the timer (24, 62, 63) is dimensioned such that the through this timer specified smallest cycle time (Tsp) corresponds to about 50 to 80 e of the cycle time (1200), which results in a constant ignition angle setting. 6. Control circuit for a converter for generating direct currents, whose size and polarity can be changed, according to one of claims 1 to 5, thereby characterized that both the thyristors for rectifying the negative half-waves, as well as the thyristors for rectifying the positive half-waves of the AC mains voltage a separate timing element (62, 63) is assigned for clock time monitoring. 7. Control circuit for a converter according to claim 6, characterized characterized in that the cycle time monitoring device has a device which prevents a follow-up pulse if there is no control pulse if this starting from the rear zero crossing of the half-waves of the alternating voltage to be rectified has a follow-up time which is smaller than the predetermined smallest cycle time (Tsp) and releases a control pulse as soon as the follow-up time of the smallest cycle time is equivalent to. 8. Control circuit according to claim 4 and 7, characterized in that that the input of the monostable multivibrator (62, 63) with the output of a network synchronous Clock is connected, which at the end of each half cycle of the AC mains voltage supplies a pulse and the monostable multivibrator (62, 63) with the output of a network synchronous clock is connected, which at the end of each half-wave the mains AC voltage supplies a pulse and the monostable multivibrator (62, 63) switches to the -astable state, but this after setting by a control pulse leaves unaffected. 9. Control circuit according to one of claims 6 to 8, characterized in that that the control pulses for generating the direct currents from the positive half-waves the AC mains voltage from an ignition angle comparator (66) for positive half-waves A first AND element (5G) is fed to the first input of a flip-flop (52) are, the second input for resetting the flip-flop (52) from a network synchronous Clock (64) Pulses are fed to the end of each half-wave of the mains alternating voltage, at a first output of the flip-flop (52) a connection (Zp) for controlling the corresponding Thyristors and the input of the monostable multivibrator (62), at a second output the input of a second AND element (58) is at the second input Output of the synchronous clock generator (64) is performed and the output of this AND element (58) is also connected to the input of the monostable multivibrator (62), the output of which is connected to a further input of the first AND element (50). 10. Control circuit according to one of claims 6 to 9, characterized in that that for the control pulses to generate the direct currents from the positive and the negative half-waves of the AC mains voltage are two similarly connected and constructed Pulse monitors are linked in such a way that when a control pulse is released by one of the release devices (50) the other release device until the end of the respective half-wave of the AC mains voltage (51) receives a locking signal. 11. Control circuit according to claim 10, characterized in that the release devices AND elements (50, 51) with several separate inputs are, the outputs of the AND gates (50, 51) each at the input of a flip-flop (52, 53) and each have an input (87, 862 of the AND elements (50, 51) with an output of the flip-flop (52, 53) for the Pulse monitoring of the half waves with opposite polarity.