DE19614876C1 - Simple mass production of integrated semiconductor device - Google Patents

Abstract

A process for producing an integrated semiconductor structure, having I<2>L logic inverters in combination with highly blocking npn transistors, involves subjecting a p-type semiconductor substrate to (a) masking and introducing a slowly diffusing n-type first dopant for forming buried layer zones which are then annealed; (b) masking and introducing a p-type second dopant for forming buried separation zones; (c) masking and introducing a rapidly diffusing n-type third dopant for forming additional buried layer zones; (d) annealing the buried separation zones and the additional buried layer zones; (e) epitaxially growing a single crystal n-type semiconductor layer; (f) masking and introducing a p-type fourth dopant to form p<+> separation zones aligned with the buried separation zones; (g) masking and introducing an n-type fifth dopant for forming n<+> deep connection zones; (h) masking the npn base zone (8), the I<2>L base connection zone (8') of the I<2>L injector (8") and the I<2>L base zone (9) with a first auxiliary layer (12c); (i) covering the I<2>L base (9) with a second auxiliary layer (13c); (j) introducing a p-type sixth dopant into the base zones (8, 8', 8") and into the I<2>L base (9); (k) removing the second auxiliary layer (13c); (l) introducing a p-type seventh dopant into the base zones (8, 8', 8"); and (m) masking and introducing an n-type eighth dopant to form the collectors of the I<2>L logic inverters (11) and the emitters (10b) and collectors (10a) of the npn transistors.

Description

The invention relates to a method for producing an integrated semiconductor arrangement with I²L Logic inverters in combination with high blocking NPN transistors and a Process for their production.

An essential parameter for the functioning of an I²L logic circuit is the effective upward current gain B _EFF . It can be defined as follows ( Fig. 2, 3a and 3b):

With

I _C | _{Ib = 0} : collector current of the inverter with open base connection
I _B | _{Ub = 0} : Current that flows from the base connection when the base is at reference potential

each with a constant injector _voltage U _inj .

According to F. M. Klaassen, "Device Physics of Integrated Injection Logic", IEEE Trans. Electron Devices, vol. ED-22, pp. 145-152, March 1975, this one Parameters can also be calculated according to the following relationship:

With

B _up = up-current amplification of the NPN transistor of the inverter (without injector);
I _n0 = transfer saturation _{current of the step-} up NPN transistor;
I _p0 = transfer saturation _{current of} the injection _transistor (lateral PNP).

In order to obtain the _{highest possible} upward _{current gain} B _EFF , both the upward _{current gain} of the NPN transistor of the inverter B _up and the ratio of the transfer saturation _current I _{n0 of} the upward operated NPN transistor to the I _{p0 of} the injection transistor should be as large as possible.

If you summarize all constants in "const", the ratio of the both transfer saturation currents are also written:

With
R _bi = inner baseline resistance of the NPN (pinch resistance);
N _EPI = epitaxial concentration;
W _BPNP = base width of the injection _transistor ;
F _KOLL = collector area of the NPN transistor (upwards);
F _PNP = effective emitter area of the injection transistor.

With these 5 parameters and the up-current amplification of the NPN transistor of the inverter B _up , which itself also depends on some of these parameters, the up-current amplification B _EFF can be set. Technologically, only R _bi and N _{EPI can be} influenced. The other parameters can be changed via the layout geometries. One usually tries to use minimal geometries.

In a standard buried collector process (SBC process) without additional mask or technology steps, the combination of I²L logic and high-blocking NPN transistors is limited because the increase in R _bi and N _EPI the reverse voltage of the NPN transistors reduced.

From "Technology for LSI modules in linearly compatible I²L technology", research report T83-210, October 1983, pp. 50-61, the use of an additional buried layer to increase the parameter N _{EPI is} known.

From L. Halbo and TA Hansen: "I²L and High-Voltage Analog Circuitry on the Same Chip", IEEE J. Solid-State Circuits, vol. SC-14, pp. 666-671, August 1979, it is known to increase the parameter R _bi by reducing the base width (shallow base).

Both measures increase the upward current gain B _up .

However, both proposals pose in the series production of integrated Semiconductor devices pose a problem. Because of the inevitable Process tolerances can cause circuit breakdowns due to a too small or occur due to excessive upward current amplification. With a too small one Upward current amplification, the inverter no longer has a logic function, at If the upward current gain is too high, the reverse voltage of the inverter is up to reduced to the emitter-collector short circuit.

An integrated semiconductor arrangement with I²L logic inverters in combination with high-blocking NPN transistors is known from US Pat. Base compared to the bases of the high blocking NPN transistors. As a result, the upward current gain B _{EFF of} an I²L inverter is increased in such a way that sufficient operational reliability of the circuits is ensured even in series production. The properties of other components used in bipolar technology are not affected.

From this document there is also a method for producing such Semiconductor arrangement known. On a p-type substrate, a first n-type epitaxial layer grew. Then be through endow the additional buried layers with antimony in the area of  I²L logic inverters defined. Then a second n-type epitaxial layer grew up. Then separation zones are introduced and then annealed the assembly in a thermal process. Thereby diffuses the antimony from the first epitaxial layer into the second and forms the additional buried layer zones. Finally, the base zones and the Injector zones of the inverters and the base zones of the high-blocking NPN transistors are made together in the following process steps. The reduced base width of the I²L part is different Penetration depths of the collector zones in the I²L base or the base zones of the high-blocking NPN transistors achieved.

The object of the invention is a method for producing an integrated Semiconductor arrangement with I²L logic inverters in combination with high-blocking NPN transistors indicate that it is a simple process distinguished and with a sufficient  Operational reliability of the circuits guaranteed even in series production is.

This task is accomplished through a method of making an integrated Semiconductor arrangement with I²L logic inverters in combination with high-blocking NPN transistors with the features of claim 1 solved. The beneficial The method is designed according to the characteristics of the dependent Expectations.

In an integrated semiconductor device with I²L logic inverters in combination with high-blocking NPN transistors, the I²L logic inverters having an injector zone, a base zone and a collector zone arranged in the base zone and the high-blocking NPN transistors a collector zone, a base zone and one arranged in the base zone Have emitter zone; and the I²L logic inverters and the NPN transistors are arranged in an epitaxial semiconductor layer on a semiconductor substrate ( 1 ) and are arranged between the epitaxial semiconductor layer and the semiconductor substrate buried layer zones ( 3 ), it is provided that in the areas of the I²L Logic inverters on the buried layer zones ( 3 ) further, additional buried layer zones ( 4 ) are arranged and that the base zones of the I²L logic inverters have a base width which is at least partially reduced compared to the base zones of the high-blocking NPN transistors. The properties of the other components used in bipolar technology are not affected.

The basic width of the I²L logic inverter is advantageous compared to the basic width of the NPN transistors reduced by approximately 10%.

The remaining residual thickness of the epitaxial semiconductor layer between the additional buried layer zones ( 4 ) and the base zones of the I²L logic inverters is approx. 1-2 µm.

The buried layer zones ( 3 ) are doped with a slowly diffusing substance, while the additional buried layer zones ( 4 ) are doped with a rapidly diffusing substance.

The method of manufacturing an integrated semiconductor device with I²L- Logic inverters in combination with high-blocking NPN transistors the following, in the order given Procedural steps. In a P-type semiconductor substrate, the following occurs Masking the introduction of impurities for buried layer zones by a first, slowly diffusing dopant of the N type. Then the Buried layer zones healed in a thermal process. After renewed Masking involves the introduction of the impurity implantation for buried ones Separation zones by a second P type dopant. After a The masking points for additional buried layer zones are further masked through a third, rapidly diffusing N-type dopant. Healing the buried separation zones and the additional buried Layer zones occur in a single thermal process. Then one monocrystalline semiconductor layer of the N type epitaxially grown. After a Masking takes place in the impurities for the p⁺ separation zones in Agreement with the buried separation zones by a fourth P type dopant. After masking again, the Interfaces for the n⁺-deep connection zones due to a fifth dopant from the N Type. Then the I²L base, the I²L injector and NPN base based on window openings in a first Auxiliary layer defined. Then the first defects are introduced into the base zones and at the same time into the I²L base by a sixth P type dopant. Then the window opening for the I²L base is through a second auxiliary layer is covered and then second impurities in the NPN base and the I²L injector zone by a seventh P-type dopant brought in. After masking, the impurities are introduced for the collectors of the I²L logic inverters and the emitters and collectors of the NPN transistors through an eighth N-type dopant.

Brief description of the figures

Fig. 1 shows an integrated semiconductor device having I²L logic inverter in combination with high-barrier NPN transistors after manufacture by the method according to the invention,

Fig. 2 shows a I²L inverter according to the prior art,

Fig. 3a shows an equivalent circuit diagram of an I²L-inverter in the measurement of I _c,

FIG. 3b shows an equivalent circuit diagram of an I²L-inverter in the measurement of I _b,

Fig. 4 shows a cross section through a semiconductor device at a first time of its manufacture,

Fig. 5 shows a cross section through a semiconductor device at a second time of its manufacture,

Fig. 6 shows a cross section through a semiconductor device at a third time of its manufacture,

Fig. 7 shows a cross section through a semiconductor device at a fourth time of manufacture,

Fig. 8 shows a cross section through a semiconductor device at a 5th time of manufacture,

Fig. 9 shows a cross section through a semiconductor device at a 6th time of manufacture,

Fig. 10 shows a cross section through a semiconductor device at a time of manufacture of 7,

Fig. 11 shows a doping profile of the semiconductor device according to the invention.

Fig. 1 shows an integrated semiconductor device with I²L logic inverter in combination with high-blocking NPN transistors in cross section. The illustration is chosen so that an I²L inverter can be seen on the left side and a high-blocking NPN transistor can be seen on the right side. I²L inverter and high-blocking NPN transistor are separated by a separation zone 6 extending from the semiconductor surface to substrate 1 . In the p-type semiconductor substrate, the buried layer zones 3 of the n type are arranged both in the region of the I²L inverters and in the NPN transistors. There is an epitaxially grown semiconductor layer 2 of the n type. In the area of the I²L inverter, another, additional buried layer zone 4 of the n type is arranged on the buried layer zone 3 . It extends further into the epitaxial layer 2 and thus reduces the remaining thickness of the epitaxial layer 2 that remains above the additional buried layer zone 4 .

In the surface of the epitaxial layer, the base zone 8 and the collector zone 10 a of the NPN transistor, the base connection zone 8 ', the injector zone 8 ''and the I²L base zone 9 of the I²L inverter are embedded. In the I²L base zone 9 is the collector zone 11 of the I²L inverter and in the base zone 8 of the NPN transistor its emitter zone 10 b is embedded. The base region 8 of the NPN transistor, the base terminal zone 8 ', the injector 8' 'and the base region 9 of the I²L- I²L inverter are of the p type; the collector zone 10 a, the emitter zone 10 b of the NPN transistor and the collector zone 11 of the I²L inverter are of the n type. The effective base zone of the I²L inverter, the I²L base 9 , has a reduced base width compared to the base zone 8 of the NPN transistor and the base connection zone 8 'of the I²L inverter.

Separation zones 6 of the p type, which extend from the surface of the epitaxially grown layer 2 into the semiconductor substrate 1 , ensure electrical insulation of the components. An insulating layer 12 is arranged on the surface and has window openings for the contact of the active zones with the metallization 14 .

In the present invention, two measures are combined which increase both B _up and I _n0 / I _p0 . The parameters R _bi and B _{up are} increased by reducing the base width of the I²L base zone 9 and at the same time by an additional buried layer zone 4 in the area of the I²L logic inverters. Each of the two measures is carried out in such a way that it does not ensure compliance with the lower limit value for B _EFF . However, together enough safety reserves are obtained for the reverse voltage of the inverter.

The first measure is to reduce the base width (shallow base) of the I²L base zone 9 and thereby to increase the parameters R _bi and B _up .

This can be achieved advantageously if the windows in a first auxiliary layer (z. B. SiO₂) for the implantation of the I²L base zones 9 together with the windows of the other p areas, such as base zones of the high-blocking NPN transistors 8 or the zones of high-resistance p-resistors, opened ( Fig. 9) and then in a masking step by a second auxiliary layer 13 c, z. B. a paint. A subsequent first implantation step doped the base zones 8 and any p-resistors, a second implantation step after removing the second auxiliary layer 13 c all open zones, ie the base zones of the high-blocking NPN transistors 8 , the p-resistors and the I²L- Base zones 9 . After healing and post-diffusion, a lower sheet resistance and a greater depth of penetration are obtained in the base zones 8 than in the I²L base zones 9 ( FIG. 10).

The manufacturing tolerances of the implantation steps and the Emitter diffusion. Comparatively small fluctuations in the current gain and the associated pinch resistance of the high-blocking NPN Transistors can cause extreme fluctuations in the current gain of the I²L Cause logic inverters due to their high internal Baseline resistance (= pinch resistance).

The second measure consists in increasing the parameter B _up by increasing the concentration on the emitter side by means of an additional buried layer diffusion.

In general, efforts are made to keep the out-diffusion of the buried layer zones 3 low in the case of step-down NPN transistors by using slowly diffusing atoms such as arsenic or antimony. An additional buried layer zone 4, which is additionally applied to this buried layer zone 3 exclusively in the area of the I²L inverter, and is made of a rapidly diffusing dopant such as B. phosphorus, reduces the effective distance between the buried layer zone 3 and the base and thus increases the emitter efficiency in upward operation.

The problems with this method are due to the tolerances when growing up an epitaxial layer on the wafer, which increases with increasing Increase epitaxial thickness. Too large epitaxial base distances reduce the On the other hand, increase the upward current gain and increase the epitaxy base spacing that is too small the barrier layer capacity or even lead to diffusion through. It is also for the concentration of the additional buried layer sets an upper limit because otherwise stack errors occur.

A reduced base width of the I²L bases with an additional buried layer zone 4 in the area of the I²L gates means that the problems listed in both individual measures are greatly reduced. In terms of manufacturing technology, the process is also suitable for series production.

In a process that ensures, for example, a blocking voltage of the high-voltage NPN transistors of at least 30 volts, typical values of 40 kΩ / square for the internal base path resistance of the I²L NPN transistor have been determined using a flat base alone. Due to manufacturing tolerances, this parameter fluctuates from 20 kΩ to 120 k, which leads to the failures mentioned above. The bandwidth of the inner baseline resistance of the high-voltage NPN transistor was determined to be 3 kΩ to 6 kΩ. By moving in the additional Buried Layer Zone 4 , the inner base path resistance of the I²L-NPN transistor can be reduced to 7 kΩ to 18 kΩ at typically 10 kΩ, which enables safe production without failures.

An additional buried layer zone alone, for example, would have to be implanted with a dose of at least 2 _* 10¹⁵ / cm². At this dose, stacking errors can occur, and the vertical extent of this zone is so large that it can diffuse into the base zone. With the additional use of the flat base zone in the I²L NPN transistor, the dose can be reduced to 5 _* 10¹⁴ / cm², which also increases the process reliability here.

Fig. 11 shows the doping profile of an exemplary semiconductor device without the emitter diffusion. The distance from the substrate in the epitaxial layer is plotted on the ordinate axis, and the concentration of the respective dopant is plotted on the abscissa axis. The curve labeled A shows the course of the dopant of the I²L base zone 9 , the curve labeled B shows the course of the dopant of the base zone 8 of the NPN transistors or the base connection zone 8 'and the injector zone 8 '', which was labeled C. Curve the course of the dopant of the additional buried layer zones 4 and the curve labeled D the course of the dopant of the buried layer zones 3 .

A method for producing an integrated semiconductor arrangement with I²L logic inverters in combination with high-blocking NPN transistors is explained below with reference to FIGS . 4 to 10.

The following is with masking and photolithography or with Masking with the creation of a suitable masking layer corresponding structures on the surface of the semiconductor to be processed meant. These process steps are generally known and can be one A multitude of individual process steps such as the generation of a Oxide layer, spinning a photoresist layer, exposing the Include photoresists etc. but are not limited to them.

On a P-type semiconductor substrate 1, the buried layer zones 3 are doped with a first, slowly diffusing N-type dopant by the usual methods of masking and photolithography by impurity diffusion. Arsenic As and Antimony Sb are suitable for this. The Buried Layer Zones 3 are then healed using a thermal process. The impurity diffusion takes place through openings in a first oxide layer 12 a. A cross section through the semiconductor arrangement after these method steps is shown in FIG. 4.

A second P-type dopant for the buried separation zones 5 is then introduced into the semiconductor substrate 1 by the usual methods of masking and photolithography by impurity implantation. A photoresist layer 13 a provided with window openings usually serves as masking. A cross section through the semiconductor arrangement after these method steps is shown in FIG. 5.

After a further masking and photolithography step, the impurity implantation for the additional buried layer zones 4 is carried out using a third, rapidly diffusing N-type dopant. A suitable dopant is phosphorus P. The implantation is carried out through the window openings in one serving as a mask photoresist layer 13 b. A cross section through the semiconductor arrangement after these method steps is shown in FIG. 6.

The buried separation zones and the additional buried layer zones are healed together in a thermal process. The order of the Creation of the buried separation zones and the additional buried layers Zones are therefore interchangeable.

A monocrystalline semiconductor layer 2 is then generated by the N type on the semiconductor substrate 1 by epitaxial waking. The following processes ensure that the buried layers, ie the buried separation zones 5 and the buried layer zones 3 , 4 diffuse out into the epitaxial semiconductor layer 2 . The epitaxial growth usually takes place at temperatures such that the buried layers diffuse out at the same time. A cross section through the semiconductor arrangement after these method steps is shown in FIG. 7.

By conventional methods of masking, photolithography and impurity implantation or pre-assignment with subsequent re-diffusion (drive in), p⁺-doped separation zones 6 are produced in accordance with the buried separation zones 5 with a fourth dopant of the P type in the epitaxial layer. A cross section through the semiconductor arrangement after these method steps is shown in FIG. 8.

After a further masking and photolithography process step, the n⁺-deep connection zones 7 are defined by pre-coating with a fifth dopant of the N type and subsequent subsequent diffusion in the epitaxial layer. An oxide layer 12 b serves as a mask. The n⁺-deep connection zones 7 extend from the surface of the epitaxial layer to the buried layer zones 3 or additional buried layer zones 4 .

By masking and photolithography, the zones of the NPN base 8 , the I²L base connection 8 ', the I²L injector 8 ''and the I²L base 9 are defined as window openings in a first auxiliary layer 12 c, usually made of silicon dioxide. Then the zones of the I²L base are covered by a second auxiliary layer 13 c, usually photoresist. A first impurity implantation of the base zones 8 , 8 ', 8 ''follows with a sixth dopant of the P type. The zones of the NPN base 8 , the connection region of the I²L base 8 'and the I²L injector 8 ''which are not covered by the photoresist are doped. A cross section through the semiconductor arrangement after these method steps is shown in FIG. 9.

After removal of the second auxiliary layer 13 c above the I²L base 9 , a second impurity implantation is carried out, in which all the zones specified above are now doped with a seventh P-type dopant. Thus, the dose of those zones that were exposed to the impurity implantation is larger. A cross section through the semiconductor arrangement after these method steps is shown in FIG. 10.

In a further process step, the collectors of the I²L logic inverters and the emitters and collectors of the NPN transistors by masking, Photolithography and impurity implantation with an eighth dopant from N type generated.

The method steps known per se for defining the metallization levels 14 and for passivation 12 follow. The complete semiconductor arrangement is shown in cross section in FIG. 1.

Claims (7)

1. Method for producing an integrated semiconductor arrangement with I²L logic inverters in combination with high-blocking NPN transistors with the following process steps, which proceed in the order given:

• a) providing a P-type semiconductor substrate;
• b) masking and introduction of impurities for buried layer zones by a first, slowly diffusing dopant of the N type;
• c) healing of the buried layer zones;
• d) masking and introduction of impurities for buried separation zones by a second dopant of the P type,
• e) masking and introducing impurities for additional buried layer zones by means of a third, rapidly diffusing dopant of the N type;
• f) healing of the buried separation zones and the additional buried layer zones;
• g) epitaxially waking up an N-type single crystal semiconductor layer;
• h) masking and introduction of impurities for the p⁺ separation zones in accordance with the buried separation zones by a fourth dopant of the P type;
• i) masking and introduction of impurities for the n⁺-deep connection zones by a fifth dopant of the N type;
• j) masking the NPN base region (8), the I²L base terminal zone (8 '), the I²L- injector (8' ') and the I²L base region (9) with a first auxiliary layer (12 c);
• k) covering the I²L base ( 9 ) with a second auxiliary layer ( 13 c);
• l) introduction of first impurities in the base zones ( 8 , 8 ', 8 '') and at the same time introduction of first impurities in the I²L base ( 9 ) by a sixth dopant of the P type;
• m ′) removing the second auxiliary layer ( 13 c);
• m) introduction of second impurities in the base zones ( 8 , 8 ', 8 '') by a seventh dopant of the P type;
• n) Masking and introducing impurities for the collectors of the I²L logic inverters ( 11 ) and the emitters ( 10 b) and collectors ( 10 a) of the NPN transistors by an eighth dopant of the N type.

2. The method according to claim 1, characterized by exchanging the Process steps d) and e). 3. The method according to claim 1 or 2, characterized by the common healing of the I²L base ( 9 ) and the base zones ( 8 , 8 ', 8 ''). 4. The method according to any one of claims 1 to 3, characterized in that the first dopant from the group consisting of arsenic and antimony is selected. 5. The method according to any one of claims 1 to 4, characterized in that used as second, fourth, sixth and seventh dopant boron becomes. 6. The method according to any one of claims 1 to 5, characterized in that phosphorus is used as the third, fifth and eighth dopant. 7. The method according to any one of claims 1 to 6, characterized in that after step m) after a further masking Introducing impurities for high-resistance resistors Boron is implanted.