DE1789111B2 - METHOD OF TESTING INSULATING LAYERS ON THE SURFACE OF SEMICONDUCTOR ARRANGEMENTS - Google Patents
METHOD OF TESTING INSULATING LAYERS ON THE SURFACE OF SEMICONDUCTOR ARRANGEMENTSInfo
- Publication number
- DE1789111B2 DE1789111B2 DE19671789111 DE1789111A DE1789111B2 DE 1789111 B2 DE1789111 B2 DE 1789111B2 DE 19671789111 DE19671789111 DE 19671789111 DE 1789111 A DE1789111 A DE 1789111A DE 1789111 B2 DE1789111 B2 DE 1789111B2
- Authority
- DE
- Germany
- Prior art keywords
- insulating layers
- semiconductor arrangements
- testing insulating
- testing
- arrangements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6303366 | 1966-09-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE1789111A1 DE1789111A1 (en) | 1972-03-09 |
| DE1789111B2 true DE1789111B2 (en) | 1972-10-05 |
Family
ID=13217594
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19671789111 Pending DE1789111B2 (en) | 1966-09-26 | 1967-09-21 | METHOD OF TESTING INSULATING LAYERS ON THE SURFACE OF SEMICONDUCTOR ARRANGEMENTS |
| DE19671589901 Withdrawn DE1589901B2 (en) | 1966-09-26 | 1967-09-21 | PROCESS FOR IMPROVING AND STABILIZING THE ELECTRICAL PROPERTIES OF A SEMICONDUCTOR ARRANGEMENT WITH AN INSULATING PROTECTIVE LAYER |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19671589901 Withdrawn DE1589901B2 (en) | 1966-09-26 | 1967-09-21 | PROCESS FOR IMPROVING AND STABILIZING THE ELECTRICAL PROPERTIES OF A SEMICONDUCTOR ARRANGEMENT WITH AN INSULATING PROTECTIVE LAYER |
Country Status (1)
| Country | Link |
|---|---|
| DE (2) | DE1789111B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5627935A (en) * | 1979-08-15 | 1981-03-18 | Toshiba Corp | Semiconductor device |
| JP2934456B2 (en) * | 1989-07-14 | 1999-08-16 | 株式会社日立製作所 | Surface treatment method and apparatus |
-
1967
- 1967-09-21 DE DE19671789111 patent/DE1789111B2/en active Pending
- 1967-09-21 DE DE19671589901 patent/DE1589901B2/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| DE1589901B2 (en) | 1972-02-17 |
| DE1789111A1 (en) | 1972-03-09 |
| DE1589901A1 (en) | 1970-10-22 |
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