DE10227605A1 - Layer system and production process especially for drams uses a substrate with two opposite processed surfaces and attaches a second substrate to one of these - Google Patents

Abstract

A layer system comprises a substrate having a surface processed with a conductive metal structure and an opposite processed second surface. A second substrate is attached by a third surface to the first surface of the first substrate. An independent claim is also included for a process for producing the system above.

Description

The invention relates to a layer arrangement and a method for producing a layer arrangement.

With advancing miniaturization of semiconductor devices be for Memory cell arrangements such as DRAM (dynamic random access memory, dynamic semiconductor memory) or flash memory (using a floating gate layer in which electrical charge carriers can be introduced tightly packed arrangements are required.

In particular, an arrangement with Vertical transistors advantageous because in this case the length of the Channel area that is for many planar storage arrangements cannot be reduced arbitrarily, is moved to the vertical dimension. This can make the critical Dimension, namely the length that of extending substantially perpendicularly into the substrate Channel area without loss of area on the surface of the substrate is sufficiently large become. To achieve a high surface density of memory cells can they Dimensions of the memory cell on the surface of the substrate at one Vertical transistor continues to be reduced without disruptive short channel effects occur.

For contacting and control a memory cell arrangement with densely packed arrangements of vertical transistors are buried Word or bit lines required.

Buried bit lines are the technology made of doped silicon or silicides, that is, silicon-metal alloys. This makes it well compatible with front-end processing allows however, these materials are high-resistance, which leads to undesired signal attenuation Consequence. In addition, high demands are made in some cases the process technology for forming such bit lines.

Buried pipes made of a metallic In many cases, materials that are significantly lower in resistance are not compatible with another frontend processing.

In [1] is a cell field with vertical Transistors described, the transistors directly above a bit line can be manufactured. This is the ohmic resistance the bit line is comparatively high. According to that described in [1] Method, the buried lines are doped using a diffusion process. In other words, a thin single crystal semiconductor layer made of silicon on a single-crystalline silicon substrate and electrical conductivity the epitaxially grown layer by means of doping with doping atoms elevated. Subsequently are over layers of the epitaxially grown layer, so that a buried pipe is obtained.

Furthermore, in [1] it is proposed to increase the electrical conductivity of the buried bit line by epitaxially growing cobalt silicide (CoSi ₂ ).

However, the known from [1] Process the disadvantage of being an epitaxially grown Layer as buried pipe to the one formed above and below Layer usually Dislocations, which leads to problems with the mechanical and electrical stability the layer arrangement to lead can.

An endowed epitaxially grown up Silicon layer also has a relatively high electrical resistance, causing a lot of waste heat arises, and thereby electrical signals as they pass through the buried Steamed line become.

To avoid parasitic signal attenuation and unwanted waste heat, would be a buried line of an integrated circuit advantageous, which has a reduced ohmic conductivity. For this would have to be in a substrate first the lower metallic connections are made be before the temperature-intensive process steps in upper Layers of the substrate performed (e.g. forming a gate insulating layer by means of thermal oxidation). Because such processing metallic structures often in such a case, the lower electrical Line are not formed from a metallic material, but at most made of comparatively high-resistance silicide material become.

In the ELTRAN ^® process known from [2], a delamination layer made of porous silicon is mechanically detached by using a water jet to separate the silicon substrate on the porous silicon layer into two sub-substrates.

Out [ 3] the so-called Smart-Cut ^® process is known, in which a hydrogen-containing delamination layer is formed in a substrate, which can be removed or delaminated by means of tempering.

The invention is based on the problem, a to provide electrical conduction in a substrate, the one has reduced ohmic resistance and that with acceptable Effort can be made.

The problem is caused by a layer arrangement and by a method for producing a layer arrangement with solved the features according to the independent claims.

The layer arrangement according to the invention contains a first substrate that has a first processed surface area on a first main surface that contains a metallically conductive structure. Furthermore, the first substrate contains a second processed surface area on a second main surface opposite the first main surface. A second substrate of the layer arrangement with a third main surface is attached to the first main surface of the first substrate.

In the method according to the invention for producing a layer arrangement is in a first substrate a first surface area on a first main surface processed, whereby a metallically conductive structure is formed. Further becomes a second surface area in the first substrate on an opposite side of the first main surface second main surface processed. A third major surface of a second substrate is on the first main surface attached to the first substrate.

A basic idea of the invention exists vividly therein, using the technique of wafer bonding a metallic conductive to produce buried line, for example for a memory cell array.

For this there is a first surface area on a first main surface processed a first substrate such that a metallic conductive Structure is formed that, for example, as a metallic word or bit line can be used. Becomes a second substrate on the first main surface of the first substrate by means of wafer bonding, one of the first main surface opposing second main surface of the first substrate are processed. Due to the bonding of the second substrate on the first substrate is a metallic conductive structure created.

One generated by means of wafer bonding buried pipe can be made of a metallic conductive and therefore significantly lower-impedance material are formed than this is the case with the methods known from the prior art is.

In the technique of wafer bonding two wafers are brought into contact with each other and using different methods permanently attached to each other. The Wafer bonding can be used, for example, to manufacture a silicon-on-insulator wafer (SOI wafer) can be used. There is also the possibility the technique of wafer bonding within the manufacturing process of an integrated circuit to use.

It is clearly possible according to the invention after a front end processing the back of an integrated To make the component accessible in terms of process technology. this will exploited according to the invention, in order for a frontend processing (including the formation of metallic connections for the upper contacts) Expose underside of the wafer and, for example, also with metallic contacts.

Preferred developments of the invention result themselves from the dependent Claims.

The metallic conductive structure can have a metallic material or a metallic material Material like tungsten exist.

The metallic conductive structure can have at least one word line and / or at least one bit line have at least one memory cell integrated in the layer arrangement. The memory cell can, for example, be a DRAM memory cell (dynamic random access memory) or a flash memory cell with a floating gate memory.

The first and / or the second processed surface area can have at least one integrated component.

That is at least one integrated component preferably coupled to the metallic conductive structure.

At least one integrated component can a vertical transistor his. Vertical memory transistors coupled with metallic word or bit lines enable a low-resistance contact and simultaneously a memory cell arrangement with one high integration density.

In the layer arrangement according to the invention the first and the second processed surface area is preferably such processes that the at least one integrated component on one lower end section by means of the first processed surface area is electrically connected and by means of an upper end portion of the second processed surface area electrically connected.

Between the metallic conductive structure and the at least one integrated component is preferably one electrically switchable layer is provided as a storage layer. A electrically switchable layer is a layer made of such a layer Material that by applying a suitable configuration stream or a suitable configuration voltage the ohmic resistance of the electrically switchable layer can be set permanently. Therefore, in an electrically switchable layer, strictly speaking information is stored in the value of their ohmic resistance become.

The electrically switchable layer can, for example, be a molecular layer (e.g. rotaxane, catenane, a bispyridinium compound), a dielectric (e.g. SrZrO ₃ ) or a polymer (e.g. 3-nitrobenzal malonitrile, 1,4 phenylenediamine complex, Chalcogenide compound).

The layer arrangement can be set up as an NROM memory cell arrangement (NROM, “nitrided read only memory”). In other words, at least one NROM memory cell can be integrated in the layer arrangement according to the invention be grated.

Furthermore, the method according to the invention described for producing a layer arrangement. refinements the layer arrangement also apply to the method of manufacturing one Layer arrangement.

Before processing the second surface area may material of the first substrate from an opposite side of the first main surface surface of the first substrate are removed.

The material can be removed by the first substrate on a contained therein, by means of thermal or removable mechanical treatment Delamination layer is divided into two sub-substrates.

In particular, a mechanically removable delamination layer according to the ELTRAN ^® method known from [2] or a thermally removable hydrogen-containing delamination layer known from [3], according to the Smart-Cut ^® method, can be used as the delamination layer.

This makes it vividly possible, while avoiding it one elaborate chemically removing material of the first substrate from the first substrate to thin to expose a layer for further processing.

In the process, the third main surface of the second substrate on the first main surface of the first substrate Wafer bonding are attached.

An SOI substrate can be used as the substrate (Silicon-on-Insulator) can be used.

Embodiments of the invention are shown in the figures and are explained in more detail below.

Show it:

1A to 1E Layer sequences at different times during a method for producing a layer arrangement according to a first exemplary embodiment of the invention,

2A to 2G Layer sequences at different times during a method for producing a layer arrangement according to a second exemplary embodiment of the invention,

3A to 3F Layer sequences at different times during a method for producing a layer arrangement according to a third exemplary embodiment of the invention,

4A to 4F Layer sequences at different times during a method for producing a layer arrangement according to a fourth exemplary embodiment of the invention,

5A . 5B Layer sequences at different times during a method for forming a layer arrangement according to a fifth exemplary embodiment of the invention.

The following will refer to 1A to 1E a method for producing a layer arrangement according to a first embodiment of the invention is described.

To do that in 1A shown silicon substrate 100 to get a removable delamination layer 101 into the silicon substrate using the ELTRAN ^® process described in [2] 101 brought in. The removable layer 101 represents a porous silicon layer by treating the delamination layer 101 can be detached with a water jet. By means of the removable delamination layer 101 is the silicon substrate 100 in a first silicon layer 102 and in a second silicon layer 103 divided up.

To the in 1B layer sequence shown 110 is obtained in a surface area of the first silicon layer 102 the substrate 100 on a first main surface 111 subjected to processing such that a buried metallic wire 112 is formed from tungsten.

To the in 1C layer sequence shown 120 to get another silicon substrate 121 on the first main surface 111 the layer sequence 110 attached by means of wafer bonding.

In the wafer bond process, the two substrates 100 . 121 pressed against each other by means of mechanical pressure. As a result of van der Waals forces, the two wafers assume weak adhesion, which can be converted into a mechanically strong connection by means of anodic bonding or by means of tempering. In anodic bonding, an electrical voltage is applied to the wafers and the wafers are heated.

To the in 1D layer sequence shown 130 to get the layer sequence 120 exposed to a water jet, causing the removable delamination layer 101 the first substrate made of porous silicon material 100 is divided into two halves. The second silicon layer 103 removed, leaving a second main surface 131 the layer sequence 130 is exposed.

To the in 1E layer arrangement shown 140 to get a surface area 141 near the second main surface 131 Processed using semiconductor technology. Semiconductor technology processing means in particular that, for example, electrical components are formed.

The layer arrangement 140 contains a low-resistance buried tungsten layer 112 ,

The following will refer to 2A to 2G a method for producing a layer arrangement according to a second embodiment of the invention is described.

An in 2A shown SOI wafer 200 (Silicon-on-Insulator) uses a silicon carrier layer 201 , one on the silicon carrier layer 201 trained first silicon oxide layer 202 and one on the first silicon oxide layer 202 trained first silicon layer 203 having.

To the in 2 B layer sequence shown 210 to obtain is first a surface area of the first silicon layer 203 doped with n ⁺ doping atoms (e.g. arsenic) using an ion implantation method. Trenches are also made using a lithography and an etching process 216 into the silicon layer 203 etched. The silicon sidewalls of the trenches are thermally oxidized by means of thermal oxidation, as a result of which two gate-insulating layers on the two sidewalls of each trench 211 a transistor arrangement formed in the further. Furthermore, polysilicon material is placed on the gate insulating layers 211 deposited, creating gate areas 215 are formed. Furthermore, adjacent polysilicon structures are isolated from one another as later gate regions by the trenches with silicon oxide material 212 be replenished. As in 2 B shown, the remaining n ⁺ -doped regions each form a first source / drain region 213 of a later field-effect transistor. Furthermore, the remaining material forms the first silicon layer 203 Channel regions 214 the later field-effect transistors.

To the in 2C layer sequence shown 220 will get on top of the layer sequence 210 first an electrically switchable layer 221 deposited from a bispyridinium compound. Furthermore, on the electrically switchable layer 221 a common metallic electrode 222 deposited. layers 221 . 222 are deposited by depositing a second silicon oxide layer 223 encapsulated.

The electrically switchable layer 221 between the first source / drain regions 213 on the one hand and the common metallic electrode 222 on the other hand is made of such a material that the electrical resistance of the electrically switchable layer 221 can be changed under the influence of a configuration voltage or a configuration current. The electrical property "ohmic resistance" of the layer is set by the action of a configuration current or a configuration voltage, so that the setting can be queried in a reading step. The value of the local electrical conductivity of the electrically switchable layer is clear 221 the memory information is encoded in a surrounding area of one of the field effect transistors.

To the in 2D layer sequence shown 230 to get another silicon wafer 231 on the second silicon oxide layer 223 the layer sequence 220 attached using a wafer bonding method.

To the in 2E layer sequence shown 240 to get it according to 2D below the first silicon oxide layer 202 located silicon material of the silicon carrier layer 201 chemically removed. Furthermore, using a lithography and an etching process, the first silicon oxide layer 202 structured so that contact holes 241 remain behind, by means of which silicon material of the channel areas 214 is exposed.

To the in 2F memory cell arrangement shown 250 To obtain as a layer arrangement according to a second exemplary embodiment of the invention, a second source / drain region is obtained using an ion implantation method 251 in each of the vertical transistors in a near-surface area of the channel area 214 educated. Furthermore, the contact holes 241 filled with metallic tungsten material, creating the second source / drain regions 251 of the transistors are electrically contacted. In a further method step, the surface of the layer sequence thus obtained is planarized using a CMP method (chemical mechanical polishing). Using a lithography and an etching process, the deposited metallic material is structured in such a way that metallic bit lines are thereby 252 a matrix-like arrangement of memory cells can be formed. The structuring of the bit line 252 is preferably carried out by means of photostructuring. The layer sequence obtained in this way is obtained by depositing a third silicon oxide layer 253 encapsulated.

The following will refer to 2G is a schematic spatial view of the in 2F memory cell arrangement shown 250 described, wherein in 2G only part of the components 2F is shown.

In particular, the schematic spatial view 260 a first memory cell 261 and a second memory cell 262 shown. For both memory cells 261 . 262 the electrically switchable layer is jointly provided 221 and the common metallic electrode 222 that with the first source / drain regions 213 of the memory cells 261 . 262 are coupled. The first source / drain areas 213 and the second source / drain regions 251 are each provided as n ⁺ doped regions, whereas that between the source / drain regions 213 . 251 arranged channel area 214 is p-doped. Laterally to the vertical layer sequence from the first source / drain area 213 , Channel area 214 and second source / drain area 251 adjacent is the vertically extending gate insulating layer 211 arranged by means of which the channel area 214 from the gate area partially surrounding it 215 is electrically decoupled. The gate areas are clearly illustrated 215 the word line of the memory cell arrangement 260 , The second source / drain connection 251 each memory cell 261 . 262 is with the metallic bit line 252 coupled. The memory content of the memory cells 261 . 262 is the value of the adjustable electrical resistance of that range the electrically switchable layer 221 included, which is adjacent to the respective memory cell. By applying a suitable electrical potential to the gate areas 215 a respective memory transistor can be brought into an electrically conductive state, so that an electrical current flow from the bit line 252 through the channel area 214 down to the common electrode 222 is made possible, the value of the electric current from the ohmic resistance of the electrically switchable layer 221 depends in the directly adjacent area of the respective memory transistor. The source / drain areas 213 . 251 are from the gate area 215 electrically decoupled.

In summary, with the memory cell arrangement 260 A highly integrated electronic read-only memory is created, which has a metallic bit line 252 and a buried metallic pipe 222 having.

The following will refer to 3A to 3F describes a method for producing a layer arrangement according to a third exemplary embodiment of the invention.

The in 2A SOI wafer shown 200 used.

To the in 3A layer sequence shown 300 to get the SOI wafer 200 patterned using a lithography and an etching process such that the first silicon oxide layer 202 and the first silicon layer 203 each in a plurality of silicon areas 301 and silicon oxide regions arranged underneath 302 be structured. As in 3A shown are those between adjacent silicon oxide regions 302 emerging trenches 304 partially filled with silicon nitride material, creating silicon nitride areas 303 be formed. For this purpose, silicon nitride material is deposited on the surface of the structured layer sequence and planarized using a CMP process (chemical mechanical polishing). Furthermore, silicon nitride material is selectively etched back to trenches 304 above the silicon nitride areas 303 train.

To the in 3B layer sequence shown 310 are first obtained using an ion implantation method using n ⁺ doping atoms (e.g. arsenic) in a surface area of the layer sequence 300 implanted in such a way that in the near-surface sections of the silicon areas 301 first source / drain regions 311 are formed. The essentially undoped silicon material of the silicon areas remote from the surface 301 forms the channel areas 312 of vertical transistors to be trained further. Furthermore, the layer sequence obtained is thermally oxidized, as a result of which on the side walls of the silicon stack from first source / drain regions 311 and channel areas 312 one gate insulating layer each 313 is trained. Furthermore, on the gate insulating layers 313 laterally deposited polysilicon material, creating gate areas 314 be formed. The remaining trenches are filled with silicon oxide material, which creates silicon oxide spacers 315 be formed.

To the in 3C layer sequence shown 320 will get on top of the layer sequence 310 first an electrically switchable layer 321 made of a bispyridinium compound, then a common metallic electrode 322 made of tungsten material and finally a silicon oxide layer 323 to encapsulate the layers 321 . 322 deposited.

To the in 3D layer sequence shown 330 to get another silicon wafer 331 on the silicon oxide layer 323 attached using a wafer bonding process.

To the in 3E layer sequence shown 340 to get the silicon backing 201 the layer sequence 330 removed by mechanical grinding. Furthermore, the silicon oxide areas 302 removed using a selective etching process, the etching process being selected such that during the etching of the silicon oxide regions 302 the silicon nitride areas 303 remain. This will make surface areas of the channel area 312 exposed. Furthermore, silicon oxide spacers 341 on the side walls of the trenches between adjacent silicon nitride regions 303 educated.

To the in 3F layer sequence shown 350 to get the layer sequence 340 subjected to an ion implantation process, whereby n ⁺ doping atoms (for example arsenic) into an exposed surface region of the channel regions 314 be introduced. This creates second source / drain areas 351 educated. Furthermore, by depositing tungsten material, that of the silicon oxide spacers 341 and the second source / drain regions 351 delimited contact holes are filled in a self-adjusting manner. Furthermore, using a CMP method, the tungsten material by means of which the second source / drain regions 351 the transistors are coupled together, planarized. The tungsten layer becomes the paper plane from 3F structured orthogonal plane, creating a metallic bit line 352 is trained. Furthermore, the metallic bit line 352 with another silicon oxide layer 353 covered and thereby encapsulated.

This makes the memory cell arrangement 350 created as a layer arrangement according to a third embodiment of the invention. This has the same functionality as that in 2F . 2G memory cell arrangement shown 250 . 260 ,

It should be noted that referring to 2A to 2G . 3A to 3F described manufacturing process, the removal of the silicon carrier layer 201 after wafer bonding has been carried out by means of chemical or mechanical removal of the silicon material. Alternatively, the detachment can, for example, under The use of a detachable delamination layer made of porous silicon can be realized using the ELTRAN ^® process, which is described in [2].

The following will refer to 4A to 4F a method for producing a layer arrangement according to a fourth embodiment of the invention is described.

To the in 4A layer sequence shown 400 an SOI wafer as used in

2A is shown. This contains a silicon carrier layer 201 , a silicon oxide layer arranged thereon 202 and a silicon layer arranged thereon 203 , The silicon layer 203 is considerably thinner than the silicon carrier layer 201 , d. H. the representations of 4A to 4F are not to scale. The thickness of the silicon layer 203 is preferably approximately 40 nm, whereas the thickness of the silicon carrier layer 201 is in the millimeter range. The p-doped silicon layer 203 is subjected to an ion implantation process, whereby an n ⁺ -doped layer as first source / drain regions in a surface region 401 is formed by transistors to be formed further. The remaining p-doped material of the silicon layer 203 serves as a channel area 402 , In a further process step, a first silicon nitride layer 403 deposited as a trench hard mask. Furthermore, the layer sequence obtained in this way is subjected to a lithography and an etching process, as a result of which trenches are etched into the layer sequence. For this purpose, material is the first silicon nitride layer 403 , the first silicon layer 203 and the first silicon oxide layer 202 away. The silicon material of the silicon carrier layer 201 serves as a stop layer for the etching. In the trenches formed in this way there is an ONO layer sequence 404 educated. The ONO layer sequence 404 consists of a silicon nitride layer, which is surrounded on both sides by a thin silicon oxide coating. In a further process step, the ONO layer sequence formed in the trenches 404 Polysilicon material as gate areas 405 deposited. Part of the deposited polysilicon material is removed using a chemical mechanical polishing (CMP) process to generate a planar surface, the first silicon nitride layer 403 is used as a stop layer. Furthermore, a recess is formed in the trenches by etching back further polysilicon material in a defined manner. As an alternative to the method described, the CMP method step and the subsequent etching of polysilicon can be combined to form a common etching method step. The recesses formed in the trenches, which are partially filled with polysilicon material, are filled by depositing silicon oxide material, which material uses a CMP process to form silicon oxide structures 406 is etched back, the first silicon nitride layer 403 serves as a stop layer. As an alternative to the silicon oxide deposition and the subsequent CMP process, polysilicon material of the gate region can be used 405 be thermally oxidized to form a silicon oxide surface layer that has the silicon oxide structures 406 is similar.

To the in 4B layer sequence shown 410 to get a second silicon nitride layer 411 on the surface of the layer sequence 400 deposited. Furthermore, a second silicon oxide layer 412 on the second silicon nitride layer 411 deposited. A CVD process ("chemical vapor deposition"), for example, is used for these deposition steps.

The following will refer to 4C . 4D described how a bit line of the memory cell arrangement to be formed is formed. For this the layer sequence is perpendicular to the paper plane of 4B processed. In 4C . 4D Section views of the layer sequence processed according to the following method are shown in two mutually parallel planes, both parallel to the paper plane. In 4C a first sectional view of the layer sequence extended in a direction orthogonal to the paper plane is shown, a section between two bit lines being shown. In 4D shows a section through a bit line, so that the in 4C and 4D Layer sequences shown are sectional views through the in a direction perpendicular to the paper plane of 4C . 4D trained layer sequence are parallel to each other, but along a direction perpendicular to the paper plane of 4C . 4D are offset from each other.

Furthermore, referring to the first sectional view 420 out 4C or the second sectional view 430 out 4D described how a metallic bit line is formed.

For this purpose, the silicon nitride layer 411 containing, to the paper plane of 4B orthogonal level, a lithography and an etching process is carried out, which defines the spatial course of the bit lines. Corresponding to the structuring of a photoresist layer on the surface of the layer sequence 410 (not shown) first becomes the second silicon oxide layer 412 , then the second silicon nitride layer 411 and finally the first silicon layer 203 structured, the first silicon oxide layer 202 is used as a stop layer. The trenches created in this way are made with TEOS silicon oxide 421 filled up (TEOS = tetra-ethyl-orthosilicate). After removing the photoresist, the layer sequence is subjected to a CMP process, as a result of which silicon oxide material and the second silicon nitride layer are removed 411 serves as a stop layer. Furthermore, material of the second silicon nitride layer 411 under Removed using an etching process. A titanium / titanium nitride barrier (not shown) is then deposited to prepare for subsequent deposition of tungsten material. Subsequently, tungsten material is deposited using sputtering. The layer sequence obtained in this way is planarized using a CMP method, silicon oxide being used as the stop layer. This will make a tungsten bit line 431 educated. Furthermore, on the tungsten bit line 431 optionally other TEOS silicon oxide material can be deposited, which is advantageous for a subsequent wafer bond process step.

In 4E is a spatial view of a layer sequence 440 shown how it is obtained according to the processing described below.

To the in 4E layer sequence shown 440 to get the according to 4C . 4D top surface of the layer sequence 420 . 430 using a wafer bonding process with another wafer 441 from another silicon substrate 442 and a third silicon oxide layer formed thereon 443 attached. Furthermore, the silicon carrier layer 201 removed by etching, the first silicon oxide layer 202 serves as a stop layer. Furthermore, using a fixed time etch, the first silicon oxide layer 202 removed, causing the channel area 402 is exposed. A second source / drain region is created by implanting doping atoms of the n-conductivity type (e.g. arsenic) 444 designed as an n ⁺ -doped region.

To the in 4F memory cell arrangement shown 450 (optional) silicon oxide spacers 451 on the exposed side walls of the ONO layer sequence 404 is formed, thereby reducing the word line-bit line capacitance. A titanium-titanium nitride barrier layer is also formed (not shown) to prepare for subsequent deposition of tungsten material. Subsequently, tungsten material is deposited and planarized using a CMP process with silicon nitride material as a stop layer. This makes tungsten conductor tracks 452 educated.

The thus obtained, in 4F Memory cell order shown 450 as a layer arrangement according to a fourth exemplary embodiment of the invention acts as a NROM ("nitrided read only memory") flash memory with an effective cell area per bit of 1F ² , where F is the minimum structural dimension that can be achieved with a technology generation. In the case of a NROM memory, the information to be stored is tunneled into the ONO layer sequence by hot electrons 404 saved, reducing the electrical conductivity of the channel area 402 is influenced characteristically. The value of the electrical current between the source / drain connections 444 . 401 then depends on the amount and sign of in the ONO layer sequence 404 injected or non-injected charge carriers, since this is the conductivity of the channel area 402 characteristically influence.

This shows the current between the bit lines 431 and the tungsten conductor track 452 depending on the charge state of the silicon nitride layer of the ONO layer sequence 404 ,

The following will refer to 5A . 5B a method for producing a layer arrangement according to a fifth embodiment of the invention is described.

First, the processing takes place as referring to 4A described with the difference that before the formation of the ONO layer sequence 404 only the first silicon nitride layer 403 and the first silicon layer 203 are etched, whereas by etching the first silicon oxide layer 202 is disregarded.

Optionally, silicon nitride material (not shown) in the trenches formed to be deposited as this is at a later step in the process a better defined etch stop allows than just an ONO layer sequence alone. In this case it is additional so-called recess etching required, d. H. the ditch will first filled with silicon nitride material and then again partially exposed.

Below is an ONO layer sequence 404 formed in the trenches, and polysilicon material is filled thereon as the gate region. The layer sequence obtained in this way is planarized using a CMP method, the first silicon nitride layer 403 serves as a stop layer. Furthermore, similar to the case of 4A a surface area is removed from the trench completely filled with poly-silicon material by means of an etching process. The resulting recess is made with silicon oxide material to form silicon oxide structures 406 refilled. The layer sequence thus obtained is then planarized with the removal of silicon oxide material by means of a CMP method, the first silicon nitride layer 403 serves as a stop layer. As an alternative to the two process steps described last, the polysilicon material contained in the trench can in turn be thermally oxidized.

This creates a layer sequence similar to that in 4A get shown.

In a further process step, the first silicon nitride layer 403 removed by etching, the first source / drain region 401 made of silicon material serves as a stop layer. Silicon oxide spacers can optionally be formed to reduce word line-bit line capacitance (not shown). Furthermore, a titanium / titanium nitride barrier is applied as a barrier layer for a tungsten layer that is subsequently applied. Subsequently, tungsten material is deposited by sputtering and using a CMP process planarized, using silicon oxide material as a stop layer. This will cause the in 5A layer sequence shown 500 obtained with such components, which are also in the layer sequence 400 are included, are provided with the same reference numbers. In particular, is a tungsten structure 501 shown with the silicon oxide structures 406 has a common surface.

In order to be able to better carry out a subsequent wafer bond process step, TEOS silicon oxide material is used 511 on the surface of the layer sequence 500 deposited (cf. memory cell arrangement 510 in 5B ).

In a further process step, an in 5B shown other silicon wafer 512 from a silicon substrate 513 and a fourth silicon oxide layer formed thereon 514 by means of wafer bonding to the TEOS silicon oxide structure 511 the layer sequence 500 attached. Furthermore, the silicon carrier layer 201 chemically removed, the first silicon oxide layer 202 serves as a stop layer. Furthermore, the first silicon oxide layer 202 etched with the channel area 402 made of silicon or the ONO layer sequence 404 serve as a stop layer. Subsequently, using an ion implantation method, n ⁺ doping atoms are placed in an exposed surface area of the channel area 402 introduced, creating a second source / drain region 515 is trained.

A silicon oxide auxiliary layer and a silicon nitride auxiliary layer are subsequently deposited on the surface of the layer sequence. Furthermore, the area in which the bit line is later formed is determined using a lithography method. In the surface regions of the layer sequence obtained in this way, which are free of photoresist, the silicon nitride auxiliary layer is first removed, then the silicon oxide auxiliary layer, the silicon material of the first silicon layer being used as the stop layer 203 serves. Then the silicon material of the first silicon layer 203 removed by etching, the underlying tungsten material serving as a stop layer. Below is TEOS silicon oxide filling material 516 filled into the areas exposed by means of the etching process previously carried out. The layer sequence obtained in this way is planarized using a CMP method, silicon nitride material being used as the stop layer. Subsequently, silicon nitride material of the silicon nitride auxiliary layer is removed by means of etching. Furthermore, the silicon oxide auxiliary layer is etched back, as a result of which the silicon material of the second source / drain region 515 is exposed. In that surface region of the layer sequence on which the second source / drain region 515 is exposed, a titanium / titanium nitride barrier is also applied to prepare for the formation of a bit line. Furthermore, tungsten material is applied by means of sputtering and the layer sequence is planarized using a CMP method. This makes a tungsten bit line 517 educated.

In this way, the in 5B memory cell arrangement shown 510 as a layer arrangement according to a fifth exemplary embodiment of the invention on the other silicon wafer 512 obtained as a carrier wafer. The memory cell arrangement 510 out 5B corresponds essentially to the functionality of the memory cell arrangement 450 out 4F ,

The following are in this document Publications quotes:

• [1] DE 195,19,160 C1
• [2] Yonehara, T, Sakagushi, K (2001) "ELTRAN ^®: Novel SOI wafer technology" JSAP International No. 4 (July): 10-16
• [3] Aspar, B, Moriceau, H, Jalaguier, E, Lagahe, C, Soubie, A, Biasse, B, Papon, AM, Letertre, F, Rayssac, O, Barge, T, Ghyselen, B "The Smart Cut ^® Process: A Generic Manufacturing Technique "www.enserg.fr/lpcs/pages/projet/ProgrammeFSWorkshop/P apiers / 13AsparEtAl.doc (as of April 29, 2002)

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Silicon substrate

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removable delamination layer

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first Silicon layer

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second Silicon layer

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layer sequence

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first main surface

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buried Tungsten line

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layer sequence

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other Silicon substrate

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layer sequence

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second main surface

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Layer assembly

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surface area

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SOI wafer

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Silicon carrier layer

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first Silicon oxide layer

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first Silicon layer

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layer sequence

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Gate-insulating layer

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Silicon oxide material

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first Source / drain region

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Channel region

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Gate region

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trenches

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layer sequence

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electrical switchable layer

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common metallic electrode

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second Silicon oxide layer

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layer sequence

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another Silicon wafer

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layer sequence

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vias

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Memory cell arrangement

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second Source / drain regions

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metallic bit

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third Silicon oxide layer

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schematic spatial view

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first memory cell

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second memory cell

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layer sequence

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Silicon regions

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Silicon oxide areas

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Silicon nitride areas

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trenches

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layer sequence

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first Source / drain regions

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Channel region

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Gate-insulating layer

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Gate regions

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Silicon oxide spacer

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layer sequence

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electrical switchable layer

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common metallic electrode

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Silicon oxide layer

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layer sequence

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another Silicon wafer

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layer sequence

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Silicon oxide spacer

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Memory cell arrangement

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second Source / drain regions

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metallic bit

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other Silicon oxide layer

400

layer sequence

401

first Source / drain region

402

Channel region

403

first Silicon nitride layer

404

ONO layer sequence

405

Gate region

406

Silicon structures

410

layer sequence

411

second Silicon nitride layer

412

second Silicon oxide layer

420

first sectional view

421

TEOS silicon oxide

430

second sectional view

431

Tungsten bit line

440

layer sequence

441

another wafer

442

other Silicon substrate

443

third Silicon oxide layer

444

second Source / drain region

450

Memory cell arrangement

451

Silicon oxide spacer

452

Tungsten interconnects

500

layer sequence

501

Tungsten structure

510

Memory cell arrangement

511

TEOS silicon oxide structure

512

another Silicon wafer

513

Silicon substrate

514

fourth Silicon oxide layer

515

second Source / drain region

516

TEOS silica filler

517

Tungsten bit line

Claims (14)

Layer assembly - With a first substrate having - a first processed surface area on a first main surface, which is a metallic conductive Structure contains; - one second processed surface area on one of the first main surface opposite second main surface; - with a second substrate with a third main surface, which on the first main surface of the first substrate is attached. Layer arrangement according to claim 1, wherein the metallic conductive structure has a metallic material or consists of a metallic material. Layer arrangement according to claim 1 or 2, wherein the metallic conductive Structure of at least one word line and / or at least one bit line at least a memory cell integrated in the layer arrangement. Layer arrangement according to one of claims 1 to 3, wherein the first and / or second processed surface area at least one Has integrated component. Layer arrangement according to claim 4, wherein the at least one integrated component is coupled to the metallic conductive structure. Layer arrangement according to claim 4 or 5, in which at least an integrated component is a vertical transistor. Layer arrangement according to one of claims 4 to 6, wherein the first and second processed surface area processed in this way are that the at least one integrated component - on one lower end section by means of the first processed surface area is electrically connected; - at an upper end section electrically connected by means of the second processed surface area is. Layer arrangement according to one of claims 4 to 7, in which between the metallic conductive Structure and the at least one integrated component an electrical switchable layer is provided as a storage layer. Layer arrangement according to one of claims 1 to 8, set up as NROM memory cell array. Method of making a layer-on order in which - in a first substrate - a first surface area is processed on a first main surface, as a result of which a metallically conductive structure is formed; A second surface area is processed on a second main surface opposite the first main surface; - A third main surface of a second substrate is attached to the first main surface of the first substrate. The method of claim 10, wherein prior to processing the second surface area material of the first substrate from one opposite the first main surface Surface of the first substrate is removed. The method of claim 11, wherein the material is removed by the first substrate on a contained therein by means of thermal or removable mechanical treatment Delamination layer is divided into two sub-substrates. Method according to one of claims 10 to 12, wherein the third main surface of the second substrate on the first main surface of the first substrate Wafer bonding is attached. Method according to one of claims 10 to 13, in which as first substrate, a silicon-on-insulator substrate is used.