DE102018206929A1 - Circuit for a bus system and method for operating a circuit - Google Patents

Abstract

A circuit (100) for a bus system is provided. The circuit (100) comprises: a detection circuit (102) configured to detect a rising edge of a transmission input signal (TxD); and a cancellation circuit (104) configured to be coupled between two bus-side terminals (106, 108) in response to detection of the rising edge of the transmit input signal (TxD).

Description

State of the art

The invention relates to a circuit for a bus system and a method for operating a circuit for a bus system.

It is known that long-lasting oscillations of a bus voltage of a bus system due to improper termination or an improper topology of the bus system are essential factors that can lead to error-prone data transmission. In particular, a shortening of the bit time due to increased transmission rates is problematic here.

To compensate for vibrations of the voltage is out of the DE 10 2015 222 334 A1 It is known that bus oscillations are selectively masked during data reception. A masking element is provided for masking oscillations of the bus signal for a predetermined masking time if a monitoring result shows that oscillations exceed a difference of the bus signal after a transition of the bus signal from a dominant to a recessive state at least a predetermined threshold value.

Disclosure of the invention

The problems of the prior art are solved by a circuit according to claim 1 and a method according to an independent claim. Advantageous developments are specified in the subclaims and in the following description of exemplary embodiments.

According to a first aspect of this description, a circuit for a bus system is provided. The circuit comprises: a detection circuit configured to detect a rising edge of a transmission input signal; and a suppression circuit configured to be coupled between two bus-side terminals in response to detection of the rising edge of the transient input signal. Consequently, the connection of the suppression circuit is detected in the detection of the rising edge of the transmission input signal and there is the advantage that an attenuation of a vibration on a bus line through the switched suppression circuit coincides substantially simultaneously with the transmission of the transmission signal via the two bus-side ports , Consequently, possible overshoots on a bus line are already attenuated during transmission. The robustness of the communication is thus increased.

An advantageous embodiment is characterized in that the detection circuit is configured to switch on the suppression circuit for a predetermined switch-on period, and to switch off the suppression circuit after the predetermined switch-on period has elapsed.

An advantageous embodiment is characterized in that the detection circuit is configured to switch off the suppression circuit as soon as a falling edge of the transmission input signal is detected. Advantageously, a dominant transmitted bit is not disturbed by the connection of the suppression circuit.

An advantageous embodiment is characterized in that the determination circuit is configured to switch the suppression circuit between the bus-side terminals only after a delay period has elapsed after the ascertainment of the rising edge of the transceiver input signal.

The delay time period allows a transition from the dominant to the recessive state to take place simultaneously with the connection of the suppression circuit. This prevents negative effects of too early ringing suppression on the signal still present on the bus in the dominant state.

An advantageous embodiment is characterized in that the determination circuit is configured to determine a state of the bus system in which the transmission input signal has a number of consecutive bit times, in particular six bit times, the value zero, and wherein the suppression circuit is configured to not be connected between two bus-side terminals when the state of the bus system is detected.

Advantageously, a connection of the suppression circuit and thus a disturbance of subsequent driven or dominant bits is prevented.

Another aspect of the description relates to a transceiver for a subscriber station of a bus system, wherein the transceiver comprises the circuit according to the first aspect.

Another aspect of the description relates to a method of operating a circuit for a bus system, the method comprising: determining a rising edge of a transmit input signal; and connecting a suppression circuit between two bus-side terminals in response to the detection of the rising edge of the transmission input signal.

• 1 eine Schaltung in schematischer Form;
• 2 ein schematisches Signal-Zeit-Diagramm; und
• 3 ein beispielhaftes Bussystem in schematischer Form.

In the figures show:

• 1 a circuit in schematic form;
• 2 a schematic signal-time diagram; and
• 3 an exemplary bus system in a schematic form.

1 shows a circuit 100 for a bus system. The circuit 100 includes a detection circuit 102 and a suppression circuit 104 , wherein the suppression circuit 104 between two bus-side connections 106 and 108 are arranged. About the connection 106 will the circuit 100 to a first bus line CAN_H connected. About the connection 108 will the circuit 100 to a second bus line CAN_L connected. The investigation circuit 102 determined in dependence on a transmission input signal TxD whether an interposition of a resistor 112 the suppression circuit 104 to be done or not.

The investigation circuit 102 and the suppression circuit 104 are designed for example as an ASIC, FPGA or as a discrete circuit. Furthermore, the detection circuit 102 and the suppression circuit 104 For example, a processor equipped with software to perform the respective software-defined functions. Of course, hybrid forms comprising a physical circuit and the processor on which the software is executed are also conceivable. The software is stored on a corresponding memory element. The circuit 100 is for example part of a transceiver for a subscriber station of a bus system. In another embodiment, the circuit 100 in addition to an existing transceiver.

The suppression circuit 104 is to reduce the differential voltage v_diff in the transition from dominant to recessive. Shown in schematic form comprises the suppression circuit 104 for example, a switch 110 and a resistor arranged in series therewith 112 , This resistance 112 is operated, for example, with different resistance values or impedance values. Of course, the suppression circuit 104 be designed differently and include, for example, a MOS-FET, a diode or other components with linear or non-linear behavior to reduce the differential voltage in the transition from dominance to recessive. The resistance 112 will only be between the two bus-side ports 106 . 108 switched when a rising edge of the transmit input signal TxD occurs and this circumstance of the suppression circuit 104 using the signal RSC_on is communicated.

A controller circuit 202 generates the transmit input signal TxD , A turn-on period for activating the resistance of the suppression circuit is limited to 50% of a bit time, in particular to 30% of the bit time, but comprises at least 10% of the bit time. The controller circuit 202 has knowledge of the bit time, which corresponds to the duration of one bit, in order to be able to send a message. The relevant bit boundaries at which the suppression circuit 104 is to be turned on, in response to the transmission input signal TxD determined.

So is the rising edge (from 0 to 1) of the transmit input signal TxD before, so the controller circuit wants 202 that the transmission circuit 212 no longer drives the bus.

2 shows a schematic signal-time diagram. It is a transition of tension v_diff from a second state (recessive level) to a first state (dominant level) and shown back. When returning from the first state to the second state undesirable vibrations S occur. To attenuate this, when a rising edge in the transmit input signal TxD is detected, the resistance of the suppression circuit during the Zuschaltzeitdauer Ton connected between the two bus-side ports. Furthermore, the bit time Tb is shown between two adjacent bit boundaries tB. Furthermore, the time offset tz between determining a rising edge of the transmit input signal TxD and the actual connection of the resistance of the suppression circuit. The signal RSC_on is therefore the time offset tz postponed. The time offset tz corresponds to a time offset, which by the transmission circuit 212 is produced. Delaying the signal RSC_on about the time offset tz is optional. Is the signal RSC_on before the actual edge of the signal v_diff active, so the switched resistance of the suppression circuit helps 104 in that the non-driven bus state sets, which is an advantage.

Optionally detects the detection circuit 102 whether the send input signal TxD for about six past bit times had the value zero. That is with CAN the duration of a so-called error flag. After the error flag, a rising edge follows in the transmit input signal TxD to the value one. In this case, by means of the signal RSC_on no connection of the resistance communicated. This is done because other nodes on this error flag will also respond with an error flag, ie with six dominant (driven) bits. Those driven bits would be disturbed by the switched resistance.

3 shows an exemplary configured bus system comprising two subscriber stations 502 . 504 , Each of the subscriber station 502 . 504 includes the respective circuit 100 , which with the first connection 106 to the first bus line CAN_H and with the second connection 108 to the second bus line CAN_L connected. The bus lines CAN_H and CAN_L are at their ends via a respective terminating resistor R1 and R2 connected with each other. By enabling / disabling the suppression circuit between the bus-side ports 106 . 108 cause the respective circuits 100 the subscriber station 502 and 504 in that oscillations are damped and thus reduced from dominant to recessive in a change of state. The bus system 500 operates according to the embodiments according to the CAN standard such as ISO11898. The circuit 100 and the operation of the circuit can, however, be easily transferred to other bus systems as well. In addition, other bus topologies are conceivable.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102015222334 A1 [0003]

Claims (7)

A circuit (100) for a bus system, the circuit (100) comprising: - a detection circuit (102) configured to detect a rising edge of a transmission input signal (TxD); and - A suppression circuit (104) which is configured to be switched between two bus-side terminals (106, 108) in response to the detection of the rising edge of the transmission input signal (TxD). The circuit (100) after the Claim 1 wherein the detection circuit (102) is configured to switch on the suppression circuit (104) for a predetermined turn-on time period and to turn off the suppression circuit (104) after the predetermined turn-on time has elapsed. The circuit (100) of any one of the preceding claims, wherein the detection circuit (102) is configured to switch the suppression circuit off once a falling edge of the transient input signal (TxD) is detected. The circuit (100) of any one of the preceding claims, wherein the detection circuit (102) is configured to switch the suppression circuit between the bus-side terminals (106, 108) only after determining the rising edge of the transient input signal (TxD). a delay period has expired. The circuit (100) of any one of the preceding claims, wherein the detection circuit is configured to determine a state of the bus system in which the transmit input signal (TxD) has a number of consecutive bit times, in particular six bit times, zero value, and wherein the Suppression circuit (104) is configured so as not to be connected between two bus-side terminals (106, 108) when the state of the bus system is detected. A transceiver for a subscriber station of a bus system, the transceiver comprising the circuit (100) according to any one of the preceding claims. A method of operating a circuit (100) for a bus system, the method comprising: - determining (102) a rising edge of a transmit input signal (TxD); and - Connecting (104) of a suppression circuit (104) between two bus-side terminals (106, 108) in response to the determination of the rising edge of the transmission input signal (TxD).

Images