CN2613046Y - Chip packaging structure - Google Patents

Abstract

The utility model discloses a chip sealing structure and the manufacturing craft, wherein the chip sealing manufacturing craft is a manufacturing craft making use of high precise thin line, such as TFT-LCD manufacturing craft, IC manufacturing craft or a manufacturing craft with other high density base plate which is used to strengthen the line distribution density and decrease the electric connecting length to reach a manifestation of high electric property. Firstly one basic plate is regarded as a hard basic plate, wherein the basic plate is equipped with at least one slot hole, the material of the basic plate can be ceramic, glass or metal, and the basic plate can be a printing circuit board, then an embedding block is embedded to the slot hole which forms a multiple layer inner connection device layer on the basic plate with a high density welding pad (a convex pad) and micro thin line, then the embedding block is removed, the chip is embedded on the slot hole on the basic plate, the chip goes across the source surface, and is connected with the multiple layer inner connection device layer by way of covering plates connection, and is electrically connected with the internal lines of the multiple layer inner connection device layer.

Description

Chip package structure

technical field

The utility model relates to a chip packaging structure and a manufacturing process thereof, in particular to a chip packaging structure with high-density contacts and fine lines and a manufacturing process thereof.

Background technique

Flip Chip Interconnect Technology (FC for short) uses an area array to arrange multiple die pads on the active surface of the die. And form bumps on the chip pad, and then flip the chip, and then use these bumps to electrically and structurally connect the chip pad to the carrier (carrier) respectively Contacts on the chip enable the chip to be electrically connected to the carrier through the bumps, and to be electrically connected to external electronic devices through the internal circuit of the carrier. It is worth noting that since the chip bonding technology (FC) can be applied to the high pin count (High Pin Count) chip packaging structure, and has many advantages such as reducing the chip packaging area and shortening the signal transmission path, the chip bonding technology At present, it has been widely used in the field of chip packaging. Common chip packaging structures that apply flip chip bonding technology include Flip Chip Ball Grid Array (FC/BGA) and Flip Chip Pin Grid Array (Flip ChipPin Grid Array). Array, FC/PGA) and other types of chip packaging structures.

Please refer to FIG. 1 , which shows a schematic cross-sectional view of a conventional pad ball grid array chip packaging structure. The chip package structure 100 includes a substrate 110 , a plurality of bumps 120 , a chip 130 , and a plurality of solder balls 140 . Wherein, the substrate 110 has a top surface 112 and a corresponding bottom surface 114, and the substrate 110 further has a plurality of bump pads 116a and a plurality of ball pads 116b. In addition, the chip 130 has an active surface (active surface) 132 and a corresponding back surface 134, wherein the active surface 132 of the chip 130 generally refers to the side of the chip 130 with active components (activedevice) (not shown), and The chip 130 further has a plurality of chip pads 136, which are disposed on the active surface 132 of the chip 130, and used as a medium for the signal output and output of the chip 130, wherein the positions of the bump pads 116a correspond to the positions of the chip pads 136 respectively. . In addition, the bumps 120 respectively electrically and structurally connect one of the chip pads 136 to one of the corresponding bump pads 116a. Moreover, the solder balls 140 are respectively disposed on the solder ball pads 116b for electrical and structural connection to external electronic devices.

Please also refer to FIG. 1 , an underfill 150 is filled in the space surrounded by the top surface 112 of the substrate 110 and the active surface 132 of the chip 130 to protect the bump pad 116a, the chip pad 136 and the bump. 120 , and at the same time buffer the phenomenon of thermal stress (thermal stress) mismatch between the substrate 110 and the chip 130 when heated. Therefore, the chip pad 136 of the chip 130 will be electrically and structurally connected to the bump pad 116a of the substrate 110 through the bump 120, and then routed down to the bottom of the substrate 110 through the internal circuit 118 of the substrate 110. The solder ball pads 116b on the bottom surface 114 are finally electrically and structurally connected to external electronic devices via the solder balls 140 on the solder ball pads 116b.

In consideration of improving the computing speed of the chip and reducing the manufacturing cost of the chip, the area of the chip and the gap between the chip pads must be gradually reduced, which means that the density of the chip pad will be relatively gradually increased. Therefore, when a chip with a high-density chip pad adopts the cover chip (FC) type and is packaged with a ball grid array (BGA) or a pin grid array (PGA) at the same time, due to the adjacent chips of the chip The pitch of the pads is very small. At this time, it is necessary to use a substrate with high-density bump pads and fine lines, so that the chip can be placed on the top surface of the substrate in a cover-chip bonding manner, and the internal circuit of the substrate can be rewound. The chip pads of the chip are extended and distributed to the bottom surface of the substrate, and then through contacts such as balls or pins located on the bottom surface of the substrate, the chip can finally be electrically connected to external electronic devices.

As mentioned above, the common materials of the substrates of the cover ball grid array type (FC/BGA) or the cover pin grid array type (FC/PGA) include ceramics and organic materials. An organic substrate (organic substrate) in which an organic material is used as a material of a dielectric layer (dielectric layer) is relatively common. It is worth noting that since the organic substrate is seriously affected by the thermal expansion of the dielectric layer, the line width and line spacing of the organic substrate that can be mass-produced today can only reach 25 microns and 25 microns, respectively. Therefore, it is difficult to form fine internal circuits. At the same time, the organic substrate must use a core layer as the internal structure of the organic substrate, and at the same time build up from the upper and lower sides of the core layer to form multi-layer wiring layers (such as 1/2/1 layer or 2/2/2 layers), in other words, the traditional manufacturing process cannot form the wire layer on a single side of the core layer, so that the internal wiring of the organic substrate will not be formed on the same side of the core layer.

Utility model content

In view of this, the purpose of this utility model is to provide a chip packaging structure and manufacturing process thereof, which can provide a multi-layer interconnect layer (multi-layer interconnect layer) of high-density solder pads (bump pads) and fine lines, and can The manufacturing cost of the chip packaging structure is effectively reduced.

In order to achieve the above purpose of the present invention, the present invention proposes a chip packaging structure, which is mainly composed of a substrate, a multi-layer interconnection layer and a chip. The substrate has a top surface and a corresponding bottom surface, and the substrate further has a slot hole, wherein the slot hole penetrates the substrate and connects the top surface and the bottom surface. In addition, the multilayer interconnection layer has a first surface and a corresponding second surface, and the multilayer interconnection layer is arranged on the top surface of the substrate through the first surface, and closes one end of the slot near the top surface, and the multilayer interconnection layer The inline layer has an internal line. In addition, the chip has an active surface and a corresponding back surface, wherein the chip is embedded in the slot hole of the substrate, and the chip is structurally connected to the first surface of the multi-layer interconnection layer through the active surface and in the way of cover chip bonding, And it is electrically connected to the internal circuit of the multilayer interconnection layer.

In order to achieve the above purpose of the utility model, the utility model proposes a chip packaging manufacturing process, including: (a) providing a substrate, wherein the substrate has a top surface and a corresponding bottom surface, and the substrate has a slot hole, and the slot The hole runs through the substrate, and connects the top surface and the bottom surface; (b) inserts a fitting block into the slot hole, and the fitting block has a fitting surface, and the fitting surface is aligned with the top surface of the substrate; (c) forms a The multilayer interconnection layer is on the top surface of the substrate and the fitting surface of the fitting block, wherein the multilayer interconnection layer has a first surface and a corresponding second surface, and the multilayer interconnection layer passes through the first surface, and disposed on the top surface of the substrate and the fitting surface of the fitting block, and the multilayer interconnection layer has an internal circuit; (d) removing the fitting block; and (e) embedding a chip in the slot hole of the substrate, Wherein the chip has an active surface and a corresponding back surface, and the chip is structurally connected to the first surface of the multilayer interconnection layer through the active surface and in the way of cover chip bonding, and is electrically connected to the multilayer interconnection layer Internal wiring of the online layer.

Therefore, the utility model utilizes the manufacturing technology of thin film transistor liquid crystal display panel (TFT-LCDpanel), the manufacturing technology of integrated circuit (IC) or the manufacturing technology of high-density substrate and their respective production machines. As a hard bottom plate, and insert a fitting block into the slot hole of the substrate, then form a multi-layer interconnection layer with high-density solder pads (bump pads) and fine lines on the substrate, and then remove the fitting Finally, the chip is embedded in the slot hole of the substrate, and the chip can be electrically and structurally connected to the multi-layer interconnection layer in the way of cover sheet bonding, and the chip packaging manufacturing process of the present invention is completed.

In order to make the above-mentioned purpose, features and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 shows a schematic cross-sectional view of a traditional chip packaging structure of a paddle ball grid array; and

2A to 2F sequentially show a schematic flow chart of a chip packaging manufacturing process in a preferred embodiment of the present invention.

Wherein, the description of reference signs is as follows:

100: Chip package structure 110: Substrate

112: top surface 114: bottom surface

116a: bump pad 116b: solder ball pad

120: Bump 130: Chip

132: Active surface 134: Back side

136: chip pad 140: solder ball

150: primer

Detailed ways

Please refer to FIGS. 2A to 2F , which sequentially illustrate a schematic flow chart of a chip packaging manufacturing process according to a preferred embodiment of the present invention. Please refer to FIG. 2A first. First, a substrate 210 is provided. The substrate 210 has a top surface 212 and a corresponding bottom surface 214. The slot hole 216 is formed through the top surface 212 and the bottom surface 214 of the substrate 210 by conventional drilling or chemical etching. In addition, the material of the substrate 210 is, for example, ceramics, glass or metal, and the substrate 210 can also be a low-cost printed circuit board (Printed Circuit Board, PCB). 2B, a fitting block 220 is embedded in the slot 216, and the fitting block 220 has a fitting surface 222, and the fitting surface 222 is aligned on the top surface 212 of the substrate 210, so that the top of the substrate 210 The surface 212 and the fitting surface 222 of the fitting block 220 can jointly form a planarized surface, wherein the top surface 214 of the substrate 210 and the fitting surface 222 of the fitting block 220 must have a higher level of flatness (co-planarity) ), to improve the yield of the subsequent manufacturing process of fine lines. In addition, the outer surface of the fitting block 220 forms, for example, a thermal release tape 224 or a solder layer (solder layer), and the fitting block 220 is relatively positioned in the slot through the viscosity of the adhesive layer 224 or the solder layer. 216 , and in the subsequent manufacturing process, the adhesive layer 224 can also be heated to reduce the viscosity of the adhesive layer 224 to facilitate the removal of the fitting block 220 .

Then please refer to FIG. 2C, forming a multilayer interconnection layer 230 on the top surface 212 of the substrate 210 and the fitting surface 222 of the fitting block 220, wherein the multilayer interconnection layer 230 mainly includes an isolation base layer (isolation base layer) 232 , a patterned multi-layer wire layer 234, at least one dielectric layer 236 and a plurality of conductive plugs 238, and these wire layers 234 are sequentially overlapped on the isolation bottom layer 232, and the dielectric layer 236 is arranged in two phases between adjacent wire layers 234, and these conductive plugs 238 respectively penetrate through the dielectric layer 236 and electrically connect two adjacent wire layers 234, and these wire layers 234 and these conductive plugs 238 constitute an inner circuit (inner circuit )240. Wherein the internal circuit 240 is isolated from the substrate 210 by the isolation bottom layer 232, and the isolation bottom layer 232 is, for example, a dielectric material layer, and at least one wire plug 246 can be formed in the isolation bottom layer 232, so that the internal circuit 240 can be The substrate 210 is electrically connected via the conductive plug 246 .

As shown in FIG. 2C , the internal circuit 240 forms a plurality of bump pads 242 on the first surface 230 a of the multi-layer interconnection layer 230 , and the bump pads 242 are correspondingly located within the range surrounded by the slots 216 of the substrate 210 . In addition, the internal circuit 240 further forms a plurality of bonding pads 244 on the second surface 230b of the multilayer interconnection layer 230 for connecting the contacts 290 (as shown in FIG. 2F ), and the contacts 290 are arranged on the multilayer in an area array. On the second surface 230b of the inner line layer 230 . In addition, the material of the wire layer 234 of the internal connection 240 is, for example, copper, aluminum and these alloys, and the material of the dielectric layer 236 is, for example, silicon nitride, silicon oxide or other organic dielectrics. wait. It should be noted that in order to protect the topmost wire layer 234 , a patterned solder mask 250 can be formed on the topmost wire layer 234 to expose the bonding pads 244 .

Also as shown in FIG. 2C, since the present invention can utilize the high-density manufacturing technology of liquid crystal display panels or integrated circuits to form this multilayer interconnection layer 230 on the substrate 210, so that the interior of the multilayer interconnection structure 230 The line width and line pitch of the circuit 240 can range from 1 to several microns. Therefore, compared with the conventional substrate 110 with organic material as the dielectric layer material shown in FIG. and finer lines. In addition, when forming the multilayer interconnection layer 230 on the substrate 210, a passive component (not shown) can be arranged inside the multilayer interconnection layer 230 at the same time, and electrically connected to the multilayer interconnection layer 230. The internal circuit 240 of the internal connection layer 230 may use a special winding design of the internal circuit 240 to form passive components such as capacitors and inductors.

Also as shown in FIG. 2C, before chip packaging, in order to ensure that the electrical properties of the internal circuit 240 of the multilayer interconnection layer 230 are normal, the electrical test (electrical test) of the internal circuit 240 of the multilayer interconnection layer 230 can be performed in advance. This will ensure that the chip packaging structure can work normally after the chip is subsequently packaged on the multi-layer interconnection layer 230 . First, the internal circuit 240 is tested by contacting the bonding pad 244 with a plurality of probe points (not shown), and a test circuit 226 is formed on the mating surface 222 of the mating block 220, and the bump pads of the multi-layer interconnection layer 230 242 is connected to the test circuit 226 and electrically tests the internal circuit 240 of the multi-layer interconnection layer 230 through the test circuit 226 . After the multilayer interconnection layer 230 is electrically tested, it can timely detect some circuits that cannot operate normally, so as to ensure that the chip packaging structure can operate normally after the chip is subsequently packaged in the multilayer interconnection layer 230, and then Improve the qualification rate of the manufacturing process.

Next, referring to FIG. 2D , the fitting block 220 is removed so that the bottom surface 214 of the substrate 210 forms the original slot 216 and exposes the bump pads 242 on the first surface 230 a of the multi-level interconnect 230 . Since the fitting block 220 is embedded in the slot 216 of the substrate 210 with the adhesive layer 224 (or solder layer), it is only necessary to heat the adhesive layer 224 (or solder layer) to lower the adhesive layer 224 (or solder layer). Viscosity, the fitting block 220 can be removed from the slot hole 216 of the substrate 210 .

2E, a chip 260 is embedded in the slot 216 of the substrate 210, wherein the chip 260 has an active surface 262 and a corresponding back surface 264, and the chip has a plurality of chip pads 266, which are located on the chip 216. Active surface 262 . In addition, a plurality of bumps 268 are electrically and structurally connected to the chip pad 266 and the bump pad 242 respectively, so the chip 260 can be disposed on the first surface 230a of the multilayer interconnection layer 230 in the way of chip bonding. , and electrically connect the chip 260 to the internal circuit 240 of the multilayer interconnection layer 230 . In this way, the chip packaging structure 200 is completed, wherein the active surface 262 of the chip 260 forms a primer layer 270, and the primer layer 270 can surround the bumps 268, so there is no need to additionally fill the primer into the chip 260 and the multi-layer The space enclosed between the inline layers 230 .

Next, please refer to FIG. 2F , after the cover chip bonding is completed, the chip packaging structure can further fill the space surrounded by the chip 260 , the multi-layer interconnection layer 230 and the substrate 210 with an encapsulant 272 to cover the chip 260 . In addition, the back surface 264 of the chip 260 and the bottom surface 214 of the substrate 210 can optionally be equipped with a heat sink 280, the material of which is a material with good heat dissipation, such as copper, aluminum and their alloys, to place the chip 260 on the The heat generated during high-speed operation is quickly conducted to the surface of the chip package structure 200 , thereby improving the heat dissipation performance of the chip package structure 200 . Moreover, a plurality of contacts 290 can also be configured on the surface of the bonding pad 244 for connecting to an external electronic device (not shown), and the contact 290 is, for example, a ball or a pin for A chip package structure of the chip ball grid array type (FC/BGA) or the chip pin grid array type (FC/PGA) is formed.

As shown in FIG. 2F , in the above-mentioned chip packaging structure 200, it is not limited to a single-chip packaging structure, and it can be suitable for packaging multiple chips 260 only by slightly changing the position and number of the slot holes 216 of the substrate 210. On a single substrate 210, these chips 260 are respectively located in one of the slot holes 216 of the substrate 210, and the chips 260 can be electrically connected to each other through the internal circuit 240 of the multilayer interconnection layer 230, so the chip packaging structure 200 will It can be applied to chip packaging structures such as Multi-Chip Module (MCM) and System In Package (SIP).

As shown in FIG. 2C, since the material of the substrate 210 can be a conductive material such as metal, the substrate 210 can be used as the ground terminal of the chip package structure 200. The method is, for example, as shown in FIG. 2C, forming at least one conductive plug 246 on the multilayer On the first surface 230a of the interconnection layer 230, the conductive plug 246 is structurally connected to the top surface 212 of the substrate 210, and is electrically connected to the substrate 210, and the grounding circuit of the multilayer interconnection layer 230 is through the conductive plug. The plug 246 is electrically connected to the substrate 210 . In this way, the internal circuit 240 of the chip package structure 200 can use a substrate 210 with good conductivity to increase the area of its ground terminal.

In addition, as shown in the partial enlarged view of the lower left corner of FIG. 2F, the substrate 210 can also be a printed circuit board, which has a substrate circuit 218, and the first surface 230a of the multilayer interconnection layer 230 has at least one conductive plug. 246, wherein the conductive plug 246 is structurally connected to the top surface 212 of the substrate 210, and is electrically connected to the substrate circuit 218 of the substrate 210, so that the internal circuit 240 of the multilayer interconnection layer 230 can pass through the conductive plug 246, And electrically connected to the substrate circuit 218 of the substrate 210 . In this way, the chip package structure 200 can not only use the internal circuit 240 of the multi-layer interconnection layer 230 to lay out fine circuits, but also use the substrate circuit 218 provided by the substrate 210 to increase the layout space, so the overall structure of the chip package structure 200 can be improved. line area.

It can be seen from the above description that the chip packaging structure and its manufacturing process of the present invention use a substrate as the bottom plate, wherein the substrate has slots as large as the chip, and the material of the substrate can be ceramics, glass or metal, and the substrate can also be It is a printed circuit board, and then a embedded block is embedded in the slot, and a multi-layer interconnection layer with high-density solder pads (bump pads) and fine lines is formed on the substrate, and then the embedded block, and then embed the chip in the slot hole of the substrate, and the chip is structurally connected to the surface of the multi-layer interconnection layer through the active surface and in the way of covering chip bonding, and is electrically connected to the multi-layer internal connection layer. The internal circuits of the connection layer are finally obtained with a chip package structure.

To sum up, the chip packaging structure of the present invention and its manufacturing process have the following advantages:

1. This utility model integrates the manufacturing process technology and production machine of liquid crystal display panel or integrated circuit into the chip packaging manufacturing process of the present utility model. It is worth noting that due to the liquid crystal display panel, integrated circuit or high The manufacturing process technology of the density substrate is very mature at present, so in the case of mass production, the manufacturing cost of the chip packaging structure will be greatly reduced.

2. The utility model uses a plurality of probes to contact the bonding pads to test the internal circuit, and the mating surface of the fitting block also forms a test circuit, and through this test circuit, the incoming electricity is tested for the internal circuit of the multi-layer interconnection layer Whether it is normal or not, after the subsequent chip is packaged in the multi-layer interconnection layer, this will effectively improve the pass rate of the manufacturing process of the chip package structure.

3. Since the utility model utilizes the manufacturing technology of the liquid crystal display panel, the line width and line spacing of the wires that can be produced can reach 1 micron, or even less than 1 micron, so the density of the chip pad on the chip gradually increases In the case of the chip packaging and manufacturing process of the utility model, the density of the chip pad of the chip can be fully matched, and the multi-layer interconnection layer of the high-density solder pad (bump pad) and the micro-circuit is provided, and it is easier to control the multi-layer The unit electrical impedance of the wires in the interconnection layer to improve the electrical properties of the chip packaging structure.

4. In the chip packaging structure of the present utility model, since the fitting block is embedded in the slot hole of the substrate through the glue layer (or solder layer), it is only necessary to heat the glue layer (or solder layer) to reduce the The viscosity of the glue layer (or solder layer) can remove the embedded block from the slot hole of the substrate.

5. In the chip packaging structure of the present utility model, multiple chips or other passive components can be embedded in multiple slots of the substrate, so that the chip packaging structure of the present utility model can be applied to multi-chip modules (MCM) and System in single package (SIP) and other chip package types.

Although the utility model has been disclosed as above with a preferred embodiment, it is not intended to limit the utility model. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the utility model. Therefore, the scope of protection of the present utility model should be determined by the appended claims.

Claims (10)

1. a chip-packaging structure is characterized in that, this structure comprises:

One substrate has an end face and a corresponding bottom surface, and this substrate has more a slotted eye, and wherein this slotted eye runs through this substrate, and connects this end face and this bottom surface;

One multilayer interconnect layer, have a first surface and a corresponding second surface, and this multilayer interconnect layer is disposed at this end face of this substrate via this first surface, and seals the end near this end face of this slotted eye, and this multilayer interconnect layer has an internal wiring; And

One chip, has an active surface and a corresponding back side, wherein this chip system embeds this slotted eye of this substrate, and this chip is via this active surface, and to cover the mode of chip bonding, structural this first surface that is connected to this multilayer interconnect layer, and be electrically connected on this internal wiring of this multilayer interconnect layer.

2. chip-packaging structure as claimed in claim 1 is characterized in that, the material of this substrate comprise pottery, glass and metal one of them.

3. chip-packaging structure as claimed in claim 1 is characterized in that, the material of this substrate is a conductive material.

4. chip-packaging structure as claimed in claim 3, it is characterized in that, this multilayer interconnect layer has more at least one conductive plunger, and structural this end face that is connected to this substrate of this conductive plunger, and be electrically connected on this substrate, and this internal wiring of this multilayer interconnect layer is via this conductive plunger, and is electrically connected on this substrate.

5. chip-packaging structure as claimed in claim 1 is characterized in that this substrate is a printed circuit board (PCB), and has a base plate line.

6. chip-packaging structure as claimed in claim 5, it is characterized in that, this multilayer interconnect layer has more at least one conductive plunger, and structural this end face that is connected in this substrate of this conductive plunger, and be electrically connected on this base plate line of this substrate, and this internal wiring of this multilayer interconnect layer is via this conductive plunger, and is electrically connected on this base plate line of this substrate.

7. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises a sealing, and it is filled in the space that is surrounded between this chip, this multilayer interconnect layer and this substrate.

8. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises a fin, and it is disposed at this back side of this chip and this bottom surface of this substrate.

9. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises a plurality of contacts, its structural this second surface that is connected to this multilayer interconnect layer, and be electrically connected at this internal wiring of this multilayer interconnect layer.

10. chip-packaging structure as claimed in claim 1 is characterized in that, more comprises at least one passive component, and it is embedded in the inside of this multilayer interconnect layer, and this passive component system is electrically connected at this internal wiring of this multilayer interconnect layer.

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