CN211426703U - Chip detection device - Google Patents

Abstract

The utility model provides a chip detection device, comprising: at least one detection head and a detection host, the detection head includes a plurality of probes and a communication interface, the probes are used for contacting the terminals of the tested chips to make all the probes The probe is connected in communication with the chip to be tested; the communication interface is connected with the probe, and the communication interface is used to realize the communication between the detection head and the detection host; the detection host includes a plurality of function detection circuits and a selection circuit, the selection circuit is used to select the required function detection circuit to communicate with the detection head, so that the detection host can perform corresponding performance detection on the chip through the detection head. The chip detection device of the utility model adopts a mode in which several function detection circuits cooperate with the selection circuit, and the selection circuit selects the corresponding function detection circuit according to the detection requirements, thereby realizing detection of different functions of the chip.

Description

Chip detection device

technical field

The utility model relates to a chip detection device, in particular to a chip detection device in printer consumables.

Background technique

Recording devices, such as printers, copiers, and facsimile machines, are used to record information to be recorded on a recording medium such as paper through consumables (such as ink, toner, etc.). The recording device generally includes a recording device main body and a consumable box. The consumables box is usually detachably mounted on the recording device, and is provided with a consumables chip for marking data information such as the consumption amount or the remaining amount of the consumables in the consumables box. The consumable chip is usually detachably mounted on the consumable box, and a storage element is provided in the chip to store rewritable data such as the consumption or remaining amount of the consumable, and other read-only data related to the consumable box. When the consumable box is installed on the recording device, the chip on the consumable box will establish an electrical connection with the recording device, and perform data exchange with the recording device.

In the current market, not only original consumable chips produced by original manufacturers, but also compatible consumable chips sold by compatible manufacturers are sold. , may lead to changes in the performance of the chip; various factors cause the performance of the consumable chips installed on the consumable box to be uneven, and the product quality and user interests cannot be guaranteed. The consumable chip detection device in the prior art can only detect whether the written data in the consumable chip is complete, but cannot detect other properties of the consumable chip, and evaluate the quality of the chip.

Utility model content

In view of the above problems, the present invention provides a chip detection device, which can comprehensively test the performance of the chip.

The utility model provides a chip detection device, comprising: at least one detection head and a detection host,

The detection head includes a plurality of probes and a communication interface, the probes are used for contacting the terminals of the tested chip to make the probes communicate with the tested chip; the communication interface is connected to the probe. needle connection, the communication interface is used to realize the communication between the detection head and the detection host;

The detection host includes a plurality of function detection circuits and a selection circuit, and the selection circuit is used for selecting a required function detection circuit to communicate with the detection head, so that the detection host performs corresponding performance detection on the chip through the detection head.

Optionally, the detection host further has an information storage unit, and the information storage unit is used for pre-storing information of a variety of different chips.

Optionally, the detection head further includes a configuration storage unit, the configuration storage unit is communicatively connected to the communication interface, and the configuration storage unit is used to store multiple communication protocols and/or multiple electrical definition arrays of terminals. cloth method.

Optionally, the configuration storage unit is further configured to temporarily store the detection result of the detected chip.

Optionally, the plurality of function detection circuits include a terminal electrical definition detection circuit, a communication protocol detection circuit, a read-write function detection circuit, a data acquisition circuit, a power consumption detection circuit, a frequency detection circuit, and a chip maximum/low working voltage detection circuit. Or any combination of two or more of the protection capability detection circuits.

Optionally, the detection host is configured to comprehensively score the performance of the tested chip according to performance detection results of a plurality of the function detection circuits.

Optionally, the detection host further includes an input interface and an output interface;

The input interface is used to receive the chip performance that the user needs to detect, so that the selection circuit selects the corresponding function detection circuit and performs the detection operation through the detection head;

The output interface is used for receiving the detection result of the detection head and displaying it on the detection host.

Optionally, the input interface is connected to a button unit on the detection host, and the user selects detection requirements through the button unit; the output interface is connected to a display screen on the detection host, and the display screen is used for displaying the detection result;

Alternatively, the input interface and the output interface are connected to a touch display screen on the detection host, and the touch display screen can not only allow the user to select detection requirements, but also display the detection results.

Optionally, a communication connection is established between the detection head and the detection host through wired communication or wireless communication.

The chip detection device of the utility model adopts the mode that several function detection circuits cooperate with the selection circuit, and the selection circuit selects the corresponding function detection circuit according to the detection requirements, thereby realizing detection of different functions of the chip. Therefore, the utility model can comprehensively detect and evaluate the performance of the chip, which is beneficial to improve the quality of the product in an all-round way.

Description of drawings

Fig. 1 is the composition of the detection circuit of an embodiment of the chip detection device of the present invention;

2 is an internal circuit module structure of an embodiment of the chip detection device of the present invention;

3 is an external structure of an embodiment of the chip detection device of the present invention;

4 is a terminal electrical definition detection circuit of an embodiment of the chip detection device of the present invention;

5 is an internal circuit structure of a voltage detection circuit of an embodiment of the chip detection device of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. The embodiments described above are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

As shown in FIG. 1 , an embodiment of the present invention provides a chip detection device, comprising: at least one detection head 1 and a detection host 2 ,

The detection head 1 includes a plurality of probes 11 and a communication interface, the probes 11 are used for contacting the terminals of the tested chip so that the probes 11 are communicatively connected with the tested chip; the communication interface Connected with the probe 11, the communication interface is used to realize the communication between the detection head 1 and the detection host 2;

The detection host 2 includes a plurality of function detection circuits 26 and a selection circuit 24, and the selection circuit 24 is used to select a desired function detection circuit 26 to communicate with the detection head 1, so that the detection host 2 is executed by the detection head 4. Check the performance of the chip.

As an optional implementation of this embodiment, the several function detection circuits 26 include a terminal electrical definition detection circuit 261, a communication protocol detection circuit 262, a read/write function detection circuit 263, a data acquisition circuit 264, a power consumption detection circuit 265, a frequency Detection circuit 266 , chip highest/low voltage detection circuit 267 and protection capability detection circuit 268 . Of course, this embodiment does not limit the protection scope of the present invention, and in other embodiments, any two or more function modules from the above-mentioned function detection modules may also be selected.

In this embodiment, the selection circuit 24 is used to select the function detection circuit. Therefore, the chip detection device of this embodiment adopts a method in which several function detection circuits cooperate with the selection circuit 24, and the selection circuit 24 selects the corresponding function according to the detection requirements. Detection circuit, so as to realize the detection of different functions of the chip. Therefore, this embodiment can comprehensively test and evaluate the performance of the chip, which is beneficial to improve the quality of the product in an all-round way.

The detection host needs to establish a communication connection with the tested chip. For example, as shown in FIG. 3 , the chip detection device further includes a detection head 1 , and the detection head 1 includes a plurality of probes 11 and a communication interface for communication with the probes 11 . ;

The plurality of probes 11 are used to make contact with the detection terminals of the chip under test and establish a communication connection.

The detection head 1 and the detection host 2 establish a communication connection through wired communication or wireless communication, wherein the wired communication means that the detection head and the detection host realize the communication connection through a signal line, and the wireless communication means that the detection head and the detection host are realized through Bluetooth, RFID, etc. communication connection.

The above-mentioned detection head 1 establishes a communication connection with the detected chip by contacting with the probe 11 , and the advantage is that the connection can be realized conveniently and quickly. However, the connection manner does not limit the present invention, and any other manner capable of realizing communication connection can also be adopted.

Specifically, as shown in FIG. 2, it is the internal circuit module structure of the chip detection device, wherein the detection head 1 includes: a stylus unit 11 and a communication interface 12, and the communication interface 12 is provided in the internal circuit structure of the detection head 1; the communication interface 12 is respectively connected with a plurality of contact pins 11 and the internal circuit of the host 2, and the plurality of contact pins 11 can be in contact with the terminals of the chip one by one. After the communication interface 12 receives the detection command sent from the host The stylus 11 communicates with the chip, completes the detection and feeds back the detection result to the host 2 . As an optional implementation of this embodiment, the internal circuit of the detection head 1 further includes a configuration storage unit 13, and the configuration storage unit 13 can be used to store a variety of different communication protocols, a variety of electrical definition arrangements of terminals and other information, The communication interface 12 is respectively connected with the plurality of contact pins 11, the configuration storage unit 13 and the internal circuit of the host 2. After the communication interface 12 receives the detection instruction sent from the host 2 side, it calls the required data from the configuration storage unit 13. Or the program communicates with the chip via a plurality of contact pins 11 to complete the detection and feed back the detection result to the host 2 .

As an optional implementation of this embodiment, the host 2 further includes a display screen 21 and a key unit 22 disposed outside, an input interface 23, a selection circuit 24, an information storage unit 25, a detection circuit 26 and an output disposed in the internal circuit module interface 27. The button unit 22 is connected with the input interface 23. When the user presses the corresponding button of the chip performance to be detected, the input interface 23 converts it into an electrical signal and sends the electrical signal to the selection circuit 24 connected to it; the selection circuit 24 is respectively associated with the information The storage unit 25 is connected to the detection circuit 26, wherein the information storage unit is pre-stored with information such as the model of use corresponding to the chip model, the corresponding manufacturer, etc., and the detection circuit 26 includes a plurality of circuits for detecting different chip performances, and a selection circuit 24 Select the corresponding detection circuit 26 according to the above-mentioned electrical signal to detect the chip through the detection head 1, and the detection head 1 feeds back the detection result to the output interface 27, and the output interface 27 is connected to the display screen 21, so the detection result is displayed on the display screen. Further, the host can also comprehensively score and display on the display screen 21 according to the multiple detected performance results. In this embodiment, the display screen 21 is set outside the detection host as a display module, but this method is not unique, and other methods can also be used, for example, an external display device can also be used for display, or a projection display can be used. Wait. The key unit 22 is used as the input module in this embodiment. Similarly, this method is not unique, and other modules capable of completing information input, such as a keyboard or a touch screen, can also be used as the input module.

The chip detection device in this embodiment can detect a variety of different performances of the chip, and can perform comprehensive scoring according to the different performance results of the chip, which is convenient to evaluate the quality of the chip, remove the chip with poor quality, and leave the quality of the chip. Better chips to ensure the interests of users.

The specific description of the detection process of each of the above functional detection circuits is as follows:

Terminal electrical definition detection circuit: As shown in Figure 4, for the convenience of description, in this embodiment, the chip has VCC (power supply terminal), GND (ground terminal), RST (reset terminal), CLK (clock terminal), SDK (data terminal) ) as an example with five terminals, the communication interface 12 includes VCC, GND, RST, CLK, and SDK modules that input corresponding timings to the corresponding terminals on the side of the MCU and the analog printer, and each of the modules shown is respectively associated with each probe 11 is connected, that is, the VCC, GND, RST, CLK, and SDK modules in the communication interface 12 respectively input signals to the VCC, GND, RST, CLK, and SDK terminals of the chip through the probe 11 .

The probes 11 of the plurality of test heads 1 can all be in one-to-one contact with the terminals of the chip to be tested, but the electrical definition arrangement order of the probes 11 of each test head 1 is different. The selection circuit 24 receives the instruction and turns on the terminal electrical definition detection circuit 261 in the detection circuit 26. When the communication interface 12 receives the instruction to detect the electrical definition of the terminal, it sends an instruction to the chip to determine whether the chip can work normally. Explain that the electrical definition arrangement order of the probes of the used detection head 1 is consistent with the electrical definition arrangement order of the chip terminals, and the electrical definition arrangement order of the detection head 1 is sent to the output interface 21 of the host, and displayed on the display screen 27; If the host 2 displays a message indicating that the communication is abnormal, replace other detection heads until the host 2 indicates that the communication is normal and returns to the terminal definition arrangement sequence.

Alternatively, as shown in Figure 4, there is another implementation of an electrically defined detection circuit. When the user selects the electrical definition of the detection terminal through the detection host 2, the selection circuit 24 receives the instruction and turns on the terminal electrical definition detection circuit 261 in the detection circuit 26. When the communication interface 12 receives the instruction to detect the electrical definition of the terminal, the configuration The storage unit 13 reads the pre-stored electrical definition arrangement order of various terminals, and the MCU turns on the corresponding probe 11 according to each electrical definition arrangement order, and inputs the corresponding signal to the chip. When the order is consistent, that is, the test is passed, the MCU sends the corresponding electrical definition arrangement order to the output interface 21 of the host, and displays it on the display screen 27 . This implementation can reduce the number of detection heads that need to be configured.

Since the other circuit performance detection circuits need to predict the electrical definitions of the chip terminals, when testing the performance of the same chip, the detected electrical definitions of the chip terminals are temporarily stored in the configuration storage unit 13, and each subsequent chip performance detection circuit The chips are detected based on the temporarily stored terminal electrical definition sequence. The time period from the detection head touching a certain chip to the time it leaves the chip is determined as the same chip. If the detection head detects no chip contact, the electrical definition sequence of the chip terminals temporarily stored in the configuration storage unit 13 is deleted, which can improve the performance of the host computer. The detection speed is very fast, and there is no need to determine the electrical definition sequence of the terminals for each performance test.

Communication protocol detection circuit: The configuration storage unit 13 stores various communication protocol programs, such as IIC, SPI, parallel port (I/O), DMA and other communication protocols. When the user selects the communication protocol of the detection chip through the detection host 2, the selection circuit 24 receives the instruction and turns on the communication protocol detection circuit 262 in the detection circuit 26. When the communication interface 12 receives the instruction to detect the communication protocol of the chip, the configuration The storage unit 13 reads the communication protocol program and the determined electrical definition sequence of the terminals, and sends different communication protocols to the chip through the data communication terminals. When the chip can work normally under a certain communication protocol, the protocol is sent to the host. The output interface 21 is displayed on the display screen 27.

Since the following circuit performance detection circuits all need to predict the communication protocol of the chip, when detecting the performance of the same chip, the detected communication protocol is temporarily stored in the configuration storage unit 13, and each subsequent chip performance detection circuit is temporarily stored in this way. communication protocol to operate the chip. It is determined as the same chip within the time period from when the detection head touches a certain chip to when it leaves the chip. If the detection head detects no chip contact, the communication protocol temporarily stored in the configuration storage unit 13 is deleted, which can improve the detection speed of the host. There is no need to determine the communication protocol of the chip for every performance test.

Read-write function detection circuit: when the user selects the read-write function of the detection chip through the detection host 2, the selection circuit 24 receives the instruction and turns on the read-write function detection circuit 263 in the detection circuit 26, and the read-write function detection circuit 263 sends the communication The interface 12 sends a read command, the communication interface 12 reads the determined terminal electrical definition sequence and communication protocol program from the configuration storage unit 13, sends the read command to the chip through the data communication terminal, and judges whether the chip has a response, and the judgment result is sent to the chip. Feedback to the output interface 27, if it is normal, it will display "reading function is normal" on the display screen, otherwise it will display "reading function abnormal"; when detecting the writing function, judge the time from when the chip receives the write command to the completion of the write command response, and judge the response time Whether it is within the preset time range, the judgment result is fed back to the output interface 27, if the response time is within the preset time range, the display screen will display "write function is normal", otherwise it will display "write function abnormal";

Data acquisition circuit: when the user selects to acquire the internal data of the chip by detecting the host 2, the selection circuit 24 receives the instruction and turns on the data acquisition circuit 264 in the detection circuit 26, and the data acquisition circuit 264 sends a read instruction to the communication interface 12. The communication interface 12 reads the determined terminal electrical definition sequence and communication protocol program from the configuration storage unit 13, sends the read command to the chip through the data communication terminal, and the chip returns the basic information of the chip to the communication interface 12 through the data communication terminal. The basic information includes chip model, production date, serial number, etc., and the communication interface returns the basic information obtained from the chip to the data acquisition circuit 264 . The information storage unit 25 is pre-stored with information such as the printer model corresponding to each chip model, the corresponding manufacturer, etc. The data acquisition circuit 264 obtains the corresponding signal from the information storage unit 25 according to the chip model, and then sends it to the output interface. 27 and displayed on the display 21.

Power consumption detection circuit: The power consumption detection circuit 265 is divided into a static power consumption detection circuit and a dynamic power consumption detection circuit.

When detecting the static power consumption of the chip, the static power consumption detection circuit sends an instruction to detect the static power consumption of the chip to the communication interface 12. After the communication interface receives the instruction, the MCU in the communication interface 12 conducts the detection of the VCC module and the corresponding chip VCC terminal. The probes corresponding to the remaining terminals of the chip are all connected to the GND module. At this time, the voltage and current of the VCC terminal of the chip are detected, and the static power consumption is calculated. The smaller the static power consumption, the better the performance of the chip.

When detecting the dynamic power consumption of the chip, the dynamic power consumption detection circuit sends an instruction to detect the dynamic power consumption of the chip to the communication interface 12, and the communication interface 12 reads the determined electrical definition sequence of the terminals and the communication protocol program from the configuration storage unit 13, and the communication The MCU in the interface 12 turns on the probes of each module and the corresponding terminal of the chip, sends instructions to the chip, detects the voltage and current of the VCC terminal when the chip is in a normal working state, and calculates the dynamic power consumption. The performance of the chip is better.

Frequency detection circuit: when the user selects the operating frequency of the detection chip through the detection host 2, the selection circuit 24 receives the instruction and turns on the frequency detection circuit 266 in the detection circuit 26. The chip sends an instruction to judge whether the chip can work normally, and determine the frequency range that the chip can work normally. The larger the frequency range of the chip's normal work, the better the performance. ” and “General” are displayed on the display screen 21 .

Voltage detection circuit: when the user selects the working voltage of the detection chip through the detection host 2, the selection circuit 24 receives the instruction and turns on the voltage detection circuit 267 in the detection circuit 26. As shown in FIG. 5, it is the circuit of the voltage detection circuit 267. Schematic diagram, only 4-level resistors are listed in the figure. In the actual application process, the resistance can be increased or decreased. By controlling the switch S to change the value of the resistor R connected to the circuit, the voltage detection circuit 267 sends the VCC to the chip through the communication interface 12 The terminal provides different voltages, and sends commands to the chip under different voltages to determine the highest and lowest voltages that the chip can work normally. The larger the voltage range of the chip's normal operation, the better the performance. The ranges are divided into "Excellent", "Good" and "Fair" and displayed on the display screen 21 .

Protection capability detection circuit: The protection capability detection circuit 268 may include various circuits, such as overcurrent protection, overvoltage protection, temperature protection, electrostatic protection, etc. This embodiment takes overvoltage protection capability detection as an example.

The protection capability detection circuit 268 first obtains the maximum working voltage of the chip through the voltage detection circuit 267, applies a voltage greater than the maximum working voltage to the VCC terminal of the chip through the communication interface 12, and then returns to the normal working voltage, and sends an instruction to the chip at this time. , to judge whether the chip can work normally, if it can work normally, it means that the overvoltage protection capability of the chip is good.

The chip detection device of this embodiment adopts a manner in which several function detection circuits cooperate with the selection circuit, and the selection circuit selects the corresponding function detection circuit according to the detection requirements, so as to realize detection of different functions of the chip. It should be noted that the host can also execute the detection functions of multiple function detection circuits at the same time. Therefore, this embodiment can comprehensively test and evaluate the performance of the chip, which is beneficial to improve the quality of the product in an all-round way.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field of the present invention can easily think of changes within the technical scope disclosed by the present invention. Or replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A chip detection apparatus, comprising: at least one detection head and a detection host,

the detection head comprises a plurality of probes and a communication interface, wherein the probes are used for contacting with terminals of a chip to be detected so as to enable the probes to be in communication connection with the chip to be detected; the communication interface is connected with the probe and is used for realizing the communication between the detection head and the detection host;

the detection host comprises a plurality of function detection circuits and a selection circuit, wherein the selection circuit is used for selecting the required function detection circuit to communicate with the detection head, so that the detection host can perform corresponding performance detection on the chip through the detection head.

2. The chip detection apparatus according to claim 1, wherein: the detection host is also provided with an information storage unit, and the information storage unit is used for prestoring information of various different chips.

3. The chip detection apparatus according to claim 1, wherein: the detection head also comprises a configuration storage unit, the configuration storage unit is in communication connection with the communication interface, and the configuration storage unit is used for storing a plurality of communication protocols and/or a plurality of electrical definition arrangement modes of terminals.

4. The chip detection apparatus according to claim 3, wherein: the configuration storage unit is also used for temporarily storing the detection result of the detected chip.

5. The chip detection device according to any one of claims 1 to 3, wherein: the plurality of function detection circuits include any two or more combinations of a terminal electrical definition detection circuit, a communication protocol detection circuit, a read-write function detection circuit, a data acquisition circuit, a power consumption detection circuit, a frequency detection circuit, a chip maximum/low working voltage detection circuit, or a protection capability detection circuit.

6. The chip detection apparatus according to claim 5, wherein: the detection host is used for comprehensively scoring the performance of the detected chip according to the performance detection results of the plurality of function detection circuits.

7. The chip detection apparatus according to claim 5, wherein: the detection host further comprises an input interface and an output interface;

the input interface is used for receiving the performance of a chip which needs to be detected by a user, so that the selection circuit selects the corresponding function detection circuit and executes detection operation through the detection head;

the output interface is used for receiving the detection result of the detection head and displaying the detection result on the detection host.

8. The chip detection apparatus according to claim 7, wherein: the input interface is connected with a key unit on the detection host, and a user selects a detection requirement through the key unit; the output interface is connected with a display screen on the detection host, and the display screen is used for displaying the detection result;

or the input interface and the output interface are connected with a touch display screen on the detection host, and the touch display screen can be used for a user to select a detection requirement and can display a detection result.

9. The chip detection apparatus according to claim 1, wherein: and the detection head and the detection host machine are in communication connection in a wired communication or wireless communication mode.

10. The chip detection apparatus according to claim 1, wherein: the detected chip is a printing consumable chip and is used for storing relevant information of consumables.

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