CN210301052U - Fetal heart signal processing circuit and fetal heart rate meter - Google Patents
Fetal heart signal processing circuit and fetal heart rate meter Download PDFInfo
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- CN210301052U CN210301052U CN201920432065.1U CN201920432065U CN210301052U CN 210301052 U CN210301052 U CN 210301052U CN 201920432065 U CN201920432065 U CN 201920432065U CN 210301052 U CN210301052 U CN 210301052U
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Abstract
The utility model is suitable for a child heart monitoring technology field provides a child heart signal processing circuit and foetus cardiotachometer. The embodiment of the utility model provides a through providing a fetal heart signal processing circuit including fetal heart signal acquisition device and treater, integrated setting first amplifier circuit, sampling circuit, memory, buffer and the kernel in the treater, simple structure, compactness; the fetal heart signal is collected through the fetal heart signal collecting device, the fetal heart signal is amplified through the first amplifying circuit, the fetal heart signal after amplification is sampled through the sampling circuit, the audio compiling program is solidified in the memory and stored in the sampled fetal heart signal, the audio compiling program is operated through the buffer, the audio signal with the uniformity in the frequency range and the frequency interval is generated and preset according to the stored fetal heart signal and is output, the noise in the fetal heart signal can be effectively eliminated, and the accuracy of the detection result of the fetal heart frequency is improved.
Description
Technical Field
The utility model belongs to the technical field of fetal heart monitoring, especially, relate to a fetal heart signal processing circuit and foetus cardiotachometer.
Background
Fetal heart rate variability in the fetus is the primary means of detection for proper assessment of fetal intrauterine conditions. Currently, a common fetal heart rate monitoring method is to use a doppler fetal heart rate meter to collect and output fetal heartbeat sound.
However, the existing doppler fetal heart rate meter has a complex structure, and the output fetal heart beat sound has more noise, which reduces the accuracy of the detection result of the fetal heart rate.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the utility model provides a fetal heart signal processing circuit and fetal heart rate appearance to solve current doppler fetal monitor structure complicacy, and the fetal heartbeat sound of output has more noise, has reduced the problem of the accuracy of the testing result of fetal heart rate.
The embodiment of the utility model provides a first aspect provides a fetal heart signal processing circuit, including fetal heart signal acquisition device and treater, the treater includes integrated first amplifier circuit, sampling circuit, memory, buffer and the kernel that sets up;
the fetal heart signal acquisition device is electrically connected with the first amplifying circuit and the kernel, the first amplifying circuit, the sampling circuit, the memory and the buffer are sequentially and electrically connected and are all electrically connected with the kernel, and an audio compiling program is solidified in the memory;
the fetal heart signal acquisition device acquires fetal heart signals;
the first amplifying circuit amplifies the fetal heart signals; the sampling circuit samples the amplified fetal heart signals;
the memory stores the sampled fetal heart signals;
the buffer runs the audio compiler to generate and output audio signals with a preset frequency range and frequency interval uniformity according to the stored fetal heart signals;
the core controls the working states of the fetal heart signal acquisition device, the first amplification circuit, the sampling circuit, the memory and the buffer.
In one embodiment, the fetal heart signal acquisition device comprises a piezoelectric ceramic sensor;
the piezoelectric ceramic sensor converts the ultrasonic Doppler signals into voltage signals to obtain the fetal heart signals.
In one embodiment, the sampling circuit comprises an analog-to-digital converter;
and the analog-to-digital converter performs signal sampling in a preset frequency range on the amplified fetal heart signals to obtain the fetal heart signals in the preset frequency range and with uniform frequency intervals.
In one embodiment, the sampling accuracy of the analog-to-digital converter is 24 bits.
In one embodiment, the predetermined frequency range is 0Hz to 200 Hz.
In one embodiment, the fetal heart signal processing circuit further comprises a filter circuit;
the filter circuit is electrically connected between the fetal heart signal acquisition device and the first amplifying circuit;
the filter circuit filters the fetal heart signal.
In one embodiment, the fetal heart signal processing circuit further comprises a second amplifying circuit;
the second amplifying circuit is electrically connected between the fetal heart signal acquisition device and the first amplifying circuit and is also electrically connected with the inner core;
the second amplifying circuit amplifies the fetal heart signal.
In one embodiment, the processor is a single chip microcomputer.
In one embodiment, the fetal heart signal processing circuit further comprises a speaker;
the loudspeaker is electrically connected with the buffer and the inner core;
the buffer runs the audio compiler to generate audio signals with a preset frequency range, frequency interval uniformity and simulated sound effect according to the stored fetal heart signals and outputs the audio signals to the loudspeaker;
and the loudspeaker converts the audio signal into a sound signal with the analog sound effect and plays the sound signal.
A second aspect of the embodiments of the present invention provides a fetal heart rate meter, including the fetal heart signal processing circuit.
The embodiment of the utility model provides a through providing a fetal heart signal processing circuit including fetal heart signal acquisition device and treater, integrated setting first amplifier circuit, sampling circuit, memory, buffer and the kernel in the treater, simple structure, compactness; the fetal heart signal is collected through the fetal heart signal collecting device, the fetal heart signal is amplified through the first amplifying circuit, the fetal heart signal after amplification is sampled through the sampling circuit, the audio compiling program is solidified in the memory and stored in the sampled fetal heart signal, the audio compiling program is operated through the buffer, the audio signal with the uniformity in the frequency range and the frequency interval is generated and preset according to the stored fetal heart signal and is output, the noise in the fetal heart signal can be effectively eliminated, and the accuracy of the detection result of the fetal heart frequency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments or the prior art descriptions will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a fetal heart signal processing circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a fetal heart signal processing circuit provided in the second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a fetal heart signal processing circuit provided in the third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a fetal heart signal processing circuit provided by the fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a fetal heart signal processing circuit according to a fifth embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention better understood, the technical solution in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Example one
As shown in fig. 1, the fetal heart signal processing circuit 100 provided in the embodiment of the present application is applied to a fetal heart rate meter, the fetal heart signal processing circuit 100 includes a fetal heart signal acquisition device 101 and a processor 102, and the processor 102 includes a first amplification circuit 1, a sampling circuit 2, a memory 3, a buffer 4, and a core 5, which are integrally arranged.
In a Specific Application, the Processor may be a Central Processing Unit (CPU), and may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like, and the general-purpose processors may be a single chip microcomputer.
As shown in fig. 1, in the present embodiment, the fetal heart signal acquiring device 101 is electrically connected to the first amplifying circuit 1 and the core 5, the first amplifying circuit 1, the sampling circuit 2, the memory 3 and the buffer 4 are electrically connected in sequence and are all electrically connected to the core 5, and an audio compiler program is solidified inside the memory 3.
In a specific application, the electrical connection refers to a connection for transmitting communication signals such as current signals, voltage signals, pulse signals and the like through cable wires, data wires and the like.
In the present embodiment, the fetal heart signal acquisition device 101 is used to acquire a fetal heart signal.
In a specific application, the type of the fetal heart signal acquisition device is determined by the type of the fetal heart rate meter to which the fetal heart signal processing circuit is applied.
In this embodiment, the piezoelectric ceramic sensor is used for acquiring an ultrasonic doppler signal during fetal heartbeat and converting the ultrasonic doppler signal into a voltage signal to obtain a fetal heart signal; wherein, the ultrasonic Doppler signal is a sound signal, and the fetal heart signal is a voltage signal.
In the present embodiment, the first amplification circuit 1 is used to amplify the fetal heart signal.
In a specific application, the first amplifying circuit may be implemented by any amplifier having a voltage signal amplifying function, and the amplifier may specifically be implemented by an electronic active device such as a transistor or a valve, for example, a bipolar transistor or a field effect transistor.
In the present embodiment, the sampling circuit 2 is used to sample the amplified fetal heart signal.
In a specific application, the sampling circuit can be realized by any sampling device with a frequency sampling function, and is specifically used for sampling signals with the same frequency range and interval uniformity as the normal fetal heart frequency in the fetal heart signals.
In this embodiment, the sampling circuit includes an analog-to-digital converter;
and the analog-to-digital converter performs signal sampling in a preset frequency range on the amplified fetal heart signals to obtain the fetal heart signals in the preset frequency range and with uniform frequency intervals.
In a specific application, the analog-to-digital converter should be a 16-bit, 24-bit or 32-bit analog-to-digital converter with higher sampling precision.
In this embodiment, the sampling precision of the analog-to-digital converter is 24 bits.
In this embodiment, the predetermined frequency range is 0Hz to 200 Hz.
In specific applications, the predetermined frequency range can be reduced to 0 Hz-50 Hz.
In this embodiment, the memory 3 is used to store the sampled fetal heart signals.
In a specific application, the memory is an internal storage medium of the processor, and may be a Smart Memory Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), or the like.
In the present embodiment, the buffer 4 is used for running an audio compiler to generate and output an audio signal with a predetermined frequency range and a uniform frequency interval according to the stored fetal heart signal.
In a specific application, the audio compiler can generate an audio signal with any analog sound effect and the frequency range and the frequency interval characteristic of the audio signal are the same as the normal fetal heart frequency according to the actual needs of a user, and can also generate an audio signal with the sound effect, the frequency range and the frequency interval characteristic of the normal fetal heart signal. Compared with the traditional fetal heart signal, the audio signal generated by the buffer effectively eliminates the noise and the signal interference, thereby improving the accuracy of the detection result of the fetal heart frequency.
In a specific application, the buffer may be a RAM (random access Memory) or a ROM (Read-Only Memory).
In the present embodiment, the core 5 is used to control the operating states of the fetal heart signal acquiring device 101, the first amplifying circuit 1, the sampling circuit 2, the memory 3, and the buffer 4.
In a specific application, the core 5 is mainly used for sending a control instruction to each circuit or device electrically connected thereto in the form of an electrical signal such as a voltage signal, a pulse signal, or the like, so as to control the operating state of each circuit or device, for example, to control the buffer to run an audio compiler.
In this embodiment, the kernel is core hardware in the processor, is a core device for data processing, and carries an operating system program for performing operations such as calculating, sending a control instruction, receiving an instruction, processing data, and the like.
In the embodiment, the fetal heart signal processing circuit comprising the fetal heart signal acquisition device and the processor is provided, and the first amplifying circuit, the sampling circuit, the memory, the buffer and the kernel are integrated in the processor, so that the fetal heart signal processing circuit is simple and compact in structure; the fetal heart signal is collected through the fetal heart signal collecting device, the fetal heart signal is amplified through the first amplifying circuit, the fetal heart signal after amplification is sampled through the sampling circuit, the audio compiling program is solidified in the memory and stored in the sampled fetal heart signal, the audio compiling program is operated through the buffer, the audio signal with the uniformity in the frequency range and the frequency interval is generated and preset according to the stored fetal heart signal and is output, the noise in the fetal heart signal can be effectively eliminated, and the accuracy of the detection result of the fetal heart frequency is improved.
Example two
As shown in fig. 2, in this embodiment, the fetal heart signal processing circuit 100 in the first embodiment further includes a filter circuit 103, and the filter circuit 103 is electrically connected between the fetal heart signal acquiring device 101 and the first amplifying circuit 1.
In the present embodiment, the filter circuit 103 is used to filter the fetal heart signal.
In a specific application, the filter circuit may be implemented by any circuit or device having a voltage signal filtering function, for example, an LC filter circuit or an RC filter circuit.
In this embodiment, fetal heart signals are preliminarily filtered by the filter circuit, so that stray waves in the fetal heart signals can be preliminarily eliminated, a part of the stray signals are removed, then the fetal heart signals enter the processor, and the stray signals can be better eliminated by sampling through the sampling circuit.
EXAMPLE III
As shown in fig. 3, in this embodiment, the fetal heart signal processing circuit 100 in the first embodiment further includes a second amplifying circuit 104, and the second amplifying circuit 104 is electrically connected between the fetal heart signal acquiring device 101 and the first amplifying circuit 1, and is also electrically connected to the core 5.
In the present embodiment, the second amplification circuit 104 is used to amplify the fetal heart signal.
In a specific application, the second amplifying circuit may be implemented by any amplifier having a voltage signal amplifying function, and the amplifier may specifically be implemented by an electronic active device such as a transistor or a valve, for example, a bipolar transistor or a field effect transistor.
In this embodiment, the fetal heart signal enters the processor after being primarily amplified by the second amplifying circuit, and is secondarily amplified by the first amplifying circuit, so that the sampling circuit can conveniently sample the frequency, and the accuracy of frequency sampling is improved.
Example four
As shown in fig. 4, in this embodiment, the fetal heart signal processing circuit 100 in the first embodiment further includes a filter circuit 103 and a second amplifier circuit 104, the filter circuit 103 is electrically connected between the fetal heart signal acquiring device 101 and the second amplifier circuit 104, and the second amplifier circuit 104 is electrically connected between the filter circuit 103 and the first amplifier circuit 1, and is further electrically connected to the core 5.
In the present embodiment, the filter circuit 103 is used to filter the fetal heart signal.
In a specific application, the filter circuit may be implemented by any circuit or device having a voltage signal filtering function, for example, an LC filter circuit or an RC filter circuit.
In the present embodiment, the second amplification circuit 104 is used to amplify the fetal heart signal.
In a specific application, the second amplifying circuit may be implemented by any amplifier having a voltage signal amplifying function, and the amplifier may specifically be implemented by an electronic active device such as a transistor or a valve, for example, a bipolar transistor or a field effect transistor.
In this embodiment, child heart signal is through the preliminary filtering of filter circuit, can tentatively eliminate the stray wave in the child heart signal, gets rid of partly noise signal, then gets into the treater after the preliminary amplification of second amplifier circuit, carries out the secondary through first amplifier circuit again and enlargies, can effectively improve the sampling circuit and carry out the rate of accuracy that frequency sampled to the noise signal that disappears that can be better.
EXAMPLE five
In this embodiment, the fetal heart signal processing circuit 100 according to any one of the first to fourth embodiments further includes a speaker 105, and the speaker 105 is electrically connected to the buffer 4 and the core 5.
As shown in fig. 5, the case where the fetal heart signal processing circuit 100 further includes a speaker 105 on the basis of the first embodiment is exemplarily shown.
In the present embodiment, the buffer 4 is used for running an audio compiler to generate an audio signal with a preset frequency range, a uniform frequency interval and an analog sound effect according to the stored fetal heart signal and output the audio signal to the speaker 105;
the loudspeaker 105 is used for converting the audio signal into a sound signal with analog sound effect and playing the sound signal;
the core 5 is used to control the volume of the speaker 105, and controls the on and off states.
In specific application, the buffer can generate an audio signal with any simulation sound effect according to an audio compiler, and the simulation sound effect can simulate the tone of any sounding object according to the actual needs of a user and can also simulate the original fetal heartbeat sound.
In a specific application, the speaker may be an internal speaker or an external speaker of a fetal heart rate meter to which the fetal heart signal processing circuit is applied. When the loudspeaker is an external loudspeaker, the buffer is electrically connected with the loudspeaker through a matched audio interface, and the external loudspeaker is favorable for replacement and maintenance.
It should be understood that the fetal heart signal processing circuit and the fetal heart rate meter provided by the embodiment of the present invention inevitably further include a power supply circuit, a man-machine interaction device, a housing, a circuit board, etc., and the embodiment of the present invention is not specifically described in the embodiments of the present invention.
The above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. The fetal heart signal processing circuit is characterized by comprising a fetal heart signal acquisition device and a processor, wherein the processor comprises a first amplifying circuit, a sampling circuit, a memory, a buffer and an inner core which are integrated;
the fetal heart signal acquisition device is electrically connected with the first amplifying circuit and the kernel, the first amplifying circuit, the sampling circuit, the memory and the buffer are sequentially and electrically connected and are all electrically connected with the kernel, and an audio compiling program is solidified in the memory;
the fetal heart signal acquisition device acquires fetal heart signals;
the first amplifying circuit amplifies the fetal heart signals; the sampling circuit samples the amplified fetal heart signals;
the memory stores the sampled fetal heart signals;
the buffer runs the audio compiler to generate and output audio signals with a preset frequency range and frequency interval uniformity according to the stored fetal heart signals;
the core controls the working states of the fetal heart signal acquisition device, the first amplification circuit, the sampling circuit, the memory and the buffer.
2. A fetal heart signal processing circuit according to claim 1, wherein the fetal heart signal acquisition device comprises a piezo-ceramic sensor;
the piezoelectric ceramic sensor converts the ultrasonic Doppler signals into voltage signals to obtain the fetal heart signals.
3. The fetal heart signal processing circuit of claim 1, wherein the sampling circuit comprises an analog-to-digital converter;
and the analog-to-digital converter performs signal sampling in a preset frequency range on the amplified fetal heart signals to obtain the fetal heart signals in the preset frequency range and with uniform frequency intervals.
4. A fetal heart signal processing circuit according to claim 3 wherein the sampling accuracy of the analog to digital converter is 24 bits.
5. A fetal heart signal processing circuit according to claim 3 wherein the predetermined frequency range is 0Hz to 200 Hz.
6. The fetal heart signal processing circuit of claim 1, further comprising a filter circuit;
the filter circuit is electrically connected between the fetal heart signal acquisition device and the first amplifying circuit;
the filter circuit filters the fetal heart signal.
7. The fetal heart signal processing circuit of claim 1, further comprising a second amplification circuit;
the second amplifying circuit is electrically connected between the fetal heart signal acquisition device and the first amplifying circuit and is also electrically connected with the inner core;
the second amplifying circuit amplifies the fetal heart signal.
8. The fetal heart signal processing circuit of claim 1, wherein the processor is a single-chip microcomputer.
9. The fetal heart signal processing circuit of claim 1, further comprising a speaker;
the loudspeaker is electrically connected with the buffer and the inner core;
the buffer runs the audio compiler to generate audio signals with a preset frequency range, frequency interval uniformity and simulated sound effect according to the stored fetal heart signals and outputs the audio signals to the loudspeaker;
and the loudspeaker converts the audio signal into a sound signal with the analog sound effect and plays the sound signal.
10. A fetal heart rate apparatus comprising the fetal heart signal processing circuit of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920432065.1U CN210301052U (en) | 2019-03-29 | 2019-03-29 | Fetal heart signal processing circuit and fetal heart rate meter |
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| CN201920432065.1U CN210301052U (en) | 2019-03-29 | 2019-03-29 | Fetal heart signal processing circuit and fetal heart rate meter |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109925003A (en) * | 2019-03-29 | 2019-06-25 | 深圳市捷美瑞科技有限公司 | A kind of fetal heart rate signal processing circuit and heart rate meter for fetus |
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2019
- 2019-03-29 CN CN201920432065.1U patent/CN210301052U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109925003A (en) * | 2019-03-29 | 2019-06-25 | 深圳市捷美瑞科技有限公司 | A kind of fetal heart rate signal processing circuit and heart rate meter for fetus |
| CN109925003B (en) * | 2019-03-29 | 2024-09-27 | 深圳市捷美瑞科技有限公司 | Fetal heart signal processing circuit and fetal heart rate meter |
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