CN203855403U - Silicon-based photonic interconnection device - Google Patents
Silicon-based photonic interconnection device Download PDFInfo
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- CN203855403U CN203855403U CN201420037240.4U CN201420037240U CN203855403U CN 203855403 U CN203855403 U CN 203855403U CN 201420037240 U CN201420037240 U CN 201420037240U CN 203855403 U CN203855403 U CN 203855403U
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 71
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 58
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model discloses a silicon-based photonic interconnection device. A photonic device is communicated with a TSV (through-silicon via) deep hole through a first RDL (redistribution layer) and a second RDL; a first electronic device and a second electronic device are connected with the photonic device through a first convex point and a second convex point; through the connection of the TSV deep hole, a third RDL and a third convex point on the back surface, and a base plate, the base plate can be communicated with a CMOS (complementary metal oxide semiconductor)/photonic device on the front surface. An advanced CMOS chip can be mixed and integrated with various single-chip silicon-photon devices. The single-chip integration of a high-performance silicon-photon device on an SOI (silicon-on-insulator) substrate and the advanced manufacturing of a CMOS chip are ensured simultaneously, the high-performance silicon-photon device and the CMOS chip are allowed to be manufactured by using various most advanced and convenient processes, and a CMOS process is fully adopted, so that the cost can be further greatly reduced; the single-chip integrated silicon-photon device and the advanced CMOS chip complete ultra-short distance high-speed electrical interconnection through a TSV technology, and wideband silicon-photon interconnection is realized.
Description
Technical field
The utility model relates to microelectronics technology, relates in particular to a kind of manufacture method and silicon-based optical interconnection device of high-speed wideband silicon light keyset.
Background technology
In optical-electric module, mainly comprise two parts: opticator chip and coupling and control circuit.Wherein, photon chip mainly includes source and passive two kinds.Active electrooptic modulator (modulator), the photodetector (photodetector) of mainly comprising, passive device is mainly some multiplex/demultiplex (mux, demux) and optical waveguide etc.Electrical chip be mainly concerned with driving (Driver), the photodetector of electrooptic modulator amplifier (amplifiers of trans-impedance amplifier TIA or limiting amplifier LA or other types), also have some other coupling and control circuit, such as clock recovery (CDR), go here and there and change (Serdes), on-off circuit (Switches) etc.
At present mostly this class optical-electric module is to be integrated on pcb board, by discrete optical chip and with it the electrical chip of correspondence assemble respectively by the mode of wirebonding and flipchip.Although wherein wirebonding mode is easy to assembly, but because the problems such as loss, in high-frequency high-speed system, obvious these defects of RC delay and inductive effect make its application limited, the length that need to shorten as far as possible wirebonding gold thread reduces loss, in the following 100G system that even Tbit transmits, be almost difficult to application.The mode of flipchip is because adopt the mode of direct interconnection, can avoid significantly the loss of gold thread, but along with constantly dwindling of COMS chip technology node, and the circuit line width and the line-spacing difficulty that continue reduction PCB version are larger, the state of the art still rests on micron dimension, if the electrical chip that is packaging body is assembled on PCB substrate, obviously can increase cost and power consumption, be also unfavorable for that compact, miniaturization are integrated.
On the other hand, in the field of silica-based light delivery module, its development trend is that silicon based photon device and electricity chip are both directly printed on silicon wafer by traditional cmos process, the CPAK100G optical module of for example Cisco, also has IBM to adopt 90nm COMS technique that electricity and opticator (the silicon based photon device except laser instrument) are realized on sheet integrated.Complete the new technology of electricity and opticator for the ripe COMS technique of this employing simultaneously, a lot of companies and research team think that in design and volume production, having variety of issue occurs, for example Intel just thinks, according to the development of Moore's Law, the process node of COMS will certainly be more and more less, and the declaration meeting of 14nm Broadwell of Intel started to go into operation the first quarter in 2014.And for photonic device, its technique magnitude also rests on tens microns or hundreds of nanometer, the technique of this node is enough to ensure that the performance of existing optics realizes.The two has determined optics and electricity part to utilize COMS technique of the same race to complete in the unmatched development trend of process node, obviously improper, considers selection that neither be best from cost control.
Utility model content
The object of this part is to summarize some aspects of embodiment of the present utility model and briefly introduces some preferred embodiments.In this part and the application's specification digest and utility model title, may do a little simplification or omit to avoid the making object of this part, specification digest and utility model title fuzzy, and this simplification or omit and can not be used for limiting scope of the present utility model.
In view of the problem existing in above-mentioned and/or existing high-speed wideband silicon light keyset, the utility model is proposed.
Therefore, an object of the present utility model is to provide a kind of silicon-based optical interconnection device by TSV (Through-Silicon Via) technology, to form function silicon light keyset, the high-speed and high-density short distance that solves photonic device and advanced COMS electronic chip this key technical problem that interconnects.
For solving the problems of the technologies described above, the utility model provides following technical scheme:
For solving the problems of the technologies described above, the utility model provides following technical scheme: a kind of silicon-based optical interconnection device, comprise, the integrated Semiconductor substrate of photonic device, described Semiconductor substrate has front and back, in described Semiconductor substrate, be provided with photonic device, described photonic device has contact zone, on described contact zone, is formed with Metal Contact; Photonic device contact hole, Metal Contact interconnection in described photonic device contact hole and described Semiconductor substrate, and be disposed with barrier layer, Seed Layer and conducting metal by photonic device contact hole inwall to photonic device contact hole center, it is connected with the first salient point with a described RDL; TSV deep hole, described TSV deep hole is disposed with insulating barrier, barrier layer, Seed Layer and conducting metal by TSV inner walls of deep holes to TSV deep hole center, its one end is connected with the second salient point with the 2nd RDL in described front, and the other end is connected with the 3rd salient point with the 3rd RDL at the described back side; The first electronic device and described the first salient point form and are electrically connected; The second electronic device and described the second salient point form and are electrically connected.
As a kind of preferred version of silicon-based optical interconnection device described in the utility model, wherein: described Semiconductor substrate is SOI wafer, described SOI wafer comprises top silicon layer, silicon substrate, and being arranged at the oxide insulating layer between described top silicon layer and described silicon substrate, described SOI wafer has the first interarea and the second interarea.
As a kind of preferred version of silicon-based optical interconnection device described in the utility model, wherein: be also provided with on described top silicon layer, insulation material layer, in order to complete the manufacture of photonic device; Surface passivation layer, the refractive index of described surface passivation layer is less than the refractive index of silicon materials.
As a kind of preferred version of silicon-based optical interconnection device described in the utility model, wherein: described silicon-based optical interconnection device also comprises, substrate, described substrate is connected with described the 3rd salient point.
The utility model provides a kind of manufacture method and silicon-based optical interconnection device of high-speed wideband silicon light keyset, and compared with prior art, its beneficial effect is:
(1) save the independent manufacture of photon chip in optical-electric module, aim at respectively, installation step one by one; And then realization silicon based photon device monolithic integrated technique on SOI wafer;
(2) fully use CMOS technique and complete the manufacture of electronic chip, and then significantly reduce photoelectricity and mix integrated cost;
(3) can reduce module size, increase the port density of optical network device, reduce power consumption;
(4) utilize TSV (Through-Silicon Via) technology, in the enterprising hole and connecting up again of working of the Silicon photonics wafer that completes the sub-device of the integrated active passive light of monolithic, for optical chip and control chip thereof provide very-short-reach electric interconnection, can improve integration density, reduce the impact of interconnection line on high-frequency high-speed;
(5) RDL on SOI wafer is more suitable for the advanced COMS electrical chip that assembly performance is higher, technology node constantly dwindles;
(6) on applicable sheet, photoelectricity three-dimensional is integrated; Realize supercomputing, the transmission of high-speed wideband signal.
Brief description of the drawings
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1～Figure 11 is the schematic diagram of the product that obtains of each step of the manufacture method of a kind of high-speed wideband silicon light keyset described in the utility model;
Figure 12～Figure 19 is the schematic diagram of the product that obtains of each step of the manufacture method of the Semiconductor substrate of integrated photonic device described in the utility model;
Figure 20 is by the structural representation of Metal Contact described in lithographic definition in the utility model;
Figure 21 is the schematic diagram that the planarization of CMP technique obtains product;
Figure 22 is the structural representation that ephemeral key synthetic circle support plate obtains product;
Figure 23 is connected the 3rd salient point and obtains the structural representation of product with substrate;
Figure 24 is the schematic flow sheet of the manufacture method of high-speed wideband silicon light keyset described in the utility model;
Meanwhile, wherein,
Figure 11 is the generalized section of an embodiment of silicon-based optical interconnection device described in the utility model;
Figure 23 is the generalized section of another embodiment of silicon-based optical interconnection device described in the utility model.
Detailed description of the invention
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, detailed description of the invention of the present utility model is described in detail.
A lot of details are set forth in the following description so that fully understand the utility model, but the utility model can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization without prejudice to the utility model intension in the situation that, and therefore the utility model is not subject to the restriction of following public specific embodiment.
Secondly, the utility model is described in detail in conjunction with schematic diagram, in the time that the utility model embodiment is described in detail in detail; for ease of explanation; represent that the profile of device architecture can disobey general ratio and do local amplification, and described schematic diagram is example, it should not limit the scope of the utility model protection at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.
The manufacture method 700 that the utility model proposes a kind of high-speed wideband silicon light keyset, please refer to shown in Figure 24, and this manufacture method comprises the steps.
Step 710, first provides one to realize the single chip integrated Semiconductor substrate of photonic device, and described Semiconductor substrate has front and back, is provided with photonic device on it, and described photonic device has contact zone, on described contact zone, is formed with Metal Contact.
Concrete, as shown in Figure 1, describedly provide one to realize the single chip integrated Semiconductor substrate of photonic device, in fact be to provide one and realized the single chip integrated Semiconductor substrate of photonic device, on photonic device 100 or around contact zone 101 is set, be ion doped region, the meeting of described ion doped region and thin metal layer form metal silicide, form Metal Contact 102 on contact zone 101.Described photonic device 100 can be silicon electrooptic modulator and/or silicon/germanium photodetector and/or array waveguide grating; Or the photonic device of other process compatibles in addition, the silicon based photon devices such as such as taper end face waveguide.
And in another embodiment, the described integrated Semiconductor substrate of photonic device, can make by following technique, referring to Figure 12～Figure 19 and Fig. 1:
D1: as shown in figure 12, described Semiconductor substrate adopts SOI wafer, and it has comprised top silicon layer 10, silicon substrate 30, and being arranged at the oxide insulating layer 20 between described top silicon layer 10 and described silicon substrate 30, described SOI wafer has the first interarea and the second interarea.
D2: referring to Figure 13, by series of standards semiconductor technologies such as photoetching, etching, vapour deposition, cycle annealing, Implantation, metallization, on described top silicon layer 10, insulation material layer 40 completes the manufacture of photonic device 100, and described photonic device 100 has contact zone 101.The refractive index of insulation material layer 40 is less than the refractive index of silicon, forms the top covering of array waveguide grating, germanium photodetector, germanium/silicon electrooptic modulator, participates in optical mode field design in photon link.
In this embodiment, germanium photodetector is integrated on described insulation material layer 40, the active area of described germanium photodetector is served as by germanium material, germanium material on described silicon substrate can pass through high vacuum chemical vapour deposition (UHV-CVD), the method selective epitaxials such as molecular beam epitaxy (MBE), or pass through bonding body germanium material to silicon substrate, especially, in order to obtain better device performance, can carry out cycle annealing to germanium material, simultaneously or according to a definite sequence, array waveguide grating (AWG) and silicon electrooptic modulator are integrated on described top silicon layer 10.
D3: be formed with Metal Contact on described contact zone, as shown in Figure 14～Figure 17, first the SOI wafer of preliminary integrated photonic device 100 in D2 technique coated to photoresist, then carry out photoetching, etch preliminary contact hole 60, then resist coating again, to define metal contact layer; Then, photoetching, plated metal thin layer, Lift-off plated metal thin layer, short annealing forms Metal Contact 102, and in this embodiment, described Metal Contact 102 is metallic silicon/germanide.
D4: deposition-etch stop-layer in described Metal Contact (Etch stop layer), on described Metal Contact, be formed with etching stop layer, as one can exemplifying embodiment, etching stop layer can be silicon nitride; As shown in figure 18, chemical wet etching again, forms thin etching stop layer 103 on Metal Contact 102 surfaces, in order not affect this Semiconductor substrate optical transmission performance, the refractive index of etching stop layer 103 is less than the refractive index of silicon materials, for example, can be the nitride of silicon.
D5: form the surface passivation layer that can not affect described Semiconductor substrate optical transmission performance on described the first interarea and etching stop layer, referring to Figure 19, and then, on described the first interarea and etching stop layer 103, form the surface passivation layer 70 that can not affect described Semiconductor substrate optical transmission performance, and the refractive index of surface passivation layer 70 is less than the refractive index of silicon materials, in this embodiment, surface passivation layer 70 is silica.
D6: referring to Figure 19 and Fig. 1, last, formed surface passivation layer 70 is carried out to planarization, the accomplished single chip integrated Semiconductor substrate of photonic device 100.
After all photonic device manufactures complete, be to ensure device stability, subsequent technique need to carry out under temperature is no more than the condition of 400 DEG C.
Step 720, forms TSV deep hole from the front of described Semiconductor substrate to the back side.
As shown in Figure 2, and in conjunction with Figure 19, until a part for silicon substrate 30, form described TSV(Through-Silicon Via through surface passivation layer 70, insulation material layer 40, top silicon layer 10 and the oxide insulating layer 20 of photoetching successively etching top layer) deep hole 200.
Step 730, depositing insulating layer in described front and described TSV deep hole.
As shown in Figure 3, pass through TEOS(tetra-ethyl-ortho-silicate) process deposits insulating barrier 201, with the front of the Semiconductor substrate that insulated and the inner wall surface of TSV deep hole 200.
Step 740, the photonic device contact hole of the Metal Contact interconnection in formation and described Semiconductor substrate.
As shown in Figure 4 and referring to Figure 20, in the time forming photonic device contact hole 300, by the position of Metal Contact described in lithographic definition 102, etching insulating barrier 201, surface passivation layer 70 successively, then adjust etching technics and etch away very thin etching stop layer 103, the photonic device contact hole 300 that the Metal Contact 102 in formation and described Semiconductor substrate interconnects.
Step 750, on insulating barrier and with the photonic device contact hole of Metal Contact interconnection in deposit and spread barrier layer and Seed Layer, and in positive and described photonic device contact hole and TSV deep hole filled conductive metal.
As shown in Fig. 5～Fig. 7, first on insulating barrier 201 and the interior deposit and spread of photonic device contact hole 300 barrier layer 301, then deposit and spread Seed Layer 302 on 301 surfaces, described barrier layer, finally filled conductive metal in front and photonic device contact hole 300 and TSV deep hole 200, in this embodiment, the conducting metal of filling can be copper or tungsten etc., and mode can be plated metal copper or chemical vapor deposition (CVD) tungsten.
Step 760, described positive form with described photonic device contact hole in conductive gold the symbolic animal of the birth year RDL and the first salient point that are electrically connected, and the 2nd RDL and the second salient point that are electrically connected with the conductive gold symbolic animal of the birth year in described TSV deep hole.
As shown in Figure 8, referring to Figure 21, by CMP(Chemical Mechanical Planarization, chemical-mechanical planarization) technique, remove barrier layer 301, Seed Layer 302 and conducting metal planarization positive in step 750, insulating materials flatening process, can improve the difference in height between photonic device on photonic device manufacture Semiconductor substrate the first interarea afterwards; Then, successively described positive form with described photonic device contact hole 300 in and with described TSV deep hole 200 in a RDL411 and first salient point 421 of conductive gold symbolic animal of the birth year electric connection, and with described TSV deep hole 200 in conductive gold symbolic animal of the birth year be electrically connected the 2nd RDL412 and the second salient point 422, and no matter a RDL411 or the 2nd RDL412, its number of plies decides according to concrete I/O number, can be but be not limited to one deck or two-layer.
Step 770, starts described in attenuate Semiconductor substrate until expose the conducting metal of described TSV deep hole from the described back side.
As shown in figure 22, in the time carrying out technique for thinning back side, also first bonding wafer support plate in the time being faced with, to ensure overall thickness, then described in attenuate, Semiconductor substrate until expose the conducting metal of described TSV deep hole 200, is convenient to form the electric connection at the back side, as shown in Figure 9.
Step 780, the 3rd RDL and the 3rd salient point that are electrically connected in the formation of the described back side and the conductive gold symbolic animal of the birth year in described TSV deep hole.
As shown in figure 10, overleaf form with described TSV deep hole 200 in conductive gold symbolic animal of the birth year be electrically connected the 3rd RDL413 and the 3rd salient point 423.Certainly, if in step 770, first bonding wafer support plate in the time being faced with, forms in this step 780 after the 3rd RDL413 and the 3rd salient point 423 of conductive gold symbolic animal of the birth year electric connection, through removing interim bonding, getting rid of described wafer support plate, cleaning, do not tire out and state at this.
Step 790, is connected described the first salient point, the second salient point respectively with the first electronic device, the second electronic device.
As shown in figure 11, referring to Figure 10, lose money instead of making money electrical chip by section, front, the first salient point 421, the second salient point 422 are connected with the first electronic device 500 and the second electronic device 600 respectively, complete silicon-based optical interconnection device.In this technique, a RDL411 and the 2nd RDL412 link up photonic device and TSV deep hole 200, and the first electronic device 500 and the second electronic device 600 are connected with photonic device by the first salient point 421, the second salient point 422.
Certainly, after the first salient point 421, the second salient point 422 are connected with the first electronic device 500 and the second electronic device 600 respectively, then the 3rd salient point 423 is connected with substrate, is accomplished to the assembling of substrate.As shown in figure 23, and referring to Figure 10, Figure 11, in this technique, be connected with substrate by TSV deep hole 200, the 3rd RDL413 and the 3rd salient point 423, realize the communication of the first electronic device 500, the second electronic device 600 and the photonic device in substrate and front.
The utility model also provides a kind of silicon-based optical interconnection device, in one embodiment, referring to Fig. 1～Figure 11, it has comprised, has realized the single chip integrated Semiconductor substrate of photonic device 100, and described Semiconductor substrate has front and back, in described Semiconductor substrate, be provided with photonic device 100, described photonic device 100 has contact zone 101, on described contact zone 101, is formed with Metal Contact 102, and described photonic device can comprise active device and/or passive device; Photonic device contact hole 300, the Metal Contact 102 in its Semiconductor substrate interconnects, and by its inwall wherein the heart be disposed with barrier layer 301, Seed Layer 302 and conducting metal, and be connected with the first salient point 421 with a described RDL411; Especially, described photonic device 100, the passive devices such as the silicon array waveguide optical grating (AWG) of containing, also can comprise above-mentioned Metal Contact, barrier layer, Seed Layer etc. and conducting metal (not shown) thereof, and can complete electricity wiring by RDL and salient point, to realize external electrical control, such as heating electrode.TSV deep hole 200, by its inwall wherein the heart be disposed with insulating barrier 201, barrier layer 301, Seed Layer 302 and conducting metal, its one end is connected with the second salient point 422 with the 2nd RDL412 in described front, and the other end is connected with the 3rd salient point 423 with the 3rd RDL413 at the described back side; This silicon-based optical interconnection device also comprises, the first electronic device 500 and the second electronic device 600, the first electronic devices 500 and described the first salient point 411 formation electric connections, and the second electronic device 600 forms and is electrically connected with described the second salient point 412.
In another embodiment, referring to Fig. 1～Figure 11 and Figure 23, be connected with substrate by the 3rd salient point 423, be accomplished to the assembling of substrate, therefore silicon-based optical interconnection device has also comprised substrate.
Semiconductor substrate can adopt and comprise top silicon layer 10, silicon substrate 30, and be arranged at the silicon-on-insulator of the oxide insulating layer 20 between described top silicon layer 10 and described silicon substrate 30.
It should be noted that, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although the utility model is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the technical solution of the utility model, and not departing from the spirit and scope of technical solutions of the utility model, it all should be encompassed in the middle of claim scope of the present utility model.
Claims (4)
1. a silicon-based optical interconnection device, is characterized in that: comprises,
The integrated Semiconductor substrate of photonic device, described Semiconductor substrate has front and back, in described Semiconductor substrate, is provided with photonic device, and described photonic device has contact zone, on described contact zone, is formed with Metal Contact;
Photonic device contact hole, Metal Contact interconnection in described photonic device contact hole and described Semiconductor substrate, and be disposed with barrier layer, Seed Layer and conducting metal by photonic device contact hole inwall to photonic device contact hole center, it is connected with the first salient point with a described RDL;
TSV deep hole, described TSV deep hole is disposed with insulating barrier, barrier layer, Seed Layer and conducting metal by TSV inner walls of deep holes to TSV deep hole center, its one end is connected with the second salient point with the 2nd RDL in described front, and the other end is connected with the 3rd salient point with the 3rd RDL at the described back side;
The first electronic device and described the first salient point form and are electrically connected;
The second electronic device and described the second salient point form and are electrically connected.
2. silicon-based optical interconnection device according to claim 1, is characterized in that:
Described Semiconductor substrate is SOI wafer, described SOI wafer comprises top silicon layer, silicon substrate, and be arranged at the oxide insulating layer between described top silicon layer and described silicon substrate, described SOI wafer has the first interarea and the second interarea.
3. silicon-based optical interconnection device according to claim 2, is characterized in that: on described top silicon layer, is also provided with,
Insulation material layer, in order to complete the manufacture of photonic device;
Surface passivation layer, the refractive index of described surface passivation layer is less than the refractive index of silicon materials.
4. silicon-based optical interconnection device according to claim 1, is characterized in that: described silicon-based optical interconnection device also comprises,
Substrate, described substrate is connected with described the 3rd salient point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420037240.4U CN203855403U (en) | 2014-01-21 | 2014-01-21 | Silicon-based photonic interconnection device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420037240.4U CN203855403U (en) | 2014-01-21 | 2014-01-21 | Silicon-based photonic interconnection device |
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| CN201420037240.4U Expired - Lifetime CN203855403U (en) | 2014-01-21 | 2014-01-21 | Silicon-based photonic interconnection device |
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| CN103787268A (en) * | 2014-01-21 | 2014-05-14 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing high-speed broadband silicon light adapter plate, and silicon-based optical interconnection device |
| CN105022127A (en) * | 2014-04-16 | 2015-11-04 | 苹果公司 | Active silicon optical bench |
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