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CN203300637U - Semiconductor encapsulating body - Google Patents

Semiconductor encapsulating body Download PDF

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Publication number
CN203300637U
CN203300637U CN2013200031509U CN201320003150U CN203300637U CN 203300637 U CN203300637 U CN 203300637U CN 2013200031509 U CN2013200031509 U CN 2013200031509U CN 201320003150 U CN201320003150 U CN 201320003150U CN 203300637 U CN203300637 U CN 203300637U
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substrate
semiconductor package
pad
metal layer
semiconductor
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严柱阳
郑润载
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QUICK KOREA SEMICONDUCTOR CO Ltd
Fairchild Korea Semiconductor Ltd
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QUICK KOREA SEMICONDUCTOR CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor encapsulating body includes a substrate which has insulation performance and includes a ceramic material, a metal layer which is arranged on the substrate, a chip pad which is arranged on the metal layer, a bonding layer which is used for connecting the metal layer with the chip pad, and a semiconductor chip which is arranged on the top surface of the chip pad so as to be electrically connected to the chip pad.

Description

半导体封装体semiconductor package

相关申请的交叉引用Cross References to Related Applications

本申请要求在2012年1月6日向韩国知识产权局递交的韩国实用新型申请10-2012-0000159的优先权，其公开内容通过引用全部并入本文中。This application claims priority from Korean Utility Model Application No. 10-2012-0000159 filed with the Korean Intellectual Property Office on Jan. 6, 2012, the disclosure of which is incorporated herein by reference in its entirety.

技术领域 technical field

本实用新型涉及一种半导体封装体，且更具体地，涉及一种包括在其上装载半导体芯片的衬底的半导体封装体。The utility model relates to a semiconductor package, and more particularly, to a semiconductor package including a substrate on which a semiconductor chip is mounted.

背景技术 Background technique

由于近来电子装置具有高速、大容量和小型化性能，所以半导体封装体的集成化提高。因此，对于在半导体封装体中有效地使相邻装置电绝缘的结构和制造方法进行了研究。还对能够有效地释放由半导体封装体产生的热量的结构和制造方法存在增长的需求。Since electronic devices have high speed, large capacity, and miniaturization performance recently, the integration of semiconductor packages has increased. Accordingly, research has been conducted on structures and manufacturing methods that effectively electrically isolate adjacent devices in semiconductor packages. There is also a growing need for structures and fabrication methods that can efficiently dissipate heat generated by semiconductor packages.

实用新型内容 Utility model content

本实用新型提供了一种具有改进可靠性的半导体封装体。The utility model provides a semiconductor packaging body with improved reliability.

根据本实用新型的一方面，提供了一种半导体封装体，包括：衬底，所述衬底具有绝缘性能，并且包括陶瓷材料；金属层，所述金属层设置在所述衬底上；芯片焊盘(die paddle)，所述芯片焊盘设置在所述金属层上；粘合层，所述粘合层用于连接所述金属层和所述芯片焊盘；以及半导体芯片，所述半导体芯片设置在所述芯片焊盘的顶表面上以电连接到所述芯片焊盘。According to an aspect of the present invention, a semiconductor package is provided, including: a substrate, the substrate has insulating properties, and includes a ceramic material; a metal layer, the metal layer is disposed on the substrate; a chip a die paddle, the die paddle is disposed on the metal layer; an adhesive layer, the adhesive layer is used to connect the metal layer and the die paddle; and a semiconductor chip, the semiconductor A chip is disposed on the top surface of the die pad to be electrically connected to the die pad.

所述粘合层可以由焊料材料形成。The adhesive layer may be formed of a solder material.

所述金属层可以与所述衬底接触，并且从所述衬底的边缘向内设置预定长度。The metal layer may be in contact with the substrate and disposed inwardly from an edge of the substrate by a predetermined length.

所述半导体封装体还可以包括密封构件，所述密封构件围绕所述半导体芯片和所述芯片焊盘，并且用于使所述衬底的下表面暴露。The semiconductor package may further include a sealing member surrounding the semiconductor chip and the die pad and exposing a lower surface of the substrate.

所述半导体封装体可以包括多个所述衬底，并且所述衬底通过在它们之间插入所述密封构件而彼此隔开设置。The semiconductor package may include a plurality of the substrates, and the substrates are spaced apart from each other by interposing the sealing member therebetween.

所述半导体封装体还可以包括连接到所述芯片焊盘的引线。The semiconductor package may further include leads connected to the die pad.

附图说明 Description of drawings

由以下结合附图的详细说明，将更清楚地理解本实用新型的示例性实施方式，其中：From the following detailed description in conjunction with the accompanying drawings, the exemplary embodiments of the present utility model will be more clearly understood, wherein:

图1是根据本实用新型的实施方式的半导体封装体的透视图；1 is a perspective view of a semiconductor package according to an embodiment of the present invention;

图2是图1的半导体封装体的横截面图；2 is a cross-sectional view of the semiconductor package of FIG. 1;

图3是图1的半导体封装体的仰视图；3 is a bottom view of the semiconductor package of FIG. 1;

图4A至4D是用于描述制造图1的半导体封装体的方法的横截面图；以及4A to 4D are cross-sectional views for describing a method of manufacturing the semiconductor package of FIG. 1; and

图5是根据本实用新型的另一实施方式的半导体封装体的横截面图。5 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

具体实施方式 Detailed ways

现在将参照其中示出本实用新型示例性实施方式的附图，更充分地描述本实用新型。然而，本实用新型可以包含在许多不同形式中，并且不应该解释为限制在本文中阐述的实施方式；更确切地，提供这些实施方式，使得本实用新型内容将是全面和完整的，并且充分将本实用新型的构思传达给本领域的普通技术人员。The invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully To convey the concept of the present utility model to those of ordinary skill in the art.

同样，由于例如制造技术和/或偏差的原因，预计可能会发生与图示形状的偏离。因此，本实用新型的实施方式不应该解释为限制本文中示出区域的具体形状，而是包括例如由于制造导致的形状上的误差。在图中，相同的附图标记表示相同的元件。此外，图中示意性地示出了不同的元件和区域。因此，本实用新型不限于在图中示出的相对尺寸和间隔。在本文中使用的术语“和/或”包括一个或多个相关列出项目的任一和全部组合。Also, deviations from the illustrated shapes are expected to occur due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. In the figures, the same reference numerals denote the same elements. Furthermore, different elements and regions are schematically shown in the figures. Accordingly, the invention is not limited to the relative sizes and spacings shown in the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

图1是根据本实用新型实施方式的半导体封装体1000的透视图。图2是沿着图1的线II-II′获得的半导体封装体1000的横截面图。FIG. 1 is a perspective view of a semiconductor package 1000 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor package 1000 taken along line II-II' of FIG. 1 .

虽然出于方便说明的原因，在图1中省略了用于保护内部构件的模制构件(molding member)180，但是在图2中示出了模制构件180。Although a molding member 180 for protecting internal members is omitted in FIG. 1 for convenience of illustration, the molding member 180 is shown in FIG. 2 .

参照图1和图2，半导体封装体1000包括衬底100a和100b，多个金属层110、多个芯片焊盘135和第一半导体芯片160a至第四半导体芯片160d。半导体封装体1000还包括多根第一引线130、第二引线140、多根导线170(第一导线至第五导线171、173、175、177和179)和模制构件180。1 and 2, a semiconductor package 1000 includes substrates 100a and 100b, a plurality of metal layers 110, a plurality of die pads 135, and first to fourth semiconductor chips 160a to 160d. The semiconductor package 1000 also includes a plurality of first leads 130 , a second lead 140 , a plurality of wires 170 (first to fifth wires 171 , 173 , 175 , 177 , and 179 ), and a molding member 180 .

衬底100a和100b可以由陶瓷材料形成。衬底100a和100b可以包括例如Al2O3、AlN、SiO2或BeO。衬底100a和100b的下表面可以用作辐射表面。或者，附加的散热器(未示出)还可以设置在衬底100a和100b的下表面上。The substrates 100a and 100b may be formed of a ceramic material. The substrates 100a and 100b may include, for example, Al 2 O 3 , AlN, SiO 2 or BeO. The lower surfaces of the substrates 100a and 100b may serve as radiation surfaces. Alternatively, additional heat sinks (not shown) may also be provided on the lower surfaces of the substrates 100a and 100b.

金属层110分别形成在衬底100a和100b上。金属层110可以分别从衬底100a和100b的边缘向内形成第一方向上的第一长度L1和第二方向上的第二长度L2。第一长度L1可以与第二长度L2相同或相似。或者，第一长度L1可以为0。换句话说，金属层110可以向内形成其中衬底100a和100b彼此相邻的第二方向上的第二长度L2，并且可以形成在第一方向上具有与衬底100a和100b相同的宽度。金属层110还可以用于辐射由第一半导体芯片至第三半导体芯片160a、160b和160d产生的热量。Metal layers 110 are formed on the substrates 100a and 100b, respectively. The metal layer 110 may form a first length L1 in a first direction and a second length L2 in a second direction inwardly from the edges of the substrates 100a and 100b, respectively. The first length L1 may be the same as or similar to the second length L2. Alternatively, the first length L1 may be zero. In other words, the metal layer 110 may be formed inwardly by the second length L2 in the second direction in which the substrates 100a and 100b are adjacent to each other, and may be formed to have the same width as the substrates 100a and 100b in the first direction. The metal layer 110 may also serve to radiate heat generated by the first to third semiconductor chips 160a, 160b, and 160d.

第一半导体芯片160a和第二半导体芯片160b通过芯片粘合层150安装在芯片焊盘135上。芯片粘合层150可以由例如金属性环氧树脂或焊料材料形成。第一半导体芯片160a至第四半导体芯片160d的大小和数量不限于图1中示出的那些大小和数量，并且可以以不同方式进行修改。The first semiconductor chip 160 a and the second semiconductor chip 160 b are mounted on the die pad 135 through the die bonding layer 150 . The die attach layer 150 may be formed of, for example, metallic epoxy or solder material. The sizes and numbers of the first to fourth semiconductor chips 160a to 160d are not limited to those shown in FIG. 1 and may be variously modified.

第一半导体芯片160a至第四半导体芯片160d可以彼此连接，和/或经由导线170电连接到引线130和引线140。导线170可以经由第一半导体芯片160a至第四半导体芯片160d与引线130和140上的接触点(未示出)而传输电信号。The first to fourth semiconductor chips 160 a to 160 d may be connected to each other and/or electrically connected to the leads 130 and 140 via wires 170 . The wire 170 may transmit electrical signals via the first to fourth semiconductor chips 160 a to 160 d and contact points (not shown) on the leads 130 and 140 .

第一半导体芯片160a至第四半导体芯片160d可以包括功率装置和/或控制装置。功率装置可以适用于电动机驱动装置、功率变换器、整流器、功率因数校正(PFC)或显示驱动装置。然而，本实用新型的范围不限于此。或者，第一半导体芯片160a至第四半导体芯片160d可以包括有源装置。例如，该有源装置可以包括选自金属氧化物半导体场效应晶体管(MOSFET)、绝缘栅双极晶体管(IGBT)和二极管，或其组合的装置。The first to fourth semiconductor chips 160a to 160d may include power devices and/or control devices. The power unit may be suitable for motor drives, power converters, rectifiers, power factor correction (PFC) or display drives. However, the scope of the present invention is not limited thereto. Alternatively, the first to fourth semiconductor chips 160a to 160d may include active devices. For example, the active device may comprise a device selected from a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a diode, or a combination thereof.

具体地，第三半导体芯片160c可以包括控制装置，并且可以安装在与芯片焊盘135隔开的子芯片焊盘145上以减少或抑制在第三半导体芯片160c与第一半导体芯片160a和第二半导体芯片160b之间可能产生的热交流(cross talking)。或者，可使用与第二引线140分离的控制装置的分离衬底代替子芯片焊盘145。Specifically, the third semiconductor chip 160c may include a control device, and may be mounted on the sub-chip pad 145 spaced apart from the chip pad 135 to reduce or suppress interference between the third semiconductor chip 160c and the first semiconductor chip 160a and the second semiconductor chip 160c. possible heat exchange (cross talking) between the semiconductor chips 160b. Alternatively, instead of the chiplet pad 145 , a separate substrate of the control device separate from the second lead 140 may be used.

芯片焊盘135可以从第一引线130延伸以形成为一体。子芯片焊盘145可以从第二引线140延伸以形成为一体。引线130和140由引线架(未示出)提供，并且将第一半导体芯片160a至第四半导体芯片160d连接到外电路。虽然仅在图1和图2中示出了两根第一引线130和一根第二引线140，但是可以设置更多数量的引线130和140。The die pad 135 may extend from the first lead 130 to be integrally formed. The sub-chip pad 145 may extend from the second lead 140 to be integrally formed. The leads 130 and 140 are provided by a lead frame (not shown), and connect the first to fourth semiconductor chips 160a to 160d to an external circuit. Although only two first leads 130 and one second lead 140 are shown in FIGS. 1 and 2 , a greater number of leads 130 and 140 may be provided.

芯片焊盘135分别经由焊盘粘合层120连接到设置在衬底100a和100b上的金属层110。焊盘粘合层120可以例如由焊料材料形成。或者，焊盘粘合层120可以由导热的环氧树脂或含硅弹性体形成。当焊盘粘合层120由焊料材料形成时，芯片焊盘135可以分别通过焊接过程连接到衬底100a和100b。就这一点而言，芯片焊盘135还可以经由金属层110容易地连接到衬底100a和100b。如果芯片焊盘135通过焊接过程附接到衬底100a和100b上，则芯片焊盘135与衬底100a和100b之间的附着力相对较强，因此防止其间的脱离现象。The die pads 135 are connected to the metal layers 110 provided on the substrates 100 a and 100 b via the pad adhesive layers 120 , respectively. The pad adhesive layer 120 may be formed of, for example, a solder material. Alternatively, the pad adhesive layer 120 may be formed of thermally conductive epoxy or silicon-containing elastomer. When the pad adhesive layer 120 is formed of a solder material, the chip pads 135 may be connected to the substrates 100a and 100b through a soldering process, respectively. In this regard, the die pad 135 can also be easily connected to the substrates 100 a and 100 b via the metal layer 110 . If the die pad 135 is attached to the substrates 100a and 100b through a soldering process, the adhesion between the die pad 135 and the substrates 100a and 100b is relatively strong, thus preventing a detachment phenomenon therebetween.

此外，如上所述，由于金属层110从衬底100a和100b的边缘向内形成，所以在焊接过程期间不会在相邻芯片焊盘135之间产生由焊盘粘合层120形成的桥。In addition, as described above, since the metal layer 110 is formed inwardly from the edges of the substrates 100a and 100b, a bridge formed by the pad adhesive layer 120 is not generated between adjacent chip pads 135 during the bonding process.

模制构件180部分地密封第一半导体芯片160a至第四半导体芯片160d、芯片焊盘135、子芯片焊盘145以及引线130和140。第一引线130和第二引线140可以从模制构件180伸出。模制构件180可以形成为填充衬底100a与100b之间的空间，并且使衬底100a和100b的下表面暴露。模制构件180可以由例如环氧塑封料(EMC)形成。The molding member 180 partially seals the first to fourth semiconductor chips 160 a to 160 d , the die pad 135 , the sub-chip pad 145 , and the leads 130 and 140 . The first lead 130 and the second lead 140 may protrude from the molding member 180 . The molding member 180 may be formed to fill a space between the substrates 100a and 100b and expose lower surfaces of the substrates 100a and 100b. The molding member 180 may be formed of, for example, epoxy molding compound (EMC).

图3是图1半导体封装体1000的仰视图。FIG. 3 is a bottom view of the semiconductor package 1000 of FIG. 1 .

在图3中，与图1和图2中相同的附图标记表示相同的部件，因此将省略其重复说明。In FIG. 3 , the same reference numerals as in FIGS. 1 and 2 denote the same components, and thus repeated description thereof will be omitted.

参照图3，半导体封装体1000可以包括多个包含图1和图2中示出衬底100a和100b的衬底100a、100b、100c、100d和100e。衬底100a、100b、100c、100d和100e的各个下表面从模制构件180暴露到外部。衬底100a、100b、100c、100d和100e可以通过模制构件180彼此隔开。Referring to FIG. 3 , a semiconductor package 1000 may include a plurality of substrates 100 a , 100 b , 100 c , 100 d , and 100 e including the substrates 100 a and 100 b shown in FIGS. 1 and 2 . The respective lower surfaces of the substrates 100 a , 100 b , 100 c , 100 d and 100 e are exposed to the outside from the molding member 180 . The substrates 100 a , 100 b , 100 c , 100 d , and 100 e may be separated from each other by a molding member 180 .

因此，设置在衬底100a、100b、100c、100d和100e之上的芯片焊盘135(参见图1和图2)可以彼此电绝缘，因此防止在相邻芯片焊盘135之间发生短路，并且有助于辐射由第一半导体芯片160a至第四半导体芯片160d产生的热量。因此，可以提供具有改进可靠性的半导体封装体1000。Accordingly, the die pads 135 (see FIGS. 1 and 2 ) disposed over the substrates 100a, 100b, 100c, 100d, and 100e can be electrically insulated from each other, thus preventing short circuits from occurring between adjacent die pads 135, and Helps to radiate heat generated from the first to fourth semiconductor chips 160a to 160d. Accordingly, the semiconductor package 1000 having improved reliability may be provided.

图4A至4D是用于描述制造图1半导体封装体的方法的横截面图。4A to 4D are cross-sectional views for describing a method of manufacturing the semiconductor package of FIG. 1 .

参照图4A，半导体芯片160a和160b经由芯片粘合层150安装在芯片焊盘135上。而且，半导体芯片160c经由芯片粘合层150安装在子芯片焊盘145上。芯片焊盘135和子芯片焊盘145可以为分别从第一引线130和第二引线140伸出的部分。芯片焊盘135和子芯片焊盘145可以由例如铜(Cu)形成，并且可以形成为包括两种或更多种金属的多层。芯片粘合层150可以包括导电材料，例如金属性环氧树脂或焊料材料。Referring to FIG. 4A , semiconductor chips 160 a and 160 b are mounted on the die pad 135 via the die bonding layer 150 . Also, the semiconductor chip 160 c is mounted on the sub-chip pad 145 via the die bonding layer 150 . The die pad 135 and the sub-die pad 145 may be portions protruding from the first lead 130 and the second lead 140 , respectively. The die pad 135 and the sub-die pad 145 may be formed of, for example, copper (Cu), and may be formed as a multilayer including two or more metals. The die attach layer 150 may include a conductive material such as metallic epoxy or solder material.

参照图4B，金属层110形成在衬底100a上。可以通过诸如溅射的物理气相沉积(PVD)或化学气相沉积(CVD)形成金属层110。但是关于金属层110的制造方法不限于此。金属层110与衬底100a的边缘隔开预定距离，以形成在衬底100a的中央部分上。Referring to FIG. 4B, a metal layer 110 is formed on a substrate 100a. The metal layer 110 may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD) such as sputtering. However, the method of manufacturing the metal layer 110 is not limited thereto. The metal layer 110 is spaced a predetermined distance from the edge of the substrate 100a to be formed on the central portion of the substrate 100a.

接下来，在金属层110上形成焊盘粘合层120。例如，可以通过印刷焊料浆体形成焊盘粘合层120。Next, a pad adhesive layer 120 is formed on the metal layer 110 . For example, the pad adhesive layer 120 may be formed by printing solder paste.

参照图4C，实施用于经由焊盘粘合层120将芯片焊盘135附接在金属层110上的回流过程。因此，芯片焊盘135可以经由金属层110连接到衬底100a。Referring to FIG. 4C , a reflow process for attaching the chip pad 135 on the metal layer 110 via the pad adhesive layer 120 is performed. Accordingly, the die pad 135 may be connected to the substrate 100 a via the metal layer 110 .

接下来，可以实施用于去除在焊盘粘合层120内由助焊剂(flux)产生的残留物的清洗过程。助焊剂是包括在焊料浆体中用于防止氧化物形成的添加剂。Next, a cleaning process for removing residues generated by flux within the pad adhesive layer 120 may be performed. Fluxes are additives included in solder pastes to prevent oxide formation.

参照图4D，通过使用导线170(即，第一导线至第四导线171、173、175和177)实施用于将半导体芯片160a、160b和160c与引线130和140电连接的丝焊法。Referring to FIG. 4D , a wire bonding method for electrically connecting the semiconductor chips 160 a , 160 b and 160 c with the leads 130 and 140 is performed by using the wires 170 (ie, first to fourth wires 171 , 173 , 175 and 177 ).

接下来，参照图1和图2，实施用于形成模制构件180的过程，该模制构件180部分地密封半导体芯片160a、160b和160c、芯片焊盘135、子芯片焊盘145以及引线130和140。就这一点而言，模制构件180不形成在衬底100a的下表面上，从而使衬底100a的下表面暴露。Next, referring to FIGS. 1 and 2, a process for forming a molding member 180 that partially seals the semiconductor chips 160a, 160b, and 160c, the die pads 135, the sub-chip pads 145, and the leads 130 is implemented. and 140. In this regard, the molding member 180 is not formed on the lower surface of the substrate 100a, thereby exposing the lower surface of the substrate 100a.

图5是根据本实用新型的另一实施方式的半导体封装体2000的横截面图。FIG. 5 is a cross-sectional view of a semiconductor package 2000 according to another embodiment of the present invention.

在图5中，与图1和图2中相同的附图标记表示相同的部件，则因此将省略其重复说明。In FIG. 5 , the same reference numerals as those in FIGS. 1 and 2 denote the same components, and thus repeated description thereof will be omitted.

参照图5，半导体封装体2000包括衬底100a、金属层110、芯片焊盘135和多个半导体芯片160a、160b和160c。半导体封装体2000还包括第一引线130、第二引线140、多根导线170(第一导线至第四导线171、173、175和177)和模制构件180。Referring to FIG. 5, a semiconductor package 2000 includes a substrate 100a, a metal layer 110, a die pad 135, and a plurality of semiconductor chips 160a, 160b, and 160c. The semiconductor package 2000 also includes a first lead 130 , a second lead 140 , a plurality of wires 170 (first to fourth wires 171 , 173 , 175 and 177 ), and a molding member 180 .

芯片焊盘135经由焊盘粘合层120A连接到衬底100之上的金属层110。焊盘粘合层120A可以例如由焊料材料形成。或者，焊盘粘合层120A可以由导热的环氧树脂或含硅弹性体形成。当焊盘粘合层120A由焊料材料形成时，芯片焊盘135可以通过焊接过程连接到衬底100a。就这一点而言，芯片焊盘135还可以经由金属层110容易地连接到衬底100a。如果芯片焊盘135通过焊接过程附接到衬底100a上，则芯片焊盘135与衬底100a之间的附着力相对较强，因此防止其间的脱离现象。The die pad 135 is connected to the metal layer 110 over the substrate 100 via the pad adhesion layer 120A. The pad adhesive layer 120A may be formed of, for example, a solder material. Alternatively, the pad adhesive layer 120A may be formed of thermally conductive epoxy or silicon-containing elastomer. When the pad adhesive layer 120A is formed of a solder material, the chip pad 135 may be connected to the substrate 100a through a soldering process. In this regard, the die pad 135 may also be easily connected to the substrate 100 a via the metal layer 110 . If the die pad 135 is attached to the substrate 100a through a soldering process, the adhesion between the die pad 135 and the substrate 100a is relatively strong, thus preventing a detachment phenomenon therebetween.

在本实施方式中，焊盘粘合层120A可以从金属层110的边缘突出第三长度L3。就这一点而言，在参照图4C的上述回流过程期间，用于形成焊盘粘合层120A的焊料材料能够由于压缩而流动，因此形成焊盘粘合层120A。然而，在该情况下，焊盘粘合层120A仍可以与衬底100a的边缘隔开第四长度L4。In this embodiment, the pad adhesive layer 120A may protrude from the edge of the metal layer 110 by a third length L3. In this regard, during the above-described reflow process with reference to FIG. 4C , the solder material used to form the pad adhesive layer 120A can flow due to compression, thus forming the pad adhesive layer 120A. However, in this case, the pad adhesive layer 120A may still be separated from the edge of the substrate 100a by the fourth length L4.

或者，焊盘粘合层120A可以具有与衬底100a相同的宽度或者可以从衬底100a的边缘向外突出预定距离。在该情况下，如图3中所示，衬底100a可以通过模制构件180而与该衬底100a相邻的衬底100b隔开，并且金属层110从衬底100a的边缘向内形成第一长度L1，因此防止在芯片焊盘135之间出现短路。Alternatively, the pad adhesive layer 120A may have the same width as the substrate 100a or may protrude outward from the edge of the substrate 100a by a predetermined distance. In this case, as shown in FIG. 3 , the substrate 100a may be separated from the substrate 100b adjacent to the substrate 100a by a molding member 180, and the metal layer 110 forms a second layer inwardly from the edge of the substrate 100a. A length L1 , thus preventing short circuits between the die pads 135 .

根据本实用新型的半导体封装体，通过使用彼此电绝缘的衬底，可以防止在芯片焊盘之间出现短路，并且可以改进热辐射效率。According to the semiconductor package of the present invention, by using the substrates that are electrically insulated from each other, short circuits can be prevented from occurring between the chip pads, and heat radiation efficiency can be improved.

根据本实用新型的半导体封装体，通过使用金属层和焊料材料而连接衬底和芯片焊盘，可以增加衬底与芯片焊盘之间的附着力，因此改进了半导体封装体的可靠性。According to the semiconductor package of the present invention, by connecting the substrate and the die pad using the metal layer and solder material, the adhesion between the substrate and the die pad can be increased, thus improving the reliability of the semiconductor package.

虽然已经具体示出并参照其示例性实施方式说明了本实用新型，但是将理解，可在其中进行形式和细节的不同变化而不脱离所附权利要求的精神和范围。While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (6)

1.一种半导体封装体，包括：1. A semiconductor package, comprising: 衬底，所述衬底具有绝缘性能，并且包括陶瓷材料；a substrate having insulating properties and comprising a ceramic material; 金属层，所述金属层设置在所述衬底上；a metal layer disposed on the substrate; 芯片焊盘，所述芯片焊盘设置在所述金属层上；a chip pad, the chip pad being disposed on the metal layer; 粘合层，所述粘合层用于连接所述金属层和所述芯片焊盘；以及an adhesive layer for connecting the metal layer and the die pad; and 半导体芯片，所述半导体芯片设置在所述芯片焊盘的顶表面上以电连接到所述芯片焊盘。A semiconductor chip disposed on a top surface of the die pad to be electrically connected to the die pad. 2.根据权利要求1所述的半导体封装体，其中，所述粘合层由焊料材料形成。2. The semiconductor package of claim 1, wherein the adhesive layer is formed of a solder material. 3.根据权利要求1所述的半导体封装体，其中，所述金属层与所述衬底接触，并且从所述衬底的边缘向内设置预定长度。3. The semiconductor package of claim 1, wherein the metal layer is in contact with the substrate and is disposed inwardly by a predetermined length from an edge of the substrate. 4.根据权利要求1所述的半导体封装体，还包括密封构件，所述密封构件围绕所述半导体芯片和所述芯片焊盘，并且用于使所述衬底的下表面暴露。4. The semiconductor package according to claim 1, further comprising a sealing member surrounding the semiconductor chip and the die pad and for exposing a lower surface of the substrate. 5.根据权利要求4所述的半导体封装体，其中，所述半导体封装体包括多个所述衬底，并且所述衬底通过在所述衬底之间插入所述密封构件而彼此隔开设置。5. The semiconductor package according to claim 4, wherein the semiconductor package includes a plurality of the substrates, and the substrates are separated from each other by interposing the sealing member between the substrates set up. 6.根据权利要求1所述的半导体封装体，还包括连接到所述芯片焊盘的引线。6. The semiconductor package of claim 1, further comprising leads connected to the die pad.
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