CN201181705Y - Multi-chip package structure - Google Patents

Abstract

The utility model relates to a multi-chip packaging structure contains at least: the substrate is provided with a first surface, a second surface and an opening, and the opening is arranged between the first surface and the second surface; the dynamic random access memory chip is arranged on the first surface of the substrate, and one active surface of the dynamic random access memory chip faces the opening; the flash memory chip is arranged on the dynamic random access memory chip; at least one first wiring electrically connected between the flash memory chip and the substrate; at least one second wiring electrically connected to the active surface and the second surface of the DRAM chip through the opening; the first sealing colloid is formed on the first surface and covers the dynamic random access memory chip, the flash memory chip and the first wiring; the second sealing colloid is formed in the opening and covers the opening and the second connecting wire; and the solder balls are arranged on the second surface, and the height of the solder balls on the second surface is higher than that of the second sealing colloid.

Description

Multi-chip package structure

technical field

The utility model relates to a multi-chip packaging structure, in particular to a multi-chip packaging structure in which multiple chips are stacked at the same time.

Background technique

In the semiconductor production process, integrated circuit packaging (IC package) is one of the important steps in the production. It is used to protect the IC chip and provide external electrical connections to prevent damage from external forces or environmental factors during transportation and placement. In addition, integrated circuit components also need to be combined with passive components such as resistors and capacitors to form a system in order to perform the intended function, and electronic packaging (Electronic Packaging) is used to establish the protection and organizational structure of integrated circuit components. Generally speaking, electronic packaging is carried out after the integrated circuit chip is produced, including all the production processes between the bonding and fixing of the IC chip, circuit connection, structural sealing, bonding with the circuit board, system combination, and product completion. The purpose of electronic packaging is to complete the combination of IC chips and other necessary circuit components to transmit electrical energy and circuit signals, provide heat dissipation channels, load bearing and structural protection and other functions.

In today's electronic devices, a single electronic device often needs to be provided with multiple chips to perform multiple functions at the same time, so as to meet the needs of modern people for electronic devices. Taking mobile phones (mobile phones) as an example, most of the current mobile phones are built with flash (Flash) memory chips, dynamic random access memory (Dynamic Random Access Memory; DRAM) chips and controller chips. However, the above-mentioned chips are generally formed in different packaging structures respectively, thus increasing the space occupied by the packaging structures, and also increasing the difficulty of realizing thinness and miniaturization of electronic devices (mobile phones).

Contents of the invention

The technical problem to be solved by the utility model is to provide a multi-chip packaging structure, in which dynamic random access memory (DRAM) and flash memory (Flash Memory) chips are stacked in a single packaging structure, so as to save the cost of electronic devices (such as mobile phones) interior space.

In order to solve the above technical problems, the utility model provides a multi-chip packaging structure, which is characterized in that it at least includes: a substrate with a first surface, a second surface and an opening, wherein the opening is opened on the first surface Between and the second surface; a dynamic random access memory chip is arranged on the first surface of the substrate, and an active surface of the dynamic random access memory chip is facing the opening; a flash memory chip is arranged on the On the dynamic random access memory chip; at least one first wire electrically connected between the flash memory chip and the substrate; at least one second wire electrically connected to the dynamic random access memory chip through the opening The active surface and the second surface of the substrate; a first encapsulant, formed on the first surface of the substrate, and covering the dynamic random access memory chip, the flash memory chip and the first wiring; a first two sealants, formed in the opening of the substrate, and covering the opening and the second wiring; and a plurality of solder balls, disposed on the second surface of the substrate, wherein the solder balls are on the second surface The height above is higher than the height of the second encapsulant.

The above-mentioned multi-chip packaging structure is characterized in that it further includes at least: a control chip disposed on the flash memory chip and electrically connected to the substrate.

The above-mentioned multi-chip packaging structure is characterized in that it further includes: a control chip disposed on the first surface of the substrate and electrically connected to the substrate.

The above-mentioned multi-chip packaging structure is characterized in that the height of the solder ball on the second surface is at least 0.1 mm higher than the height of the second encapsulant.

The above-mentioned multi-chip packaging structure is characterized in that the multi-chip packaging structure is electrically connected to a carrier board of a mobile phone.

The above-mentioned multi-chip packaging structure is characterized in that the substrate is provided with at least one passive element.

The above-mentioned multi-chip packaging structure is characterized in that the substrate also has a ring stepped portion, which is recessed in the opening and communicated with the first surface, and the dynamic random access memory chip is locked on the ring stepped portion .

The above-mentioned multi-chip packaging structure is characterized in that the substrate also has a ring stepped part, which is recessed in the opening and located on the second surface, and the second wiring is electrically connected to the dynamic random access memory chip with the ring on the stepped part.

The utility model also provides a multi-chip packaging structure, which is characterized in that it at least includes: a substrate with a first surface, a second surface and an opening, wherein the opening is opened on the first surface and the second surface Between; a dynamic random access memory chip, arranged on the first surface of the substrate, and the active surface of the dynamic random access memory chip is facing the opening; a flash memory chip, arranged on the dynamic random access memory On the chip; a control chip is arranged on the flash memory chip; a plurality of first wires are respectively electrically connected between the flash memory chip and the substrate, and electrically connected between the control chip and the substrate; at least one The second wiring is electrically connected to the other side of the dynamic random access memory chip and the second surface of the substrate through the opening; a first encapsulant is formed on the first surface of the substrate and includes Covering the dynamic random access memory chip, the flash memory chip, the control chip and the first wirings; a second sealant, formed in the opening of the substrate, and covering the opening and the second wirings; a solder ball disposed on the second surface of the substrate, wherein the height of the solder balls on the second surface is higher than that of the second encapsulant; and at least one passive element disposed on the substrate on the first surface.

The utility model also provides a multi-chip packaging structure, which is characterized in that it at least includes: a substrate with a first surface, a second surface and an opening, wherein the opening is opened on the first surface and the second surface Between; a dynamic random access memory chip, arranged on the first surface of the substrate, and the active surface of the chip is facing the opening; a flash memory chip, arranged on the dynamic random access memory chip; a A control chip is disposed on the first surface of the substrate; at least one first wiring is electrically connected between the flash memory chip and the substrate; at least one second wiring is electrically connected to the dynamic random access through the opening The other side of the memory chip and the second surface of the substrate; at least one third wire electrically connected between the control chip and the substrate; a first encapsulant formed on the first surface of the substrate , and cover the dynamic random access memory chip, the flash memory chip, the control chip and the first wiring; a second encapsulant, formed in the opening of the substrate, and covering the opening and the second wiring a plurality of solder balls disposed on the second surface of the substrate, wherein the height of the solder balls on the second surface is higher than the height of the second encapsulant; and at least one passive element disposed on the substrate on the first surface.

Therefore, the multi-chip packaging structure of the present invention can stack and package multiple chips in a single packaging structure, thereby saving space.

The utility model will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the utility model.

Description of drawings

1A and 1B are schematic cross-sectional views of the multi-chip packaging structure of the first embodiment of the present invention;

2 is a schematic cross-sectional view of a multi-chip packaging structure of a second embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of a multi-chip packaging structure according to a third embodiment of the present invention.

Among them, reference signs:

100, 100a, 100b: multi-chip package structure

110: Substrate

111: first surface 112: second surface

113: Opening 114: Passive components

115: Pad

116a, 116b: ring stepped portion

120: Dynamic random access memory chip

130: Flash memory chip 131: Part of the surface

140: The third chip 141: The third wiring

150: first wiring 160: second wiring

170: The first colloid 180: The second colloid

190: tin ball

Detailed ways

Please refer to FIG. 1A , which is a schematic cross-sectional view of the multi-chip packaging structure of the first embodiment of the present invention. The multi-chip packaging structure 100 of this embodiment includes a substrate 110, a dynamic random access memory (DRAM) chip 120, a flash memory (Flash Memory) chip 130, a control chip 140, a first wiring 150, a second wiring 160, a first package The colloid 170, the second colloid 180 and a plurality of solder balls (Solder Ball) 190. The DRAM chip 120 , the flash memory chip 130 and the control chip 140 are stacked on the substrate 110 . The first wiring 150 is used to electrically connect between the flash memory chip 130 and the substrate 110 , and between the control chip 140 and the substrate 110 . The second wiring 160 is used to electrically connect between the DRAM chip 120 and the substrate 110, the first sealing body 170 is used to cover the DRAM chip 120, the flash memory chip 130, the control chip 140 and the first wiring 150, and the second sealing The glue 180 is used to cover the second wiring 160, and these solder balls 190 are disposed on one side surface of the substrate 110 to electrically connect the multi-chip package structure 100 to a carrier board of an electronic device (such as a mobile phone). The carrier board can be: a printed circuit board (Printed circuit board; PCB), a flexible printed circuit board (Flexible Printed Circuits; FPC) or a main board.

As shown in Figure 1A, the substrate 110 of this embodiment has a first surface 111, a second surface 112 and an opening 113, the first surface 111 and the second surface 112 are respectively located on opposite sides of the substrate 110, and the opening 113 is opened in Between the first surface 111 and the second surface 112 , the area of the opening 113 is at least smaller than the area of the DRAM chip 120 . The substrate 110 is, for example, made of a dielectric material, such as: BT (Bismaleimide Triazine) thermosetting resin material, epoxy resin, ceramic or organic glass fiber, and is provided with a passive element 114, a pad 115 and a circuit (not shown in the figure). ). The passive element 114 is, for example, a capacitor, an inductor or a resistor, and the pads 115 and lines can be formed on the first surface 111 and the second surface 112 of the substrate 110 . In this embodiment, the passive element 114 can be disposed on the first surface 111 of the substrate 110 by surface mount (SMT), and electrically connected to the pad 115 and the circuit. However, it is not limited thereto, in some embodiments, the passive device 114 can also be buried in the substrate 110 to form an integrated passive device substrate.

As shown in FIG. 1A , the DRAM chip 120 of this embodiment can be surface-bonded on the first surface 111 of the substrate 110 and located on the opening 113 of the substrate 110 . At this time, the active surface of the DRAM chip 120 is preferably facing the first surface 111 of the substrate 110 , and part of the active surface of the DRAM chip 120 is exposed in the opening 113 . The flash memory chip 130 and the control chip 140 are sequentially stacked on the back side of the DRAM chip 120 (that is, the non-active surface of the DRAM chip 120), wherein the control chip 140 does not completely cover the flash memory chip 130, and exposes the surface of the flash memory chip 130. A portion of the surface 131 . In this embodiment, the area of the control chip 140 is, for example, smaller than that of the flash memory chip 130 ; or, the control chip 140 may be only partially disposed on the flash memory chip 130 .

As shown in FIG. 1A, the first wire 150 and the second wire 160 of this embodiment are, for example, gold wires, silver wires, copper wires or aluminum wires, and the first wires 150 are electrically connected to the active surface of the flash memory chip 130 and the substrate respectively. The pads 115 on the first surface 111 of the substrate 110 are electrically connected to the control chip 140 and the pads 115 on the first surface 111 of the substrate 110 . The second wiring 160 is electrically connected to the central pad on the active surface of the DRAM chip 120 and the pad 115 on the second surface 112 of the substrate 110 through the opening 113 of the substrate 110 .

As shown in FIG. 1A , the materials of the first encapsulant 170 and the second encapsulant 180 in this embodiment are, for example, epoxy resin, PMMA, polycarbonate or silica gel. The first encapsulant 170 is formed on the first surface 111 of the substrate 110 to cover and seal the DRAM chip 120 , the flash memory chip 130 , the control chip 140 , the first wiring 150 and the passive element 114 . The second encapsulant 180 is formed in the opening 113 of the substrate 110 to cover and seal the opening 113 (that is, part of the active surface and the central pad of the DRAM chip 120 ) and the second wiring 160 . The solder balls 190 can be disposed on the second surface 112 of the substrate 110 by using, for example, a solder ball planter (not shown), wherein the material of the solder balls 190 is, for example, tin, aluminum, nickel, silver, copper, indium or the like. alloy, wherein the height of the solder balls 190 on the second surface 112 is at least 0.1 mm higher than the height of the second encapsulant 180 , so when the multi-chip package structure 100 is electrically connected to the carrier board, the second encapsulation The colloid 180 will not affect the bonding of the solder balls 190 to the carrier.

When manufacturing the multi-chip package structure 100 of this embodiment, the DRAM chip 120 can be pre-bonded to the substrate 110 , and connected to the second wiring 160 to form the second encapsulant 180 . Next, stack the flash memory (FlashMemory) chip 130 and the control chip 140 on the back of the DRAM chip 120 , connect the first wiring 150 and form the first encapsulant 170 , and then set the solder balls 190 .

In one embodiment, the flash memory chip 130 and the control chip 140 can be pre-stacked and bonded on the back of the DRAM chip 120, and then these chips are combined on the substrate 110, and then the first wire 150 and the second wire 160 are connected, And forming the first encapsulant 170 and the second encapsulant 180 , and then disposing the solder balls 190 . However, it is not limited thereto, and those skilled in the art can form the multi-chip package structure 100 of this embodiment through other different fabrication sequences.

Therefore, the above-mentioned multiple chips can be packaged in a single package structure and arranged in an electronic device (such as a mobile phone), so as to reduce the occupied space of the above-mentioned three chips in the electronic device, thus meeting the demand for thinner and lighter electronic devices.

Please refer to FIG. 1B , which is a schematic cross-sectional view of the multi-chip packaging structure of the first embodiment of the present invention. It should be noted that the arrangement of the control chip 140 of the present invention is not limited to the method described in the above-mentioned embodiments. In some embodiments, as shown in FIG. 1B , the control chip 140 can also be directly arranged on the substrate 110, Use at least one third wire 141 to electrically connect with the substrate 110, and be located on one side of the stacked flash memory chip 130 and the DRAM chip 120, wherein the stacking and arrangement of the flash memory chip 130 and the DRAM chip 120 are also similar to those shown in FIG. 1A show the same.

Please refer to FIG. 2 , which is a schematic cross-sectional view of a multi-chip packaging structure according to a second embodiment of the present invention. Compared with the first embodiment, the substrate 110 of the multi-chip package structure 100 a of the second embodiment further has a ring stepped portion 116 a recessed in the opening 113 and connected to the first surface 111 . When the DRAM chip 120 faces the opening with the active surface and is bonded on the first surface 111 of the substrate 110, the DRAM chip 120 can be locked on the ring step portion 116a to be arranged on the substrate 110, and the same as described in the first embodiment The wire bonding method is electrically connected to the substrate 110 , thereby reducing the stacking height of the plurality of chips 120 , 130 , 140 on the substrate 110 , thereby reducing the overall height of the multi-chip packaging structure 100 .

Please refer to FIG. 3 , which is a schematic cross-sectional view of a multi-chip packaging structure according to a third embodiment of the present invention. Compared with the first embodiment, the ring step portion 116b of the substrate 110 of the multi-chip package structure 100b of the third embodiment is recessed in the opening 113 and located on the second surface 112 . At this time, the ring stepped portion 116b can be provided with a pad 115b, the second wire 160 can be electrically connected to the central pad of the DRAM chip 120 and the pad 115b on the ring stepped portion 116b, and the second sealing body 180 can be formed on the opening. 113 and the ring step portion 116b, thus the height of the second sealant 180 formed on the second surface 112 may be reduced; or, the second sealant 180 may not protrude from the second surface 112 .

It can be known from the above embodiments of the present invention that the multi-chip packaging structure of the present invention can package multiple chips at the same time, thereby saving the space occupied by the packaging structure.

Certainly, the utility model also can have other various embodiments, under the situation of not departing from the spirit and essence of the utility model, those skilled in the art can make various corresponding changes and distortions according to the utility model, but these Corresponding changes and deformations should all belong to the protection scope of the claims of the present invention.

Claims (10)

1. A multi-chip packaging structure, characterized in that it at least includes: A substrate having a first surface, a second surface and an opening, wherein the opening is set between the first surface and the second surface; a dynamic random access memory chip disposed on the first surface of the substrate, and an active surface of the dynamic random access memory chip faces the opening; a flash memory chip arranged on the dynamic random access memory chip; at least one first wire electrically connected between the flash memory chip and the substrate; at least one second wire electrically connected to the active surface of the dynamic random access memory chip and the second surface of the substrate through the opening; a first encapsulant, formed on the first surface of the substrate, and covering the dynamic random access memory chip, the flash memory chip and the first wiring; a second encapsulant, formed in the opening of the substrate, and covering the opening and the second wiring; and A plurality of solder balls are disposed on the second surface of the substrate, wherein the height of the solder balls on the second surface is higher than that of the second encapsulant. 2. The multi-chip packaging structure according to claim 1, further comprising at least: A control chip is arranged on the flash memory chip and electrically connected with the substrate. 3. The multi-chip packaging structure according to claim 1, further comprising at least: A control chip is arranged on the first surface of the substrate and electrically connected with the substrate. 4. The multi-chip package structure according to claim 1, wherein the height of the solder ball on the second surface is at least 0.1 mm higher than the height of the second encapsulant. 5. The multi-chip package structure according to claim 1, wherein the multi-chip package structure is electrically connected to a carrier board of a mobile phone. 6. The multi-chip package structure according to claim 1, wherein the substrate is provided with at least one passive element. 7. The multi-chip package structure according to claim 1, wherein the substrate further has a ring stepped part, which is recessed in the opening and connected to the first surface, and the dynamic random access memory chip It is stuck on the ring step. 8. The multi-chip package structure according to claim 1, wherein the substrate further has a ring-shaped stepped portion, which is recessed in the opening and located on the second surface, and the second wiring is electrically connected to On the dynamic random access memory chip and the ring step part. 9. A multi-chip packaging structure, characterized in that it at least includes: A substrate having a first surface, a second surface and an opening, wherein the opening is set between the first surface and the second surface; a dynamic random access memory chip disposed on the first surface of the substrate, and the active surface of the dynamic random access memory chip faces the opening; a flash memory chip arranged on the dynamic random access memory chip; a control chip set on the flash memory chip; A plurality of first wires are respectively electrically connected between the flash memory chip and the substrate, and electrically connected between the control chip and the substrate; at least one second wire electrically connected to the other side of the dynamic random access memory chip and the second surface of the substrate through the opening; a first encapsulant, formed on the first surface of the substrate, and covering the dynamic random access memory chip, the flash memory chip, the control chip and the first wires; a second encapsulant, formed in the opening of the substrate, and covering the opening and the second wiring; a plurality of solder balls disposed on the second surface of the substrate, wherein the height of the solder balls on the second surface is higher than that of the second encapsulant; and At least one passive element is disposed on the first surface of the substrate. 10. A multi-chip packaging structure, characterized in that it at least includes: A substrate having a first surface, a second surface and an opening, wherein the opening is set between the first surface and the second surface; a dynamic random access memory chip disposed on the first surface of the substrate, and the active surface of the chip faces the opening; a flash memory chip arranged on the dynamic random access memory chip; a control chip, arranged on the first surface of the substrate; at least one first wire electrically connected between the flash memory chip and the substrate; at least one second wire electrically connected to the other side of the dynamic random access memory chip and the second surface of the substrate through the opening; at least one third wire electrically connected between the control chip and the substrate; a first encapsulant, formed on the first surface of the substrate, and covering the dynamic random access memory chip, the flash memory chip, the control chip and the first wiring; a second encapsulant, formed in the opening of the substrate, and covering the opening and the second wiring; a plurality of solder balls disposed on the second surface of the substrate, wherein the height of the solder balls on the second surface is higher than that of the second encapsulant; and At least one passive element is disposed on the first surface of the substrate.

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