CN200983362Y - A BGA chip encapsulation device - Google Patents

Abstract

The utility model discloses a BGA chip packaging device, which comprises a chip (102), a mold cap (202), a first substrate (103), a lower surface welding ball (104) and a first wire bridge (105). The BGA chip packaging device also includes a second substrate (201), solder balls (203) on the upper surface and second wire bridges (204). The mold cap (202) covers the outer side of the chip (102), and a channel for the second wire bridge (204) is arranged on the upper side thereof. The first substrate (103) and the second substrate (201) are symmetrically fixed up and down on the lower bottom surface and the upper surface of the chip (102), on which the upper surface solder balls (203) and the Solder balls (104) on the lower surface. The first wire bridge (105) and the second wire bridge (204) respectively connect the chip (102) with the lower surface solder ball (104) and the upper surface solder ball (203). The utility model greatly simplifies and facilitates debugging and testing of the FPGA.

Description

A BGA chip packaging device

technical field

The utility model relates to the field of microelectronics and integrated circuit manufacturing. In particular, it relates to a packaging device for chips of the BGA package (Ball Grid Array Package) type.

Background technique

In today's high-speed digital systems, due to performance requirements, there are more and more applications of ASIC (Application Specific Integrated Circuit). In high-end and high-speed systems, ASIC has its own unique advantages. It can work at a relatively high frequency , providing performance that cannot be achieved by general-purpose chips. However, ASIC also has its own shortcomings. Because it is not programmable, it is difficult to develop and maintain, especially in terms of maintenance. Even if a small function is to be added or changed, it needs to be redesigned and taped, resulting in its development cost. The geometric progression increases. Therefore, more and more FPGAs are now being used to replace ASICs. FPGA has the characteristics of reprogrammability, so it has a greater advantage than ASIC in the maintenance of new functions, and there is not much difference in performance, so FPGA is more and more widely used.

Due to the large number of pins, today's FPGAs usually use BGA or similar packages.

Fig. 1 is the chip of prior art BGA package, as shown in Fig. 1, the physical chip 106 of prior art package is made of mold cap 101, chip 102, substrate 103, solder ball 104 and wire bridge 105 above.

Chip 102: the chip 102 is the core of the entire physical package, and is the carrier of the functions of the physical chip to implement logic, timing and circuit functions.

Mold cap 101: covers the outside of the chip 102 to prevent the chip from being damaged by external force. The mold cap has high physical strength and can resist strong external force to avoid deformation of the internal chip.

Substrate 103: Bonded to the lower part of the chip, this layer of substrate 103 is connected to the chip 102 through an adhesive, and the substrate 103 is used to realize the connection between the internal chip and the bottom solder balls. Because it needs to be in direct contact with the outside world, the substrate has a strong physical Strength and impact resistance, due to the direct contact with the solder balls, the substrate should have strong heat resistance.

Solder ball 104: fixed under the substrate 103, it is the pin of the physical package, which is the only entrance for the user to access the internal chip. The solder ball 104 is connected to the internal chip through a wire bridge, and is used to guide the input and output signals of the internal chip to external, allowing users to interface their own circuitry with that of the internal chip.

Wire bridge 105: The wire bridge 105 passes through the substrate to realize the connection between the internal chip and the external solder ball. The wire bridge is generally made of copper.

It can be seen from the above that since the chip does not directly contact the outside, the input and output signals of the chip must be connected to the solder balls through wire bridges, and the user must access the pins of the internal chip through the solder balls. To the user, the pins of the internal chip are not visible, but the solder balls are.

However, when using BGA-packaged chips, the soldered solder balls are invisible to users. Therefore, the current FPGA debugging methods are basically: first design the digital circuit in the chip combined with software waveform simulation, and then carry out board-level debugging. When a problem is encountered during debugging and testing, it is necessary to analyze the problem. At this time, it is very likely that the signal change inside the FPGA needs to be monitored. However, observation of internal signals during debugging and testing is the biggest difficulty encountered in system design using FPGAs. This internal signal can be captured by specific software through the JTAG (Joint Test Action Group) interface, but operations such as synthesis and wiring of the device need to be re-synthesized, which consumes a lot of time and requires additional FPGA internal resources to achieve this. It is inconvenient in the case of a large resource shortage, which is very unfavorable to the modular design of FPGA. Another way is to lead the internal signal to the temporary pin of the FPGA, because the multi-pin FPGA basically adopts the BGA type (EBGA (enhanced ball grid array package), FBGA (fine pitch ball grid array package), etc.) Therefore, the solder balls of the packaged chips cannot be touched, which requires test points to be drawn out for these temporary pins, which is another limitation on PCB (printed circuit board) board-level wiring.

Utility model content

The technical problem to be solved by the utility model is to provide a BGA chip packaging device, which overcomes the defect that it is difficult to realize flexible monitoring of pin signals and internal signals in the FPGA design in the prior art, especially to overcome the observation of the FGPA in the prior art. Pins need to add test points to the PCB board-level wiring or re-layout and route the FPGA.

In order to solve the above technical problems, the utility model provides a BGA chip packaging device, which includes a chip, a mold cap, a first substrate, a lower surface solder ball and a first wire bridge, the mold cap covers the outside of the chip, The first substrate is bonded to the lower bottom surface of the chip, the bottom of which fixes the solder balls on the lower surface, and the first wire bridge connects the chip and the solder balls on the lower surface, wherein the BGA chip The packaging device also includes a second substrate, solder balls on the upper surface, and second wire bridges; the second substrate is fixed on the upper surface of the chip, and is vertically symmetrical with the first substrate, and the solder balls on the upper surface are fixed on the upper surface of the chip. On the second substrate, the upper side of the mold cap is provided with a channel for the bridging of the second wire, and the second wire bridge passes through the channel and crosses the mold cap and the second substrate, connecting the upper surface solder balls to the chip.

Further, in a preferred embodiment of the present utility model, the second substrate is fixed on the upper surface of the chip by bonding.

Further, in a preferred embodiment of the present invention, the mold cap is fixed on the outside of the chip by bonding.

Further, in a preferred embodiment of the present invention, the mold cap has a larger contact surface with the second substrate.

Further, the solder balls on the upper surface are only fixed on the second substrate.

Further, the bonding method is realized by using peroxidant.

Further, in a preferred embodiment of the present invention, the solder balls on the upper surface are completely symmetrical to the solder balls on the lower surface.

Further, the solder balls on the upper surface are symmetrical to a part of the solder balls on the lower surface.

When the BGA chip packaging device of the present invention is welded on the surface of the PCB board through the solder balls on the lower surface, although the solder balls on the lower surface are invisible to the user, the solder balls on the upper surface are still visible to the user. Therefore, the user can measure the input and output signals of the internal chip through the solder balls on the upper surface.

The utility model also provides a kind of FPGA encapsulation mode that is easy to debug and test, and it comprises the following steps:

A: Construct the physical structure of the chip in a traditional way, set a mold cap on the outside of the chip, and set a first substrate on the bottom of the chip, fix the solder balls on the lower surface under the first substrate, and use the first wire to bridge the The solder balls on the lower surface are connected to the chip;

B: There is a passage for the second wire bridging on the upper side of the mold cap;

B: the upper surface of the chip is also covered with the second substrate;

C: Solder balls on the upper surface are also fixed on the second upper substrate,

D: Connect the solder balls on the upper surface to the chip with a second wire bridge.

Further, the step C may include:

C1: If wiring conditions permit, the signal of the solder ball on the upper surface on the upper side may be exactly the same as that of the solder ball on the lower surface on the other side (lower side);

C2: Due to wiring reasons, the upper surface solder balls on the upper side may only lead out part of the signals, but not all of them are the same as the signals of the lower surface solder balls on the other side (lower side).

The key points of the utility model are: 1. A layer of substrate is added in the physical packaging of the chip; 2. Solder balls are added to the upper and lower sides of the chip at the same time to enhance the visibility of the signal.

Therefore, it can be seen from the above that due to the addition of a layer of substrate and solder balls (ie, solder balls on the upper surface) on the upper surface of the traditional BGA-packaged chip, when the chip is BGA-packaged, the pins of the same internal chip At the same time, lead to both sides of the chip for physical packaging. In this way, there are solder balls corresponding to the same signal on the upper and lower sides of the chip to realize the signal visibility of the chip after PCB soldering. When debugging and testing, if you need to To measure the pins of the internal chip, only the exposed solder balls on the chip need to be measured.

Chips using this packaging method, when developers are debugging and testers are testing, if problems are found, when it is necessary to observe the pin signals of the chip, they only need to directly lead out the test points on the chip instead of It is necessary to modify the PCB single board. Even if the corresponding signal has not been led to the pins on the chip at this time, all that needs to be done is to re-lock the pins of the chip, without re-synthesis, layout and wiring of the chip. .

Therefore adopt the chip package device of the present utility model, when debugging and testing, can not change the wiring of PCB board level, do not need to add test point in PCB board level wiring, and do not need to carry out layout and wiring again to FPGA, greatly simplify And it is easy to debug and test the FPGA.

In addition, since the solder balls on the upper surface and the solder balls on the lower surface can be completely symmetrical, and can only contain a part of the solder balls on the lower surface, the utility model can be adapted to different wiring situations.

The utility model realizes an FPGA packaging device which is easy to debug and test, and makes signal pins completely visible to users by changing the traditional packaging method. Reduced the difficulty of user development. The utility model can be changed, and is widely used in BGA type and various ASIC chip packaging similar to BGA type packaging, not just FPGA chips.

Description of drawings

Fig. 1 is the chip of BGA package of prior art;

Fig. 2 is the chip of BGA package of the present utility model;

Fig. 3 is the cross-sectional view of the chip of BGA package of the present utility model in practical application;

Fig. 4 is the plan view of the chip of BGA package of the present utility model in practical application;

Detailed ways

Below in conjunction with accompanying drawing, the specific embodiment of the present utility model is described in detail.

Fig. 2 is the chip of BGA package of the present utility model, as shown in Figure 2, the chip of BGA package of the present utility model is physical chip 205, and it comprises following parts:

Chip 102: the core of the packaged physical device, that is, the crystal part in the physical device, used to realize the function of the device, which is the same as the structure in the prior art;

Substrate 201: fixed on the upper surface of the chip 102, vertically symmetrical with the substrate 103 below the chip 102, preferably, it is connected with the chip 102 by bonding, and the bonding method can be realized by using traditional peroxide. The substrate 201 is the carrier of the BGA package, and is used to connect the internal chip 102 and the solder balls 203 on the upper surface (described below), so as to prevent the chip from being directly exposed to the outside world.

Substrate 103: bonded to the bottom surface of the chip 102, and connected to the chip 102 through an adhesive, which is symmetrical with the substrate 201 up and down, and is used to realize the connection between the internal chip 102 and the solder balls on the lower surface, which is the same as the structure in the prior art .

Compared with the chip of the BGA package of the conventional technology, the chip of the BGA package of the present invention forms substrates 201 and 103 which are symmetrical up and down, so that the inner chip can be provided with wire bridges simultaneously on the upper surface of the substrate 201 and the lower surface of the substrate 103. The carrier, so that the upper and lower surfaces can fix the solder balls, this change is the focus of the utility model.

Mold cap 202: covered on the outside of the chip 102, preferably, connected to the chip 102 by a bonding method, wherein the bonding method can be realized by using a traditional peroxide, and preferably, the mold cap 202 is connected to the substrate 201 and 103 has a larger contact surface; it is used to strengthen the chip's protection against external forces and strengthen the chip's ability to resist blows. Compared with the traditional technology, the utility model reserves a connection channel between the substrate 201 and the internal chip 102 at the mold cap 202 of the upper layer, which is an improvement of the utility model.

Solder balls 203 on the upper surface: fixed on the upper surface of the substrate 201, preferably, bonded to the upper surface of the substrate 201 by a peroxide, the same as the fixing method of the solder balls 104 on the lower surface, it is only connected to the substrate 203 for For the user, the external soldering contacts can only be connected to the chip through soldering balls, and its function is the same as that of the soldering balls 104 on the lower surface.

Solder balls 104 on the lower surface: fixed on the underside of the substrate 103, which is the same structure as in the prior art.

It should be noted that the solder balls 203 on the upper surface can correspond to the solder balls 104 on the lower surface in exactly the same position and number, and can also be arranged on the upper surface of the substrate 201 as required, and only correspond to a part of the solder balls 104 on the lower surface, that is, realize A part of chip signals are led to the upper surface of the substrate 201 . This allows more flexible allocation and utilization of wiring and internal resources, and is also applicable to some specific pins, such as power and ground, which do not need to be visible to the user.

Different from the traditional BGA packaging, the utility model has solder balls on the upper and lower planes of the packaged chip, so that when the user connects the packaged chip to the PCB circuit board through the solder balls on the lower surface, the upper The solder balls on the surface are visible. When the user needs to measure and monitor the pin signals of the internal chip, the measurement can be performed directly without a test point on the PCB circuit board. It is one of the improvements of the utility model.

Wire bridge 204: The wire bridge 204 passes through the substrate 201, straddles the mold cap 202 and the substrate 201, and is used to connect the upper surface solder ball 203 and the internal chip 102, and has the same function as the wire bridge 105.

Wire bridge 105: The wire bridge 105 passes through the substrate 103 to realize the connection between the internal chip 102 and the solder ball 104 on the lower surface, which is the same as the structure in the prior art.

Physical chip 205: the packaged improved physical chip for practical application is formed by the upper substrate 201, mold cap 202, upper surface solder ball 203, wire bridge 204, chip 102, substrate 103, solder ball 104 and wire bridge 105 205.

Fig. 3 is a cross-sectional view of the BGA-packaged chip of the present invention in practical application. The physical chip 205 is a chip using the improved packaging device of the present invention. The physical chip 205 is directly welded on the surface of the PCB 301 through the solder balls 104 on the lower surface. Like the chip in the traditional BGA package, the solder balls 104 on the lower surface are used to connect the input and output signals of the chip with external circuits. The PCB board 301 is a circuit board designed for the user's own circuit system application. The test wire 302 is connected to the solder ball 203 on the upper surface of the physical chip 205 , and the user can test the signal of the chip through the test wire 302 .

In this practical application, the solder balls 203 on the upper surface and the solder balls 104 on the lower surface of the physical chip 205 can be completely symmetrical (that is, the positions and numbers can be completely aligned), or they can only correspond to a part of the solder balls 104 on the lower surface. FIG. 3 shows the situation that the solder balls 203 on the upper surface and the solder balls 104 on the lower surface of the physical chip 205 are completely symmetrical.

As shown in Figure 3, when the physical chip 205 is welded on the surface of the PCB board 301, the solder balls 104 on the lower surface have been covered by the chip itself, which is invisible to the user, while the solder balls 203 on the upper surface are not visible to the user. The user is visible, so through the solder ball 203 on the upper surface, the user can observe the input and output signals of the internal chip, which is the same as the input and output signal obtained by the solder ball 104 on the lower surface. Further, for example, the test wire 302 can be used Test the signal of the chip.

FIG. 4 is a top view of the BGA-packaged chip of the present invention in practical application. It is a top view of the physical chip 205 being welded on the surface of the PCB 301 through the solder balls 104 on the lower surface. As shown in FIG. 4, after the physical chip 205 is welded on the surface of the PCB board 301, the upper surface solder ball 203 of the physical chip 205 is still visible, while the lower surface solder ball 104 is invisible, so when it is necessary to measure the tube of the chip When the pin signal is used, the user can measure the internal signal through the solder ball 203 on the upper surface, which is very convenient for the user to measure.

In summary, the BGA chip packaging device of the present invention has the following advantages compared with traditional BGA packaged chips:

1. Since a layer of substrate and solder balls (that is, solder balls on the upper surface) are added above the chip in the traditional BGA package, and the added substrate is symmetrical up and down with the substrate fixed under the chip, and the solder balls on the upper surface and the lower solder balls are symmetrical to each other. The surface solder balls correspond to each other. Therefore, for the same internal chip pin, the solder balls on the upper and lower sides of the packaged chip can be led to the solder balls on the upper and lower sides of the packaged chip at the same time, and pins with the same signal are formed on the upper and lower sides of the packaged chip to realize the packaged chip. The signal visibility of the chip after PCB soldering, so if you need to measure the pins during debugging and testing, you only need to measure the exposed solder balls on the chip, so the PCB board-level wiring will not be changed. There is no need to add test points to the PCB board-level wiring, and there is no need to re-layout and route the FPGA, which greatly simplifies and facilitates the debugging and testing of the FPGA;

2. Since the positions and numbers of the solder balls on the upper surface and the solder balls on the lower surface can be exactly the same up and down, and can only correspond to a part of the solder balls on the lower surface, it is more flexible to allocate and utilize wiring and internal resources, and adapt to different applications. wiring occasions;

3. The packaging device of the present invention can be modified, and can be applied to various packaging devices for different chip packaging;

It can be known from the above that the BGA chip packaging device of the present invention is easy to debug and test, and it realizes the great simplification of debugging and testing of FPGA with a simple change in the packaging structure. This is a simple and flexible solution for easy debugging and testing of FPGA or other ASIC chips packaged in BGA (EBGA, FBGA, etc.).

The structure of the present utility model can also provide similar effects after making the following changes, and the changes are:

The solder balls on the upper surface can correspond to the solder balls on the lower surface completely up and down, or only correspond to a part of the solder balls on the lower surface, that is, only a part of the chip signal is led to the upper surface.

The packaging structure of the utility model can be applied to chip packaging devices of other packaging methods after modification. For example, the utility model can not only be applied in BGA-packaged chips, but can also be applied in devices with similar packages such as EBGA, FBGA, etc., or even in devices with dissimilar other packaging methods, such as: LCC, LDCC, In devices with various packaging methods such as LQFP and PQFP.

It should be noted that the utility model is not limited to the above-mentioned applications. The utility model can be applied to various occasions that require debugging and testing of chip packaging devices. Visibility, so if there are other forms to realize the intention of the utility model all fall within the protection scope of the utility model. In addition, the above-mentioned embodiments are only exemplary, and cannot be construed as limiting the present utility model. Various changes and modifications can be made to the utility model without departing from the spirit and scope of the utility model. The invention is defined by the appended claims.

Claims (8)

1, a kind of BGA chip packaging device, it comprises chip (102), mold cap (202), first substrate (103), lower surface welding ball (104) and first wire bridge (105), described mold cap ( 202) covering the outside of the chip (102), the first substrate (103) is fixed on the bottom surface of the chip (102), and the bottom surface solder balls (104) are fixed on the bottom surface, the first substrate (103) The wire bridge (105) connects the chip (102) and the lower surface solder ball (104), and it is characterized in that the BGA chip packaging device also includes a second substrate (201), an upper surface solder ball (203) and The second wire bridge (204); the second substrate (201) is fixed on the upper surface of the chip (102), symmetrical with the first substrate (103) up and down, and the solder balls (203) on the upper surface are fixed On the second substrate (201), the upper side of the mold cap (202) is provided with a channel for the second wire bridge (204), and the second wire bridge (204) passes through the channel And straddling the mold cap (202) and the second substrate (201), connecting the solder balls (203) on the upper surface and the chip (102). 2. The BGA chip packaging device according to claim 1, characterized in that, the second substrate (201) is fixed on the upper surface of the chip (102) by bonding. 3. The BGA chip packaging device according to claim 1, characterized in that, the mold cap (202) is fixed on the outer side of the chip (102) by bonding. 4. The BGA chip packaging device according to claim 1, characterized in that, the mold cap (202) has a larger contact surface with the second substrate (201). 5. The BGA chip packaging device according to claim 1, characterized in that, the solder balls (203) on the upper surface are only fixed on the second substrate (201). 6. The BGA chip packaging device according to any one of claims 2 and 3, characterized in that, the bonding method is realized by using peroxide. 7. The BGA chip packaging device according to claim 1, characterized in that, the solder balls (203) on the upper surface are completely symmetrical to the solder balls (104) on the lower surface. 8. The BGA chip packaging device according to claim 1, characterized in that, the solder balls (203) on the upper surface are symmetrical to a part of the solder balls (104) on the lower surface.

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