CN200979884Y - A compound structure of a field effect transistor - Google Patents
A compound structure of a field effect transistor Download PDFInfo
- Publication number
- CN200979884Y CN200979884Y CN 200620159594 CN200620159594U CN200979884Y CN 200979884 Y CN200979884 Y CN 200979884Y CN 200620159594 CN200620159594 CN 200620159594 CN 200620159594 U CN200620159594 U CN 200620159594U CN 200979884 Y CN200979884 Y CN 200979884Y
- Authority
- CN
- China
- Prior art keywords
- nldmos
- type
- layer
- diffusion layer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 41
- 150000001875 compounds Chemical group 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 170
- 239000002131 composite material Substances 0.000 claims abstract description 32
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 95
- 238000002955 isolation Methods 0.000 claims description 77
- 238000000407 epitaxy Methods 0.000 claims description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 150000004706 metal oxides Chemical class 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 254
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000000605 extraction Methods 0.000 description 4
- 210000000746 body region Anatomy 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The utility model discloses a composite field-effect transistor structure, comprising an N type lateral double-diffusion metallic oxide field-effect transistor (NLDMOS) and an N type junction field-effect transistor (NJFET), wherein the N+ type diffusion layer (112) inside the N type extension (102) forms a common drain area of the NLDMOS and the NJFET, and the N+ type diffusion layer (112) of the N type extension (102) forms a connecting electrode as the common drain electrode of the NLDMOS and the NJFET. The chip area would be decreased by using the structure of the utility model effectively, the initial grid voltage of the NLDMOS can be provided, and the NLDMOS can be effectively switched off, to decrease the power consumption significantly.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly to a field effect transistor.
Background
In high voltage integrated circuits, high voltage lateral double diffused metal oxide semiconductor (LDMOS) or high voltage Junction Field Effect Transistor (JFET) is commonly used as a high voltage tolerant device. In order to effectively reduce the on-resistance while improving the withstand voltage of the LDMOS or JFET device, high withstand voltage and low on-resistance of the circuit can be achieved by controlling the electric field. But only one LDMOS or one JFET is in the same circuit. When the circuit needs the high-voltage LDMOS and the high-voltage JFET at the same time, two separate components, namely the high-voltage LDMOS and the high-voltage JFET, are needed to be adopted, and the high-voltage LDMOS and the high-voltage JFET occupy larger chip area.
On the other hand, in a high-voltage integrated circuit, it is sometimes necessary to effectively control the power supply of the high-voltage terminal to the chip. For a circuit using only N-type LDMOS, if a high voltage supply is needed when the circuit is started, the enhancement-type NLDMOS is not turned on because its gate initial voltage is zero, and if the depletion-type NLDMOS is directly turned on, the problem of initial power-up is solved, but it cannot be turned off by the gate (except for the gate plus a negative voltage). Further, the circuit thus constructed is not only complicated in structure but also extremely high in power consumption.
Disclosure of Invention
To the defect that exists in the use of LDMOS and JFET among the above-mentioned high voltage integrated circuit, the utility model provides a compound field effect tube structure.
According to an aspect of the present invention, a composite fet structure is provided. It includes: lateral double diffused N-type metal oxide semiconductor field effect transistors (NLDMOS) and N-type junction field effect transistors (njets). The N-type laterally diffused metal oxide semiconductor (NLDMOS) and the N-type field effect transistor (NJFET) of the field effect transistor structure share one drain region, a P-well substrate of the N DMOS and a P-type substrate of the whole chip are used as a grid region of the N JFET, P-type upper isolation layers and P-type lower isolation layers (P-type lower isolation layers 104 in the drawing) are used for forming opposite-connection isolation around the whole N DMOS and the N JFET, and the N DMOS and the N JFET are isolated from other elements on the chip where the structure is. An N + diffusion layer (an N + diffusion layer 107 in the drawing) is arranged between the P-well substrate of the N-type laterally diffused metal oxide semiconductor (NLDMOS) and the P-well substrate of the NLDMOS to serve as a source of the NJFET. The N-type epitaxy is not only a drain drift region of the NLDMOS, but also a body region of the NJFET.
Wherein, NLDMOS include:
a P-type substrate as a substrate of the entire structure;
n-type epitaxy;
a drain region formed by an N + diffusion layer (N + diffusion layer 112 in the drawing) within the N-type epitaxy, wherein the N + diffusion layer (N + diffusion layer 112 in the drawing) of the N-type epitaxy forms a connection electrode as a drain;
a P well 110 positioned in the N-type epitaxy is used as a substrate of the NLDMOS, and a P + diffusion layer (a P + diffusion layer 108 in the drawing) on the substrate of the NLDMOS forms a connecting electrode as a substrate connecting end;
an N + diffusion layer (an N + diffusion layer 109 in the figure) in the substrate of the NLDMOS is used as a source region of the NLDMOS, and a connecting electrode is formed in the source region through the N + diffusion layer (the N + diffusion layer 109 in the figure) to serve as a source;
the gate polycrystalline silicon crossing the P well between the source region and the drain region of the NLDMOS is used as the gate of the NLDMOS, an active region and a field region are arranged below the gate of the NLDMOS, the thin oxide region of the active region is used as a gate oxide layer, the field region is positioned above the drain region of the NLDMOS, the active region is positioned above the P well and crosses the P well to intersect the source region and the drain region, and the length of the NLDMOS gate is the length of the intersection of the active region and the P well substrate.
Wherein, the NJFET includes:
the drain region of the NLDMOS is used as the drain region of the NJFET, the P-type substrate of the whole chip and a P-well in an N-type epitaxy are used as the gate region of the NJFET, wherein a P + diffusion layer (a P + diffusion layer 108 in the drawing) in the P-well and a P + diffusion layer (a P + diffusion layer 106 in the drawing) in an upper P-type isolation layer form a connecting electrode as a gate, a P-type upper isolation layer and a P-type lower isolation layer (a P-type lower isolation layer 104 in the drawing) form a gate-to-gate isolation, the P-type substrate and the gate are connected, a connecting electrode is formed relative to the N + diffusion layer (an N + diffusion layer 107 in the drawing) on the N-type epitaxy on the NLDMOS gate region and close to the source side, and is used as the source of the NJFET, and the N + diffusion layer (an N + diffusion layer 107 in the drawing) of the NJFET is positioned between the P-.
Further, a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing) may be disposed between the P-type substrate and the N-type epitaxy near the gate of the NLDMOS of the composite fet structure and near the drain electrode, or a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing) may not be disposed;
furthermore, an N well layer can be arranged at the drain ends of the NLDMOS and the NJFET of the composite field effect transistor structure, or an N well layer can be omitted;
further, in the composite field effect transistor structure, a P-type diffusion is added on the N-type epitaxy used as the drain drift region of the NLDMOS, namely between the drain terminal of the N + diffusion layer (N + diffusion layer 112 in the drawing) of the NLDMOS drain region and the P-well substrate of the NLDMOS, and the P-type diffusion can be one section or K section (K > 1). After the P-type diffusion is added, the concentration of N-type epitaxy can be improved, the on-resistance of NLDMOS is reduced, and the optimal design meeting the requirements of high withstand voltage and on-resistance is realized.
Further, in the composite field effect transistor structure, an N + diffusion layer (an N + diffusion layer 109 in the drawing) serving as the source region of the NLDMOS may be included in one N-diffusion layer to improve the withstand voltage of the P-well substrate and the source region of the NLDMOS, or there may be no N-diffusion layer around the N + diffusion layer (the N + diffusion layer 109 in the drawing) of the source region of the NLDMOS, so as to be suitable for use when the voltage of the P-well substrate and the source region of the NLDMOS is low or the P-well substrate and the source region of the NLDMOS are turned on to a potential;
further, the composite field effect transistor is of a completely centrosymmetric circular structure. The following description will be made with a field effect transistor structure having an N-well layer, a P-type lower spacer (P-type lower spacer 103 in the drawing), and an N-diffusion layer, at the center of symmetry, the NLDMOS and the drain of the NJFET, and the drain region of which is composed of an N + diffusion layer (N + diffusion layer 112 in the drawing), an N-well layer, and an N-type epitaxy layer. The N well layer is arranged in the N-type epitaxy and is a certain distance away from the P well, the magnitude of the distance determines the withstand voltage of the NLDMOS and the NJFET, and an N + diffusion layer (an N + diffusion layer 112 in the drawing) is arranged in the N well layer and is positioned at the symmetrical center. The P-type lower isolation layer (P-type lower isolation layer 103 in the figure) for the NLDMOS is located between the P-type substrate of the NLDMOS and the N + diffusion layer (N + diffusion layer 112 in the figure) of the drain of the NLDMOS, and also located between the P-type substrate and the N-type epitaxy. In the field effect transistor structure, the outermost layer of the whole NLDMOS and the NJFET is a P-type upper isolation layer and a P-type lower isolation layer (a P-type lower isolation layer 104 in the drawing) which form a pair-pass isolation, the pair-pass isolation passes through a P + diffusion layer (a P + diffusion layer 106 in the drawing), a contact hole is connected with an aluminum bar and is connected to a low potential, and the contact hole is an isolation contact hole. Between the isolation contact and the P-well substrate of the NLDMOS is an N + diffusion layer (N + diffusion layer 107 in the figure) that serves as the source contact of the NJFET. The P-well is formed between the N + diffusion layer (N + diffusion layer 107 in the drawing) of the source of the NJFET and the N + diffusion layer (N + diffusion layer 112 in the drawing) of the drain of the NLDMOS, and serves as a substrate of the NLDMOS and also serves as a gate of the NJFET. The P + diffusion layer (P + diffusion layer 108 in the figure) in the NLDMOS substrate serves as a substrate contact hole of the NLDMOS, the N + diffusion layer (N + diffusion layer 109 in the figure) in the NLDMOS substrate serves as a source of the NLDMOS, and the N + diffusion layer (N + diffusion layer 109 in the figure) of the source of the NLDMOS also serves as a contact hole. The gate polysilicon is arranged above the edge of the source electrode of the NLDMOS and the side close to the drain region and crosses between the substrate of the NLDMOS and the drain region of the NLDMOS, two sections of oxide layers are arranged below the gate polysilicon, one section is a thin oxide layer, the other section is a thick oxide layer, the thin oxide layer crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlapping size with the source electrode of the NLDMOS, the overlapping size is determined by the lateral diffusion of an N + diffusion layer (an N + diffusion layer 109 in the drawing), and the thick oxide layer is arranged above an N-type epitaxy used as the drain region of the NLDMOS. The gate polysilicon is connected to the aluminum bar through the contact hole, and the gate polysilicon is the gate of the NLDMOS. The N + diffusion layer (the N + diffusion layer 109 in the drawing) of the NLDMOS source region can be included in one N-diffusion layer to improve the withstand voltage of the NLDMOS substrate and the source region.
According to yet another aspect of the present invention, a composite fet structure is provided. It includes: NLDMOS and njets. The NLDMOS and the NJFET of the field effect transistor structure share a drain region, a P-well substrate of the NLDMOS and a P-type substrate of the whole chip are used as a grid region of the NJFET, P-type upper isolation layers and P-type lower isolation layers (P-type lower isolation layers 104 in the attached drawing) are used for forming opposite-connection isolation around the whole NLDMOS and the NJFET, and the NLDMOS and the NJFET are isolated from other elements on the chip where the structure is located. An N + diffusion layer (N + diffusion layer 107 in the figure) is arranged between the P-well substrate of the P-type N-type laterally-diffused metal oxide semiconductor (NLDMOS) and the P-well substrate of the NLDMOS to serve as a source of the NJ FET. The N-type epitaxy is not only a drain drift region of the NLDMOS, but also a body region of the NJFET.
Wherein, NLDMOS include:
a P-type substrate as a substrate of the entire structure;
n-type epitaxy;
a drain region formed by an N + diffusion layer (N + diffusion layer 112 in the drawing) within the N-type epitaxy, wherein the N + diffusion layer (N + diffusion layer 112 in the drawing) of the N-type epitaxy forms a connection electrode as a drain;
the P trap in the N-type epitaxy is used as the substrate of the NLDMOS, and a P + diffusion layer (a P + diffusion layer 108 in the drawing) on the substrate of the NLDMOS forms a connecting electrode as a substrate connecting end;
an N + diffusion layer (an N + diffusion layer 109 in the figure) in a P-well substrate of the NLDMOS is used as a source region of the NLDMOS, and a connecting electrode is formed in the source region through the N + diffusion layer (the N + diffusion layer 109 in the figure) to be used as a source;
the gate polysilicon crossing the source region and the drain region of the NLDMOS is used as a gate of the NLDMOS, an active region and a field region are arranged below the gate polysilicon of the NLDMOS, the thin oxide region of the active region is used as a gate oxide layer, the field region is positioned above the drain region of the NLDMOS, the active region is positioned above the P well and crosses the P well to intersect the source region and the drain region, and the length of the NLDMOS gate is the length of the intersection of the active region and the P well substrate.
Wherein, the NJFET includes:
the drain region of the NLDMOS is used as the drain region of the NJFET, the P-type substrate of the whole chip and a P-well in an N-type epitaxy are used as the gate region of the NJFET, a P + diffusion layer (a P + diffusion layer 108 in the drawing) in the P-well and a P + diffusion layer (a P + diffusion layer 106 in the drawing) in an upper P-type isolation are used as electrodes to be connected to form a gate, an upper P-type isolation layer and a lower P-type isolation layer (a lower P-type isolation layer 104 in the drawing) form a gate-to-gate isolation, the P-type substrate and the gate are connected, a connection electrode is formed on an N + diffusion layer (an N + diffusion layer 107 in the drawing) on the N-type epitaxy, which is opposite to the gate region of the NLDMOS and close to the source side, and is used as the source of the NJFET, and the N + diffusion layer (an N + diffusion layer 107 in the drawing) of the NJF.
Further, in the composite field effect transistor structure, a P-type lower isolation layer (a P-type lower isolation layer 103 in the drawing) may be arranged between the P-type substrate and the N-type epitaxy near the gate of the NLDMOS and near the drain electrode, or a P-type lower isolation layer (a P-type lower isolation layer 103 in the drawing) may not be arranged;
furthermore, the drain electrode terminals of the NLDMOS and the NJFET of the composite field effect transistor structure can be provided with an N well layer or not;
furthermore, in the composite field effect transistor structure, a P-type diffusion layer is added on an N-type epitaxy used as an NLDMOS drain drift region, namely between a drain leading-out end of an N + diffusion layer (an N + diffusion layer 112 in the attached drawing) of an NLDMOS drain region and a P-well substrate of the NLDMOS, wherein the P-type diffusion layer can be a section or a K section (K is more than 1), and after the P-type diffusion is added, the concentration of the N-type epitaxy can be improved, the on-resistance of the NLDMOS can be reduced, and the optimized design meeting the requirements of high withstand voltage and on-resistance can be realized;
further, in the composite field effect transistor structure, an N + diffusion layer (an N + diffusion layer 109 in the drawing) serving as the source region of the NLDMOS may be included in one N-diffusion layer to improve the withstand voltage of the P-well substrate and the source region of the NLDMOS, or there may be no N-diffusion layer around the N + diffusion 2 of the source region of the NLDMOS, so as to be suitable for use when the voltage of the P-well substrate and the source region of the NLDMOS is low or the P-well substrate and the source region of the NLDMOS are turned on to a potential;
further, the composite type field effect transistor is in a partial central symmetry circular structure, wherein the NLDMOS is in complete central symmetry, and the NJFET is in partial central symmetry. The following description will be made using a field effect transistor structure having an N-well layer, a P-type lower isolation layer (P-type lower isolation layer 103 in the drawing), and an N-diffusion layer. At the center of symmetry is the drain region of the high voltage NLDMOS and high voltage NJFET, which consists of an N + diffused layer (N + diffused layer 112 in the figure), an N-well layer and an N-type epitaxy. The N + diffusion layer (the N + diffusion layer 112 in the drawing) is arranged at a certain distance from the P well, the size of the distance determines the voltage resistance of the NLDMOS and the NJFET, and the N + diffusion layer (the N + diffusion layer 112 in the drawing) is arranged in the N well layer and is positioned at the symmetrical center. The P-type lower isolation layer (P-type lower isolation layer 103 in the figure) for the NLDMOS is located between the P-type substrate of the NLDMOS and the N + diffusion layer (N + diffusion layer 112 in the figure) of the drain of the NLDMOS, and also located between the P-type substrate and the N-type epitaxy. In the composite field effect transistor structure, the outermost layer of the whole NLDMOS and the NJFET is an opposite-through isolation formed by a P-type upper isolation layer and a P-type lower isolation layer (a P-type lower isolation layer 104 in the drawing), the opposite-through isolation is connected to a low potential through a P + diffusion layer (a P + diffusion layer 106 in the drawing) and is connected to an aluminum strip through a contact hole, and the contact hole is an isolation contact hole. The N + diffusion layer (the N + diffusion layer 107 in the drawing) is used as a source contact hole of an NJFET between an isolation contact hole and a P-well substrate of the NLDMOS; the other arc is an N + diffusion layer (N + diffusion layer 107 in the drawing) which is not used as a source contact hole of an NJFET between the isolation contact hole and the P-well substrate of the NLDMOS. The sizes of the two arcs can be changed according to the convenience and the actual requirement of the layout. The P-well is formed between the N + diffusion layer (N + diffusion layer 107 in the drawing) of the source of the NJFET and the N + diffusion layer (N + diffusion layer 112 in the drawing) of the drain of the NLDMOS, and serves as a substrate of the NLDMOS and also serves as a gate of the NJFET. In the substrate of the NLDMOS, there are a P + diffusion layer (P + diffusion layer 108 in the drawing) for a substrate contact hole of the NLDMOS and an N + diffusion layer (N + diffusion layer 109 in the drawing) for a source of the NLDMOS, and the N + diffusion layer (N + diffusion layer 109 in the drawing) for a source of the NLDMOS is also used for the contact hole. The gate polysilicon is arranged above the edge of the source electrode of the NLDMOS and the side close to the drain region, crosses between the substrate of the NLDMOS and the drain region of the NLDMOS, two sections of oxide layers are arranged below the gate polysilicon, one section of the oxide layer is a thin oxide layer, the other section of the oxide layer is a thick oxide layer, the thin oxide layer crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlapping size with the source electrode of the NLDMOS, the size of the overlapping is determined by the lateral diffusion of an N + diffusion layer (an N + diffusion layer 109 in the drawing), and the thick oxide layer is arranged above an N-type epitaxy used as the drain region. The gate polysilicon is connected to the aluminum bar through the contact hole, and the gate polysilicon is the gate of the NLDMOS. The N + diffusion layer (the N + diffusion layer 109 in the drawing) of the NLDMOS source region can be included in one N-diffusion layer to improve the withstand voltage of the NLDMOS substrate and the source region.
Utilize the utility model discloses a compound field effect transistor structure can effectively reduce chip area when the same voltage is applyed to NLDMOS and NJFET's high-voltage terminal, can not only provide NLDMOS's grid initial voltage, still can effectively turn-off NLDMOS to greatly reduce the consumption.
Drawings
Various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,
fig. 1 shows an overall longitudinal sectional structural diagram of the composite field effect transistor of the present invention;
fig. 2 shows a schematic diagram of a longitudinal cross-sectional structure of the composite fet of the present invention with complete central symmetry;
fig. 3 is a schematic diagram showing a longitudinal cross-sectional structure of a composite fet of the present invention with a P-type diffusion 539;
fig. 4 is a schematic diagram showing a longitudinal cross-sectional structure of the composite field effect transistor of the present invention without the N-well layer 111;
fig. 5 shows a schematic longitudinal sectional structure of the composite fet of the present invention without the P-type lower isolation 103;
fig. 6 is a schematic diagram showing a longitudinal cross-sectional structure of the composite fet of the present invention having an N-diffusion layer 640;
fig. 7 is a longitudinal view and a top view of the composite fet of the present invention showing central symmetry;
fig. 8 is a longitudinal view and a top view of the composite fet of the present invention showing partial central symmetry; while
Fig. 9 is a schematic circuit diagram of the NLDMOS and the NJFET corresponding to fig. 1 to 8.
Detailed Description
Various embodiments of the present invention will now be described in further detail with reference to the accompanying drawings.
Fig. 2 shows an embodiment of the composite fet of the present invention.
As shown in fig. 2, the composite type field effect transistor exhibits perfect central symmetry and has a P-type lower isolation layer 103 and an N-well layer 111. The P-type lower isolation layer 103 is located near the gate polysilicon 130 of the NLDMOS and between the P-type substrate 101 and the N-type epitaxy 102 on the side close to the drain electrode, and the N-well layer 111 is located at the drain electrode terminals of the NLDMOS and the NJFET. In the composite field effect transistor structure, the NLDMOS and the NJFET share one drain region, a P-well substrate of the NLDMOS and a P-type substrate 101 of the whole chip are used as a grid region of the NJFET, a P-type upper isolation layer 105 and a P-type lower isolation layer 104 are used for forming an opposite-pass isolation around the whole NLDMOS and the NJFET, and the NLDMOS and the NJFET are separated from other elements on the chip where the structure is located. An N + diffusion layer 107 is arranged between the P-well substrate of the N-type laterally diffused metal oxide semiconductor (NLDMOS) and the P-well substrate of the NLDMOS to serve as a source region of the NJFET. The N-type epitaxy 102 is both the drain drift region of the NLDMOS and the body region of the NJFET.
Fig. 3 is added with a P-type diffusion layer 539 on the basis of fig. 2, and the P-type diffusion layer 539 is located between a drain terminal of the N + diffusion layer 112 of the NLDMOS drain region and a P-well substrate of the NLDMOS. After the P-type diffusion layer 539 is added, the basic characteristics of the whole chip are unchanged, the concentration of the N-type epitaxy 102 can be improved, and the on-resistance of the NLDMOS is reduced, so that the optimal design of the chip is realized.
Fig. 4 is a view of fig. 2 with an N-well layer 111 removed. The structure without the N well layer 111 can increase the on-resistance of the NLDMOS and the NJFET, and is suitable for being applied to circuits with low on-resistance requirements.
Fig. 5 is a diagram of fig. 2, in which a P-type lower isolation layer 103 is removed, and the structure without the P-type lower isolation layer 103 can improve the pinch-off characteristic of the NJFET, so that the NJFET has a better constant current characteristic.
Fig. 6 adds an N-diffused layer 640 to that of fig. 2. The N-diffusion layer 640 is positioned in the P-well substrate 110, and the N + diffusion layer 109 of the NLDMOS source region is contained in the N-diffusion layer 640, so that the withstand voltage value between the substrate and the source terminal of the NLDMOS can be improved, and the N-diffusion layer is suitable for being applied to circuits which need to bear larger withstand voltage at the substrate and the source terminal.
Fig. 7 shows yet another embodiment of the composite fet structure of the present invention. As shown in fig. 7, the entire structure exhibits a completely centrosymmetric circular structure having an N-well layer 111 and a P-type lower isolation layer 103 therein. Located at the center is the drain of the high voltage NLDMOS and high voltage NJFET, which is composed of N + diffused layer 112, N-well layer 111 and N-type epitaxy 102. The N-well layer 111 is spaced from the P-well 110 within the N-type epitaxy 102 by a distance, the size of the distance determines the breakdown voltage of the NLDMOS and the NJFET, and the N + diffusion layer 112 is located at the center within the N-well layer 111 (in a structure without the N-well layer 111, the N + diffusion layer 112 is located at the center). Looking outward from the center of symmetry, the P-type lower isolation layer 103 for the NLDMOS is located between the substrate of the NLDMOS and the N + diffused layer 112 of the NLDMOS drain, and also between the P-type base 101 and the N-type epitaxy 102. The outermost layer of the whole NLDMOS and the NJFET is an opposite-through isolation layer formed by a P-type upper isolation layer 105 and a P-type lower isolation layer 104, the opposite-through isolation layer is connected to a low potential through a contact hole connecting aluminum strip through a P + diffusion layer 106, and the contact hole is an isolation contact hole. Between the isolation contact hole and the P-well substrate of the NLDMOS is an N + diffusion layer 107 serving as a source contact hole of the NJFET, and between the source N + diffusion layer 107 of the NJFET and the N + diffusion layer 112 of the drain of the NLDMOS is a P-well 110 serving as a substrate of the NLDMOS and also serving as one gate of the NJFET. The P + diffusion layer 108 in the NLDMOS substrate serves as a substrate contact hole of the NLDMOS, the N + diffusion layer 109 in the NLDMOS substrate serves as a source of the NLDMOS, and the N + diffusion layer 109 of the source of the NLDMOS is also used as a contact hole. A grid polysilicon 130 is arranged above the edge of a source electrode of the NLDMOS and the side close to the drain region and crosses between a substrate of the NLDMOS and the drain region of the NLDMOS, two sections of oxide layers are arranged below the grid polysilicon 130, one section is a thin oxide layer 129, the other section is a thick oxide layer, the thin oxide layer 129 crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlapping size with the source electrode of the NLDMOS, the size of the overlapping is determined by the lateral diffusion of an N + diffusion layer 109, and the thick oxide layer is arranged above an N-type epitaxy 102 used as the drain region of the NLDMOS. The gate polysilicon 130 is connected to the aluminum bar through the contact hole, and the gate polysilicon 130 is the gate of the NLDMOS. The N + diffusion layer 109 of the NLDMOS source region can be included in one N-diffusion layer 640 to improve the withstand voltage of the NLDMOS substrate and the source region.
Fig. 8 is yet another embodiment of a composite fet structure according to the present invention. The composite field effect transistor has a circular structure with partial central symmetry, wherein the NLDMOS has complete central symmetry, and the NJFET has partial central symmetry. The composite type field effect transistor has an N-well layer 111, a P-type lower isolation layer 103, and an N-diffusion layer 640. At the center of symmetry is the drain region of the NLDMOS and NJFET, which consists of N + diffused layer 112, N-well layer 111 and N-type epitaxy 102. The N + diffusion layer 112 is spaced from the P-well 110 by a distance, the size of the distance determines the withstand voltage of the NLDMOS and the NJFET, and the N + diffusion layer 112 is located at the symmetrical center in the N-well layer 111. The P-type lower isolation layer 103 for the NLDMOS is located between the P-type substrate 101 of the NLDMOS and the N + diffusion layer 112 of the drain of the NLDMOS, and also located between the P-type substrate 101 and the N-type epitaxy 102. In the composite field effect transistor structure, the outermost layer of the whole NLDMOS and the NJFET is a P-type upper isolation layer 105 and a P-type lower isolation layer 104 which form a pair of through isolation, the pair of through isolation passes through a P + diffusion layer 106, and is connected with an aluminum strip through a contact hole to be connected with a low potential, and the contact hole is an isolation contact hole. The N + diffusion layer 107 is divided into two sections of arcs in the same pattern, wherein the two sections of arcs are used as source contact holes of an NJFET between an isolation contact hole and a P-well substrate of the NLDMOS; the other arc is an N + diffusion layer 107 without a source contact hole serving as an NJFET between the isolation contact hole and the P-well substrate of the NLDMOS. The sizes of the two arcs can be changed according to the convenience and the actual requirement of the layout. Between the source N + diffused layer 107 and the NLDMOS source N + diffused layer 112 of the NJFET is a P-well 110 that serves as the substrate for the NLDMOS and one gate for the NJFET. In the substrate of the NLDMOS, a P + diffusion layer 108 for a substrate contact hole of the NLDMOS and an N + diffusion layer 109 for a source of the NLDMOS are provided, and the N + diffusion layer 109 for the source of the NLDMOS is also provided for the contact hole. The gate polysilicon 130 crosses between the substrate of the NLDMOS and the drain region of the NLDMOS at the edge of the source of the NLDMOS and above the side close to the drain region, two sections of oxide layers are arranged below the gate polysilicon 130, one section is a thin oxide layer 129, the other section is a thick oxide layer, the thin oxide layer 129 crosses between the substrate of the NLDMOS and the drain region of the NLDMOS and has an overlap with the source of the NLDMOS, the size of the overlap is determined by the lateral diffusion of the N + diffusion layer 109, and the thick oxide layer is positioned above the N-type epitaxy 102 serving as the drain region of the NLDMOS. The gate polysilicon 130 is connected to the aluminum bar through the contact hole, and the gate polysilicon 130 is the gate of the NLDMOS. The N + diffusion layer 109 of the NLDMOS source region can be included in one N-diffusion layer 640 to improve the withstand voltage of the NLDMOS substrate and the source region.
Fig. 9 shows a schematic circuit structure of the NLDMOS and the NJFET corresponding to fig. 1 to 8. Wherein, NJFET431 and NLDMOS432 correspond to NJFET and NLDMOS in FIG. 1 respectively; the gate 433 of the NJFET431 corresponds to the isolated contact extraction electrode 113 and the P-well extraction electrode 115 in fig. 1-8, the source 434 of the NJFET431 corresponds to the source extraction electrode 114 in fig. 1-8, and the common drain 437 of the NJFET431 and the NLDMOS432 corresponds to the drain extraction 118 in fig. 1-8. The substrate 438 of the NLDMOS432 corresponds to the P-well terminal 115 in fig. 1-8, the gate 435 of the NLDMOS432 corresponds to the gate 130 of the NLDMOS in fig. 1-8, and the source 436 of the NLDMOS432 corresponds to the source 116 of the NLDMOS in fig. 1-8.
Hereinbefore, specific embodiments of the present invention have been described with reference to the accompanying drawings. However, it will be understood by those skilled in the art that various changes and substitutions can be made in the field effect transistor type, the functional layer length, etc. in the embodiments of the present invention without departing from the spirit and scope of the present invention. Such modifications and substitutions fall within the scope of the present invention as defined by the appended claims.
Claims (19)
1. A field effect transistor structure, comprising: lateral double diffused metal oxide field effect transistors (LDMOS) and Junction Field Effect Transistors (JFET).
2. The fet structure of claim 1, wherein the LDMOS and the JFET each have respective source and gate regions, and wherein the LDMOS and the JFET share the same drain region.
3. The structure of claim 1, wherein the LDMOS and the JFET are both enhancement mode N-type field effect transistors.
4. The structure of claim 3, wherein the NLDMOS comprises: a P-type substrate (101); an N-type epitaxy (102); and a P well (110) positioned in the N-type epitaxy (102) is used as a substrate of the NLDMOS, and a P + diffusion layer (108) on the NLDMOS substrate forms a connecting electrode which is used as a substrate connecting end (438) of the NLDMOS.
5. The structure of claim 3, characterized by a drain region formed by an N + diffused layer (112) within the N-type epitaxy (102), wherein the N + diffused layer (112) of the N-type epitaxy (102) forms a connecting electrode as a common drain (437) for the NLDMOS and the NJFET.
6. The structure of claim 3, characterized in that an N + diffusion layer (109) in the substrate of the NLDMOS is used as a source region of the NLDMOS, and a connection electrode is formed through the N + diffusion layer (109) as a source (436) of the NLDMOS.
7. The structure of claim 3, wherein a gate polysilicon (130) spanning the P-well (110) between the source and drain regions of the NLDMOS and intersecting both the source and drain regions of the NLDMOS serves as a gate (435) of the NLDMOS.
8. The structure of claim 3, wherein the P-type substrate (101) and the P-well (110) in the N-type epitaxy (102) serve as gate regions of the NJFETs, and wherein the P + diffusion layer (108) in the P-well (110) and the P + diffusion layer (106) in the upper P-type isolation layer (105) form a connection electrode serving as a gate electrode (433) of the NJFETs.
9. The structure of claim 3, wherein an N + diffusion layer (107) on the N-type epitaxy (102) opposite to the NLDMOS gate and near the source side forms a connecting electrode as the source (434) of the NJFET.
10. The structure of claim 9, wherein the N + diffused layer (107) of the NJFET source (434) is located between the substrate of the NLDMOS and the P-type top spacer (105).
11. A structure as claimed in claim 3, characterized in that near the NLDMOS gate (435) and near the side of the drain electrode, there is also a P-type lower spacer (103) between the P-type substrate (101) and the N-type epitaxy (102).
12. The structure of claim 3, further comprising a Nwell layer (111) at the drain terminals of the NLDMOS and the NJFET.
13. The structure of claim 3, characterized in that a P-type diffusion (539) is added between the N + diffusion layer (112) of the NLDMOS drain region and the P-well substrate of the NLDMOS, and the P-type diffusion (539) can be a segment.
14. The structure of claim 3, characterized in that a P-type diffusion (539) is added between the N + diffusion layer (112) of the NLDMOS drain region and the P-well substrate of the NLDMOS, and the P-type diffusion (539) can be K-segment (K > 1).
15. The structure of claim 3, further characterized in that an N-diffused layer (640) is between said P-well (110) and said N + diffused layer (109), and said N-diffused layer (640) comprises said N + diffused layer (109) which serves as said NLDMOS source region.
16. A structure as claimed in claim 3, characterized in that the compound field effect transistor can assume a completely centrosymmetric circular structure.
17. The structure according to claim 3, wherein the compound type field effect transistor may exhibit a partially centrosymmetric circular structure.
18. The structure of claim 17, wherein the composite fet exhibits a circular configuration with partial centrosymmetry, the NLDMOS exhibits full centrosymmetry, and the NJFET exhibits partial centrosymmetry.
19. The structure of claim 1, wherein an upper P-type isolation layer (105) and a lower P-type isolation layer (104) are used to form an on-channel isolation around the entire periphery of the LDMOS and the JFET, and wherein the LDMOS and the JFET are separated from other components on the chip on which the structure is located by the on-channel isolation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620159594 CN200979884Y (en) | 2006-11-24 | 2006-11-24 | A compound structure of a field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620159594 CN200979884Y (en) | 2006-11-24 | 2006-11-24 | A compound structure of a field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200979884Y true CN200979884Y (en) | 2007-11-21 |
Family
ID=38980266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620159594 Expired - Fee Related CN200979884Y (en) | 2006-11-24 | 2006-11-24 | A compound structure of a field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN200979884Y (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000626A (en) * | 2012-11-28 | 2013-03-27 | 深圳市明微电子股份有限公司 | High-voltage device in composite structure and starting circuit |
| CN102044540B (en) * | 2009-10-22 | 2013-12-11 | 联华电子股份有限公司 | Semiconductor device and method of operation thereof |
| CN103700711A (en) * | 2014-01-09 | 2014-04-02 | 帝奥微电子有限公司 | Junction type field effect tube structure |
| CN103887961A (en) * | 2014-04-18 | 2014-06-25 | 杭州士兰微电子股份有限公司 | Switching power supply and controller thereof |
| CN103904078A (en) * | 2012-12-28 | 2014-07-02 | 旺宏电子股份有限公司 | High Voltage Junction Field Effect Transistor Structure |
-
2006
- 2006-11-24 CN CN 200620159594 patent/CN200979884Y/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044540B (en) * | 2009-10-22 | 2013-12-11 | 联华电子股份有限公司 | Semiconductor device and method of operation thereof |
| CN103000626A (en) * | 2012-11-28 | 2013-03-27 | 深圳市明微电子股份有限公司 | High-voltage device in composite structure and starting circuit |
| WO2014082469A1 (en) * | 2012-11-28 | 2014-06-05 | 深圳市明微电子股份有限公司 | High-voltage device of composite structure and starting circuit |
| EP2765604A4 (en) * | 2012-11-28 | 2015-05-27 | Shenzhen Sunmoon Microelectronics Co Ltd | HIGH VOLTAGE COMPOSITE STRUCTURE DEVICE AND START CIRCUIT |
| CN103000626B (en) * | 2012-11-28 | 2015-08-26 | 深圳市明微电子股份有限公司 | The high tension apparatus of composite structure and start-up circuit |
| CN103904078A (en) * | 2012-12-28 | 2014-07-02 | 旺宏电子股份有限公司 | High Voltage Junction Field Effect Transistor Structure |
| CN103700711A (en) * | 2014-01-09 | 2014-04-02 | 帝奥微电子有限公司 | Junction type field effect tube structure |
| CN103700711B (en) * | 2014-01-09 | 2017-01-25 | 帝奥微电子有限公司 | Junction type field effect tube structure |
| CN103887961A (en) * | 2014-04-18 | 2014-06-25 | 杭州士兰微电子股份有限公司 | Switching power supply and controller thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1244160C (en) | Semiconductor device | |
| CN1276516C (en) | Field Effect Transistor and Its Application Devices | |
| US9418993B2 (en) | Device and method for a LDMOS design for a FinFET integrated circuit | |
| CN104752493B (en) | Power semiconductor device | |
| CN1286186C (en) | SOI LDMOS transistor structure having improved switching characteristics | |
| CN1695255A (en) | Semiconductor component and method of manufacturing same | |
| US9543451B2 (en) | High voltage junction field effect transistor | |
| CN1641886A (en) | Isolated high voltage LDMOS transistor with a split well structure | |
| CN1925170A (en) | Lateral double-diffused field effect transistor and integrated circuit having same | |
| CN105655390A (en) | Split gate field effect transistor | |
| CN101677109A (en) | Semiconductor device and method for making the same | |
| CN1324716C (en) | Semiconductor device | |
| CN1433083A (en) | Double-diffused MOSFET and semiconductor device | |
| WO2011131030A1 (en) | Power device and method for performing conductivity modulation by using photoelectron injection | |
| CN200979884Y (en) | A compound structure of a field effect transistor | |
| CN1108814A (en) | Transistor with common base region | |
| CN100580928C (en) | A composite type field effect transistor structure and manufacturing method thereof | |
| CN1407609A (en) | Field effect transistor formed on insulative substrate and its integrated circuit thereof | |
| CN1799144A (en) | Termination structures for semiconductor devices and the manufacture thereof | |
| CN1677664A (en) | Device for electrostatic discharge protection and method of manufacturing the same | |
| US7768068B1 (en) | Drain extended MOS transistor with increased breakdown voltage | |
| WO2006134810A1 (en) | Semiconductor device | |
| US8120096B2 (en) | Power semiconductor device and method of manufacturing the same | |
| CN117594531A (en) | Semiconductor integrated circuit and method for manufacturing the same | |
| CN112909082B (en) | A high-voltage low-resistance power LDMOS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071121 Termination date: 20111124 |