CN200976345Y - Chip packaging structure - Google Patents

Abstract

A chip packaging structure includes a carrier, at least one chip, a heat sink and a heat conducting medium. The chip is disposed on the carrier and electrically connected to the carrier. The heat sink is disposed on the carrier, wherein the heat sink and the carrier together form a closed space, and the chip is located in the closed space, and the heat conducting medium fills the closed space. In addition, a manufacturing method of the chip packaging structure is also proposed.

Description

Chip package structure

technical field

The utility model relates to a chip packaging structure, in particular to a chip packaging structure with improved heat dissipation efficiency.

Background technique

In the semiconductor industry, the production of integrated circuits (IC) can be divided into three stages: integrated circuit design (IC design), integrated circuit production (IC process) and integrated circuit packaging (IC package).

In the manufacture of integrated circuits, chips are completed through the steps of wafer manufacturing, forming integrated circuits, and wafer sawing. The chip has an active surface, which generally refers to the surface of the chip with active elements. After the integrated circuit inside the wafer is completed, the active surface of the wafer is further equipped with a plurality of bonding pads (bonding pads), so that the chips formed by wafer dicing can be electrically connected to a carrier through these bonding pads ( carrier). The carrier is, for example, a leadframe or a package substrate. The chip can be connected to the carrier by wire bonding or flip chip bonding, so that the pads of the chip can be electrically connected to the contacts of the carrier to form a chip package structure.

As far as flip chip bonding technology is concerned, usually after forming these pads on the active surface of the chip, a bump (bump) will be made on each pad to electrically connect the chip to the external package. Substrate use. Since these bumps are usually arranged in an area array on the active surface of the chip, the flip chip bonding technology is suitable for use in chip packaging structures with high contact count and high contact density. For example, it has been widely used in the semiconductor packaging industry. Flip chip/ball grid array package (flip chip/ball grid array package). In addition, compared with the wire bonding technology, the flip chip bonding technology can improve the electrical performance of the chip packaging structure because the bumps can provide a shorter transmission path between the chip and the carrier.

In the existing flip-chip bonding process, after the chip is electrically connected and fixed on the substrate via a plurality of bumps, in order to enhance the heat dissipation effect of the chip, a radiator with a cavity (cavity) is usually placed. The heat spreader) is attached to the back of the chip through thermal adhesive, so that the chip is located in the groove of the heat sink disposed on the substrate. When the existing chip packaging structure is in operation, the heat generated by the chip is mainly transferred to the external environment through the heat dissipation glue and the heat sink on the back of the chip, so the temperature of the part of the heat sink that is directly thermally coupled to the back of the chip is relatively high. , while the temperature of other parts of the radiator is lower. In other words, the heat dissipation efficiency of the heat sink of the existing chip packaging structure is poor. However, with the design trend of high energy consumption and high frequency during chip operation, the heat dissipation efficiency of the existing heat sink attached to the chip is no longer sufficient. Therefore, it is necessary to improve the heat dissipation efficiency of the existing chip package structure. necessity.

Utility model content

The purpose of the utility model is to provide a chip packaging structure, the heat dissipation efficiency of which is improved.

To achieve the above or other purposes, the present invention provides a chip packaging structure, which includes a carrier, at least one chip, a heat sink and a thermal interface material (TIM). The chip is configured on the carrier and electrically connected to the carrier. The radiator is disposed on the carrier, wherein the radiator and the carrier together form a closed space, and the chip is located in the closed space. In addition, the heat transfer medium fills the confined space.

To achieve the above or other purposes, the present invention provides a chip packaging structure, which includes a carrier, at least one chip, a heat sink and a heat conducting medium. The chip is configured on the carrier and electrically connected to the carrier. The heat sink is arranged on the carrier, wherein the heat sink and the carrier together form a closed space, and the chip is located in the closed space. In addition, the thermally conductive medium is located in the closed space, wherein the thermally conductive medium is in contact with the inner surface of the heat sink.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described below in detail with accompanying drawings.

Description of drawings

FIG. 1A shows a schematic cross-sectional view of a chip packaging structure according to the first embodiment of the present invention;

FIG. 1B shows a schematic cross-sectional view of another chip packaging structure of the first embodiment of the present invention;

FIG. 2A to FIG. 2G are schematic flowcharts illustrating a manufacturing method of the chip packaging structure of FIG. 1A;

FIG. 3 is a schematic cross-sectional view of a chip packaging structure according to the second embodiment of the present invention.

Explanation of reference signs

10: Confined space 20: Accommodating space

100, 100', 200: Chip package structure 110, 210: Carrier

112.: Bearing surface 120. 220: chip

130, 130': Radiator 132: Heat sink body

132a: inner surface of heat dissipation plate 134: heat dissipation ring

134a: inner surface of heat dissipation ring 136: groove

138: Inner surface of radiator 139: Fins

140: heat conduction medium 150: conductive bump

160: Primer layer H: Height

Detailed ways

Please refer to FIG. 1A , which is a schematic cross-sectional view of a chip packaging structure according to a first embodiment of the present invention. The chip package structure 100 of the first embodiment includes a carrier 110 , at least one chip 120 , a heat sink 130 and a heat conducting medium 140 . The chip 120 is disposed on the carrier 110 and electrically connected to the carrier 110 . The heat sink 130 is disposed on the carrier 110 , wherein the heat sink 130 and the carrier 110 jointly form a closed space 10 , and the chip 120 is located in the closed space 10 . In addition, the heat transfer medium 140 fills the closed space 10 .

It is worth noting that when the chip package structure 100 is in operation, since the thermally conductive medium 140 fills the enclosed space 10 , the heat generated by the chip 120 can be transferred to the heat sink 130 through the thermally conductive medium 140 in a conductive manner. It can be seen from the thick black arrow in FIG. 1 that the heat generated by the chip 120 of this embodiment can be transferred to the heat sink 130 in a conductive manner not only from the back of the chip 120 but also from the side of the chip 120 . Therefore, compared with the prior art, the temperature of the heat sink 130 of this embodiment is more uniform (uniform), in other words, the heat dissipation efficiency of the chip packaging structure 100 of this embodiment is better.

The thermally conductive medium 140 can be thermally conductive compound or thermally conductive elastomer. Specifically, the thermal conduction medium 140 can be solder paste, thermal grease, or epoxy resin added with silicon dioxide or silver. The heat conducting medium 140 may also include metal materials such as tin or lead. It must be noted here that the heat conduction medium 140 can be changed according to the designer's requirements, and the first embodiment is only used as an example rather than limiting the present invention.

In detail, the radiator 130 of the first embodiment includes a thermal plate 132 and a thermal ring 134 . The heat dissipation ring 134 is disposed on the heat dissipation plate 132 , and the heat dissipation ring 134 and the heat dissipation plate 132 jointly form a groove 136 , and the heat dissipation ring 134 is located between the heat dissipation plate 132 and the carrier 110 . As can be seen from FIG. 1 , in the first embodiment, the enclosed space 10 can be jointly formed by the heat dissipation plate body 132 , the heat dissipation ring body 134 and the carrier 110 , and the inner surface of the heat conducting medium 140 and the heat sink 130 that fills the enclosed space 10 138 contacts. In other words, the heat conducting medium 140 of the first embodiment is in contact with the inner wall of the groove 136 of the heat sink 130 .

It must be noted here that the heat dissipation plate body 132 and the heat dissipation ring body 134 of the first embodiment can be formed separately in advance, and then processed and joined together (see later for details), but the heat dissipation plate body 132 and the heat dissipation ring body 134 It can also be integrally formed according to design requirements. In addition, please refer to FIG. 1B , which is a schematic cross-sectional view of another chip packaging structure according to the first embodiment of the present invention. The heat sink 130' of the chip package structure 100' further includes a plurality of fins (fin) 139, which are disposed on the side of the heat dissipation plate 132 opposite to the heat dissipation ring 134. In other words, the fins 139 extend from the heat sink body 132 in a direction away from the chip 120 . The function of these fins 139 is to increase the heat exchange area between the radiator 130' and the external environment, thereby improving the heat dissipation efficiency of the radiator 130'.

Please refer to FIG. 1A again, the chip packaging structure 100 of the first embodiment further includes a plurality of conductive bumps 150 and an underfill layer 160, and the carrier 110 can be a circuit board. The conductive bumps 150 are disposed between the chip 120 and the carrier 110 , and the primer layer 160 covers the conductive bumps 150 . The primer layer 160 is used to protect the conductive bumps 150 , and when the chip package structure 100 operates to generate heat, the primer layer 160 can buffer the thermal strain (thermal strain) generated between the heated carrier 110 and the heated chip 120 . strain) mismatch phenomenon.

The manufacturing method of the chip packaging structure 100 of the first embodiment will be described in detail below. 2A to FIG. 2G are schematic flowcharts of the manufacturing method of the chip packaging structure shown in FIG. 1A . The manufacturing method of the chip packaging structure 100 of the first embodiment includes the following steps. First, please refer to FIG. 2A , a carrier 110 is provided. Next, please refer to FIG. 2B , disposing at least one chip 120 on the carrier 110 . Next, the chip 120 is electrically connected to the carrier 110 .

In the first embodiment, the above-mentioned steps of disposing the chip 120 on the carrier 110 and electrically connecting to the carrier 110 are completed by flip-chip bonding technology, which includes the following sub-steps. First, a plurality of conductive bumps 150 are formed on the chip 110 by electroplating, for example. After that, the chip 120 is disposed on the carrier 110 , and the conductive bumps 150 are reflowed, so that the conductive bumps 150 are electrically connected between the chip 120 and the carrier 110 . Finally, a primer layer 160 is formed to cover the conductive bumps 150 . The underfill layer 160 is usually completed by filling an underfill between the chip 120 and the carrier 110 and baking.

Afterwards, please refer to FIG. 2C , for example, a heat dissipation ring 134 is disposed on the carrier 110 in an adhesive manner, so that the heat dissipation ring 134 surrounds the chip 120 . Afterwards, referring to FIG. 2D , a heat conduction medium 140 is filled into a containing space 20 surrounded by the heat dissipation ring 134 on the carrier 110 , so that the heat conduction medium 140 covers the chip 120 .

Then, please refer to FIG. 2E , in the first embodiment, after the above-mentioned step of filling the accommodating space 20 with the heat-conducting medium 140 , the gas inside the heat-conducting medium 140 can be extracted. If the heat-conducting medium 140 is solid, the gas inside the heat-conducting medium 140 can be extracted by vacuum extraction; The gas inside is pumped away. It must be noted here that after the gas inside the heat transfer medium 140 is pumped away, the height H of the heat transfer medium 140 will generally decrease.

Next, please refer to FIG. 2F , and then fill in the heat conduction medium 140 to fill up the accommodating space 20 and cover the chip 120 . Then, please refer to FIG. 2G , for example, a heat dissipation plate body 132 is disposed on the heat dissipation ring body 134 by adhesion or welding, so that the heat dissipation plate body 132 covers the chip 120, and the heat conduction medium 140 is filled by the heat dissipation plate body 132, heat dissipation The ring body 134 and the carrier 110 jointly form a closed space 10 . Wherein, the heat dissipation plate body 132 and the heat dissipation ring body 134 compose the heat sink 130 of this embodiment.

Please refer to FIG. 1A , in the first embodiment, the aforementioned enclosed space 10 is bounded by the inner surface 132a of the heat dissipation plate 132 , the inner surface 134a of the heat dissipation ring 134 and the carrying surface 112 of the carrier 110 . The inner surface 138 of the radiator 130 is composed of the inner surface 132 a of the heat dissipation plate 132 and the inner surface 134 a of the heat dissipation ring 134 . After the heat conduction medium 140 is filled into the enclosed space 10 , the heat conduction medium 140 will be in contact with the inner surface 138 and the bearing surface 112 . That is, the heat conduction medium 140 covers the inner surface 132 a of the heat dissipation plate body 132 , the inner surface 134 a of the heat dissipation ring 134 and the carrying surface 112 of the carrier 110 .

Please refer to FIG. 3 , which shows a schematic cross-sectional view of a chip packaging structure according to a second embodiment of the present invention. The main difference between the chip packaging structure 200 of the second embodiment and the chip packaging structure 100 of the first embodiment is that the chip packaging structure 200 of the second embodiment includes a plurality of chips 220 . The chips 220 are electrically connected to each other and are arranged on the carrier 210 in a stacked manner. It should be noted here that the quantity of these chips 220 and the manner of disposing them on the carrier 210 can be changed according to the designer's requirements. This embodiment is only used to illustrate rather than limit the utility model.

To sum up, the chip packaging structure of the present invention and its manufacturing method have at least the following advantages:

1. When the chip packaging structure of the present invention is in operation, since the heat-conducting medium fills the confined space, the heat generated by the chip can be transferred to the radiator through the heat-conducting medium in a conductive manner. Therefore, the heat generated by the chip of the present invention can be transferred to the radiator in a conduction manner not only from the back of the chip but also from the side of the chip. It can be known from the above that, compared with the prior art, the internal temperature of the heat sink of the present invention is more uniform, that is, the heat dissipation efficiency of the chip packaging structure of the present invention is better.

2. Since the steps of the manufacturing method of the chip packaging structure of the present invention can be integrated with existing processes, the manufacturing cost of the chip packaging structure of the present invention with improved heat dissipation efficiency is relatively low.

Although the present utility model has been disclosed above with preferred embodiments, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications without departing from the spirit and scope of the present utility model. and retouching, so the scope of protection of the present utility model should be defined by the appended claims.

Claims (10)

1. chip-packaging structure is characterized in that comprising:

One carrier;

At least one chip is disposed on this carrier and is electrically connected to this carrier;

One radiator is disposed on this carrier, and wherein this radiator and this carrier are common forms a confined space, and this chip is positioned at this confined space; And

One heat-conducting medium fills up this confined space.

2. chip-packaging structure as claimed in claim 1 is characterized in that this radiator comprises:

One heat radiation plate body; And

One heat radiation ring body is disposed on this heat radiation plate body, and wherein should dispel the heat ring body and this heat radiation plate body form a groove jointly, and this heat dissipating ring body is positioned between this heat radiation plate body and this carrier.

3. chip-packaging structure as claimed in claim 2 is characterized in that this heat radiation plate body and this heat radiation ring body are formed in one.

4. chip-packaging structure as claimed in claim 2 is characterized in that this radiator more comprises a plurality of fins, and it is disposed on the side with respect to this heat radiation ring body of this heat radiation plate body.

5. chip-packaging structure as claimed in claim 1 is characterized in that more comprising:

A plurality of conductive projections are disposed between this chip and this carrier; And

One primer layer coats those conductive projections.

6. chip-packaging structure is characterized in that comprising:

One carrier;

At least one chip is disposed on this carrier and is electrically connected to this carrier;

One radiator is disposed on this carrier, and wherein this radiator and this carrier are common forms a confined space, and this chip is positioned at this confined space; And

One heat-conducting medium is positioned at this confined space, and wherein this heat-conducting medium contacts with the inner surface of this radiator.

7. chip-packaging structure as claimed in claim 6 is characterized in that this radiator comprises:

One heat radiation plate body; And

One heat radiation ring body is disposed on this heat radiation plate body, and wherein should dispel the heat ring body and this heat radiation plate body form a groove jointly, and this heat dissipating ring body is positioned between this heat radiation plate body and this carrier.

8. chip-packaging structure as claimed in claim 7 is characterized in that this heat radiation plate body and this heat radiation ring body are formed in one.

9. chip-packaging structure as claimed in claim 7 is characterized in that this radiator more comprises a plurality of fins, and it is disposed on the side with respect to this heat radiation ring body of this heat radiation plate body.

10. chip-packaging structure as claimed in claim 6 is characterized in that more comprising:

A plurality of conductive projections are disposed between this chip and this carrier; And

One primer layer coats those conductive projections.

Images