CN206532784U - Switching power semiconductor devices - Google Patents

Abstract

The utility model relates to the technical field of power semiconductor devices, and specifically discloses a switch-type power semiconductor device. The device includes a silicon layer having opposing first and second surfaces, the first surface being divided into an active region and a junction termination region, the active region being surrounded by the junction termination region ; The second surface is divided into a first ion-doped region directly corresponding to the active region and a first ion-doped region corresponding to the junction terminal region, whose concentration of doping ions is lower than that of the first ion-doped region. Two ion-doped regions, the first ion-doped region is surrounded by the second ion-doped region, and further includes a metal layer bonded to the second surface. The utility model can reduce the free carrier concentration and current density in the device junction terminal area, reduce impact ionization and dynamic avalanche breakdown, and reduce the latch-up damage of edge cells due to current concentration, thereby improving the overall safe working area of the device .

Description

Switching Power Semiconductor Devices

technical field

The utility model relates to the technical field of power semiconductor devices, in particular to a switch type power semiconductor device.

Background technique

In the junction termination area of typical power devices such as MOSFET, IGBT, FRD, etc., the field limiting ring structure and field plate structure are generally included, which help the device to withstand high reverse withstand voltage. During the device turn-off or reverse recovery process, the current concentration phenomenon shown in Figure 1 is prone to occur, specifically because the ion implantation covers the entire second surface area (that is, the three parts in Figure 1 are all implanted with the same ion concentration. ) forms a current concentration in the junction termination region. And there will be relatively high carrier (minority carrier) concentration in the area with high local electric field, resulting in high impact ionization and dynamic avalanche, affecting (reducing) the safe operating area (SOA) of the device.

To avoid the above phenomenon, the most commonly used effective way is to reduce the free carrier concentration at the junction terminal, thereby reducing impact ionization and dynamic avalanche breakdown. The specific method is to reduce the ion implantation dose of the second surface, so as to reduce the implantation efficiency of the emission region of the second surface, so as to achieve the purpose of reducing the charge concentration flowing to the active region of the first surface. However, this will result in a small amount of charge in the entire chip body, a reduction in the ability to transmit current, that is, an increase in the on-resistance of the device.

The second surface of the power semiconductor device needs a higher doping concentration, so that the metal on the back can form a good ohmic contact with the silicon substrate. Usually, a layer of ion implantation with a higher concentration is performed on the second surface, followed by an annealing of the furnace tube to achieve the purpose of activating the implanted ions and repairing the implantation damage. Due to the limitation of the first surface metal layer, the annealing temperature of the furnace tube is low, and the activation rate of implanted ions is low, so a high dose of ion implantation is required. However, high-dose ion implantation will cause damage to the silicon substrate, resulting in large device leakage. Moreover, if the annealing temperature of the furnace tube is low, the ability to repair damage is relatively low, and a large amount of residual damage will also cause leakage of the device.

Utility model content

In view of the current concentration in the junction terminal area of power semiconductor devices, resulting in high impact ionization and dynamic avalanche or damage caused by device leakage, poor safe working area, etc., the embodiment of the utility model provides a switch type power semiconductor devices.

In order to achieve the above utility model purpose, the utility model embodiment adopts the following technical solutions:

A switch-type power semiconductor device comprising a silicon layer having opposing first and second surfaces, the first surface being divided into an active region and a junction termination region, further comprising a silicon layer bonded to the second The metal layer on the surface, the active region is surrounded by the junction terminal region; The second ion-doped region corresponding to the concentration of doping ions is lower than that of the first ion-doped region, the first ion-doped region is surrounded by the second ion-doped region, and the first ion-doped region is surrounded by the second ion-doped region. The area of the ion-doped region is smaller than or equal to the area of the active region.

Preferably, the minimum distance from the edge of the active region to the edge of the silicon layer is c, the minimum distance from the edge of the first ion-doped region to the edge of the silicon layer is d, and the difference between d and c Not less than 10 μm.

Preferably, the silicon layer is any one of a silicon dioxide layer, a silicon nitride layer, and a polysilicon layer.

Preferably, the metal layer is any one of Ti+Ni+Ag layer, Al+Ti+Ni+Ag layer and Ti+Au layer.

Preferably, the silicon layer has a thickness of 50 μm˜1000 μm.

Preferably, the metal layer has a thickness of 1.4 μm˜2.7 μm.

In the switch-type power semiconductor device provided by the above-mentioned embodiments of the present invention, the ion doping area on the second surface is divided into doping areas with different ion concentration, wherein the first ion doping area is a doping area with higher ion concentration , and it is defined that the first ion-doped region is directly opposite to the active region, the second ion-doped region is directly opposite to the junction terminal region, and the area of the first ion-doped region is smaller than or equal to the area of the active region, ensuring The metal and the silicon layer form a good ohmic contact, reduce the static parameters and static functions of the device such as on-resistance, reduce the free carrier concentration and current density in the junction terminal area of the device, reduce impact ionization and dynamic avalanche breakdown, and reduce edge element The cell is damaged by latch-up due to current concentration, thereby improving the overall safe operating area of the device.

Description of drawings

Fig. 1 is a schematic diagram of the current concentration phenomenon in the terminal area of a conventional power semiconductor device;

Fig. 2 is a front view of the structure of the switching power semiconductor device provided by the embodiment of the utility model;

Fig. 3 is a schematic diagram of the current flow of the structure of the switching power semiconductor device provided by the embodiment of the utility model;

Fig. 4 is a schematic diagram of the first surface of the switching power semiconductor device provided by the embodiment of the utility model;

Fig. 5 is a schematic diagram of the second surface of the switching power semiconductor device provided by the embodiment of the utility model;

Fig. 6 is a schematic flow chart of the manufacturing method of the switching power semiconductor device provided by the embodiment of the present utility model.

detailed description

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

As shown in Figures 2, 3, 4 and 5, the embodiment of the present invention provides a switching power semiconductor device.

The switching power semiconductor device includes a silicon layer 1, the silicon layer 1 includes a first surface and a second surface opposite, the first surface is divided into an active region 11 and a junction termination region 12, the active The region 11 is surrounded by the junction termination region 12; the second surface is divided into a first ion-doped region 13 corresponding to the active region 11 and an ion body corresponding to the junction termination region 12 a second ion-doped region 14 with a concentration lower than that of the first ion-doped region 13, the first ion-doped region 13 is surrounded by the second ion-doped region 14, and the first ion-doped region The area of the impurity region 13 is smaller than or equal to the area of the active region 11 , and the second surface is further combined with a metal layer 2 .

In the embodiment of the present invention, the first surface is the front side of the chip; the second surface is the back side of the chip.

Preferably, the silicon layer 1 is any one of a silicon dioxide layer, a silicon nitride layer, and a polysilicon layer.

Preferably, the metal layer 2 is any one of Ti+Ni+Ag layer, Al+Ti+Ni+Ag layer and Ti+Au layer. Among them, Ti (titanium metal) and Al (aluminum metal) can form a good ohmic contact with the silicon material on the back of the device, reducing the on-resistance of the device; Ni metal, as a barrier layer or a transition layer, has good adhesion, It can also prevent the resistance increase caused by the interdiffusion between the upper and lower back gold layers during the encapsulation process. Metals such as Ag and Au are usually used as the outermost layer of the metal on the back of the power device due to their good electrical and thermal conductivity, and their good solderability with the packaging substrate. The metal layer 2 is combined on the second surface.

The thickness of the silicon layer 1 is 50 μm to 1000 μm, corresponding to products with a blocking voltage as low as 600 V and a blocking voltage as high as 10000 V, respectively.

The thickness of the metal layer 2 is set to be 1.4 μm˜2.7 μm.

Specifically, the thickness of Ti (titanium metal) and Al (aluminum metal) is usually 0.1 μm to 0.2 μm, and Ti can form a good ohmic contact with the silicon material on the back of the device; Ni metal is used as a barrier layer, and the thickness is usually 0.3 μm to 0.5 μm. μm, which can prevent mutual diffusion between the upper and lower back gold layers during packaging. Ag, Au and other metals ensure good welding with the packaging substrate and control the cost of materials, usually with a thickness of 1 μm to 2 μm.

Preferably, the minimum distance from the edge of the active region 11 to the edge of the silicon layer 1 is c, and the minimum distance from the edge of the first ion-doped region 13 to the edge of the silicon layer 1 is d. In other words, the distance from the edge of the silicon layer 1 to the edge 11 of the active region (the width of the junction termination region 12) is c, and the distance from the edge of the silicon layer 1 to the first ion-doped region 13 (the second The ion-doped region 14) is d.

That is to say, the active region 11 is directly opposite to the first ion-doped region 13 , but the area of the active region 11 is greater than or equal to the first ion-doped region 13 . On the one hand, it can ensure that the metal layer 2 on the second surface forms a good ohmic contact with the silicon layer 1, and reduce the on-resistance and other related static parameters and static power consumption of the device; on the other hand, the area of the first ion-doped region 13 Smaller than the active region 11, it can reduce free carriers and current density to the junction terminal region 12, reduce impact ionization and dynamic avalanche breakdown, reduce the latch-up damage of edge cells due to current concentration, and improve the overall performance of the device safe work area.

The above-mentioned volume concentration of implanted ions contained in the utility model refers to the volume concentration of implanted ions in the first ion-doped region 13 and the concentration of implanted ions in the second ion-doped region 14 in the molded product. have a bulk concentration of implanted ions.

Preferably, the first ion-doped region 13 has a bulk concentration of implanted ions in the range of 1.0E17 cm ⁻³ to 1.0E19 cm ⁻³ , and the second ion-doped region 14 has a bulk concentration of implanted ions of 1.0E15cm ^-3 ~ 1.0E16cm ^-3 . The bulk concentration of implanted ions possessed by the first ion-doped region 13 is an order of magnitude higher than that of the implanted ions possessed by the second ion-doped region 14, and the combined area of the active region 11 is greater than or equal to that of the first ion-doped region The area of 13 can effectively reduce free carriers and current density to the junction terminal region 12, reduce impact ionization and dynamic avalanche breakdown, reduce the latch-up damage of edge cells due to current concentration, and improve the safety of the device as a whole work area.

Preferably, the type of the implanted ions is N-type or P-type. The N-type ions come from at least one of phosphorus and arsenic. This type of element can achieve an activation rate of 80% to 100%, making most of the implanted ions become effective ions, improving the stability of device product parameters, and the defects generated by the ion implantation process can also be well repaired , reducing the possibility of device leakage, especially when operating at high temperature.

The P-type ions come from at least one of boron element and boron difluoride. This type of element can achieve an activation rate of 80% to 100%, making most of the implanted ions become effective ions, improving the stability of device product parameters, and the defects generated by the ion implantation process can also be well repaired , reducing the possibility of device leakage, especially when operating at high temperature.

In the above-mentioned embodiments of the present invention, the ion doping of the second surface is divided into two regions corresponding to the active region 11 and the junction terminal region 12 of the first surface with different concentrations of doping ions, wherein the first ion doping The impurity region 13 is a doped region with a higher concentration of ions, which ensures a good ohmic contact between the metal and the silicon layer, reduces static parameters and static functions such as the on-resistance of the device, and the second ion-doped region has a lower concentration of ions. The doped region reduces the emission and injection efficiency of this region, thereby reducing the free carrier concentration and current density in the device junction terminal region 12, reducing impact ionization and dynamic avalanche breakdown, and reducing the latch caused by current concentration in edge cells -up damage, thereby improving the overall safe operating area of the device.

Correspondingly, on the premise of the above-mentioned embodiments, the embodiment of the present invention also provides a manufacturing method of the above-mentioned switching power semiconductor device.

As shown in FIG. 6, in one embodiment, the manufacturing method of the switching power semiconductor device includes at least the following steps:

1) The semi-finished product with the front structure completed according to the conventional process shall be thinned;

2) performing ion implantation doping treatment on the second surface;

3) using a laser annealing process to anneal the region corresponding to the second surface and the active region, and the region after the laser annealing forms a first ion-doped region;

4) performing furnace tube annealing treatment on the region of the second surface that has not been subjected to the laser annealing treatment, so that the region that has been subjected to the furnace tube annealing treatment forms a second ion-doped region;

5) Depositing a metal layer on the second surface.

The manufacturing process of the above switching power semiconductor device will be further described in detail below.

Among them, as shown in Figure 6, in step 1), the front structure here is the first surface mentioned above, that is, the front of the chip. The semi-finished product that has completed the front structure can be produced by itself or obtained by other means. The utility model is not limited.

In step 1), the second surface of the semi-finished product is thinned, including first grinding and thinning the chip, and then using an acid solution to soak the semi-finished product in batches or spraying on a single piece, through grinding and thinning and acid solution The immersion treatment removes all the dielectric layer material on the second surface and removes the stress generated during grinding.

In one embodiment, the acid solution is an aqueous solution of at least one of sulfuric acid, nitric acid, acetic acid, and hydrofluoric acid, but is certainly not limited to the acids listed above. Anything that can remove the material of the second surface dielectric layer is feasible. The concentration of the aqueous acid solution here is not limited, and the concentration of the acid can be determined according to specific needs.

Preferably, in step 2), in the ion implantation doping process, the implanted ion type is N-type or P-type.

Wherein, the N-type ions come from at least one of phosphorus and arsenic. This type of element can achieve an activation rate of 80% to 100%, making most of the implanted ions become effective ions, improving the stability of device product parameters, and the defects generated by the ion implantation process can also be well repaired , reducing the possibility of device leakage, especially when operating at high temperature.

The P-type ions come from at least one of boron element and boron difluoride. This type of element can achieve an activation rate of 80% to 100%, making most of the implanted ions become effective ions, improving the stability of device product parameters, and the defects generated by the ion implantation process can also be well repaired , reducing the possibility of device leakage, especially when operating at high temperature.

The implantation dose of the above-mentioned ions is 1.0E13cm ^-2 ~ 1.0E14cm ^-2 , which belongs to high-concentration ion implantation, and the implantation dose here refers to the total number of ions implanted per unit area, so the implantation obtained by laser annealing or furnace tube annealing after implantation The volume concentration of ions refers to the concentration obtained by dividing the implant dose by the volume. High-concentration ion implantation, on the one hand, is conducive to forming a good ohmic contact between the back metal layer and the silicon layer, reducing the on-resistance and other related static parameters and static power consumption; The activation rate is too low.

Preferably, in step 3), the laser light intensity for laser annealing is 0.5J·cm ^-2 to 5.0J·cm ^-2 , the energy density of the laser is 1J·cm ^-2 to 10J·cm ^-2 , and the laser beam The spot size is 0.1×1.0mm ² ~1.0×10.0mm ² , and the laser annealing time is 0.1~1.0μs. Laser annealing under this condition can quickly achieve high activation of implanted ions, thereby forming a doped region with high body concentration; in addition, laser annealing has strong defect repair ability, causes little damage to silicon, and has low device leakage.

Laser annealing uses the automatic scanning mode of the laser annealing equipment to perform region-selective scanning annealing on the second surface, and the selected region is shown in FIG. 5 .

In step 4), the annealing temperature of the furnace tube is 400° C. to 500° C., the annealing time of the furnace tube is 10 min to 60 min, and the annealing treatment is performed in a nitrogen atmosphere. Conventional furnace tube annealing has a low activation rate. Therefore, laser annealing is first used to form a doped region with a higher central ion concentration, and then furnace tube annealing is used to realize a doped region with a higher ion concentration (that is, the first ion-doped region). impurity region) the distribution of the doped region with a lower concentration of ions (that is, the second ion-doped region). The doped region with lower ion concentration on the second surface corresponds to the device junction termination region on the first surface. Since the ion concentration in the low body concentration doped region is low, its emission and implantation efficiency is low, thereby reducing the device junction termination region. The free carrier concentration and current density can reduce the latch-up damage of edge cells due to current concentration, thereby improving the overall safe operating area of the device.

In step 5), the deposition process of the metal layer generally adopts conventional multi-layer metal materials, such as any one of Ti+Ni+Ag, Al+Ti+Ni+Ag, Ti+Au. Of course, it is not limited to the listed metal materials. The thickness of the deposited metal layer is set to be 1.4 μm˜2.7 μm. Specifically, the thickness of Ti (titanium metal) and Al (aluminum metal) is usually 0.1 μm to 0.2 μm, and Ti can form a good ohmic contact with the silicon material on the back of the device; Ni metal is used as a barrier layer, and the thickness is usually 0.3 μm to 0.5 μm. μm, which can prevent mutual diffusion between the upper and lower back gold layers during packaging. Ag, Au and other metals ensure good welding with the packaging substrate and control the cost of materials, usually with a thickness of 1 μm to 2 μm.

Specifically, the metal layer is grown on the second surface by using electron beam evaporation or magnetron sputtering technology, and appropriate alloy process conditions, so as to ensure that the generated metal layer can form a good alloy contact with the second surface, so as to meet the requirements of subsequent chip bonding. Combination and packaging requirements.

Compared with the prior art, the manufacturing method of the switch-type power semiconductor device provided by the above-mentioned embodiments of the utility model does not need photolithography treatment (photolithography treatment includes a series of processes such as gluing, exposure, and development), which simplifies The backside process of power semiconductor devices; in addition, the doping concentration implantation of the conventional process needs to be realized by adjusting the ion implantation dose. High implantation dose requires high beam current ion implantation equipment, while low implantation dose requires bottom beam ion implantation equipment. The utility model adopts a two-step annealing process, and only needs to use a one-time injection dose, thereby omitting the injection machine equipment, reducing equipment investment and equipment operating costs. The obtained device can effectively solve the failure problem caused by current concentration in the junction terminal area, improves the conductivity of the device, reduces the on-resistance of the device, and is suitable for popularization and application.

In order to better reflect the switch-type power semiconductor device provided by the embodiment of the present invention and the manufacturing method thereof, the following examples further illustrate it.

Example 1

A method for manufacturing a switching power semiconductor device, comprising the steps of:

1) Select qualified semi-finished products that have completed the front process;

2) Thinning the second surface of the semi-finished product, including first grinding and thinning the second surface, and then soaking in an aqueous sulfuric acid solution with a mass concentration of 98%. The soaking time is 10 minutes. This step of acid soaking treatment The function is to remove the silicon slag generated during grinding and remove the stress generated during grinding. Then take it out and clean it to remove the residual acid on the surface of the semi-finished product;

3) performing phosphorus element ion implantation on the semi-finished chip obtained in step 2), and the implantation dose is 1.0E14cm ⁻² ;

4) Use laser annealing equipment to perform area-selective scanning on the second surface, and scan the center position of the second surface. The scanned area is equivalent to and corresponds to the active area of the first surface. The specific position is shown in Figure 5. Adjust the laser The light intensity is 4.0J·cm ^-2 , the energy density of the laser is 8J·cm ^-2 , the laser beam spot is 0.8×10.0mm ² , and the laser annealing time is 1.0μs to obtain the first ion-doped region;

5) Place the semi-finished product after the laser annealing treatment in the furnace tube in a nitrogen atmosphere, and perform the furnace tube annealing treatment, set the furnace tube annealing temperature to 450°C, and the annealing time to 30 minutes to form a surrounding area surrounded by the first ion doping The second ion-doped region outside the region (as shown in Figure 5);

6) After the annealing treatment of the furnace tube, a metal layer is magnetron sputtered on the second surface by using a conventional magnetron sputtering process. The metal layer is a Ti+Au layer, and the thickness of the Ti metal layer is 0.12 μm. The thickness of the Au metal layer is 1.0 μm.

Detected by the spreading resistance method (SRP method, SpreadingResistance Profiles), the volume concentration of the doping ions in the first ion-doped region formed after the laser annealing process of the switch-type power semiconductor device produced in this embodiment is 1.0E18cm ^-3 ; The volume concentration of doping ions in the two-ion doped region is 3.0E15cm ^-3 ; by measuring the current and voltage characteristic curves of the device, it can be calculated that the saturated on-voltage (on-resistance) of the device is 2.2V (corresponding to 30A 1700VIGBT product ).

Example 2

A method for manufacturing a switching power semiconductor device, comprising the steps of:

1) Select qualified semi-finished products that have completed the front process;

2) Thinning the second surface of the semi-finished product, including first grinding and thinning the second surface, and then soaking in an aqueous solution of nitric acid with a mass concentration of 90% and hydrofluoric acid with a mass concentration of 42%, The immersion time is 12 minutes. The role of this step of acid immersion treatment is to remove the silicon slag generated during grinding and remove the stress generated during grinding. Then take it out and clean it to remove the residual acid on the surface of the semi-finished product;

3) Carry out boron ion implantation to the semi-finished chip obtained in step 2), and the implantation dose is 3.0E13cm ⁻² ;

4) Use laser annealing equipment to perform area-selective scanning on the second surface, and scan the center position of the second surface. The scanned area is equivalent to and corresponds to the active area of the first surface. The specific position is shown in Figure 5. Adjust the laser The light intensity is 5.0J·cm ^-2 , the energy density of the laser is 10J·cm ^-2 , the laser beam spot is 1.0×10.0mm ² , and the laser annealing time is 0.8μs to obtain the first ion-doped region;

5) Place the semi-finished product after the laser annealing treatment in the furnace tube in a nitrogen atmosphere, and perform the furnace tube annealing treatment, set the furnace tube annealing temperature to 500°C, and the annealing time to 60 minutes to form a surrounding area surrounded by the first ion doping The second ion-doped region outside the region (as shown in Figure 5);

6) After furnace tube annealing treatment, adopt conventional magnetron sputtering process, on the second surface magnetron sputtering layer metal layer, described metal layer is Al+Ti+Ni+Ag layer, the thickness of Al metal layer The thickness of the Ti metal layer is 0.10 μm, the thickness of the Ni metal layer is 0.4 μm, and the thickness of the Ag metal layer is 1.0 μm.

Detected by the spreading resistance method (SRP method, SpreadingResistance Profiles), the volume concentration of the doping ions in the first ion-doped region formed after the laser annealing process of the switch-type power semiconductor device produced in this embodiment is 1.0E19cm ^-3 ; The volume concentration of doping ions in the two-ion doped region is 3.0E16cm ^-3 ; by measuring the current and voltage characteristic curves of the device, it can be calculated that the saturated conduction voltage (conduction resistance) of the device is 2.0V (corresponding to 50A 1200VIGBT products ).

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modification, equivalent replacement or improvement made within the spirit and principles of the present utility model shall be included in this utility model. within the scope of protection of utility models.

Claims (6)

1. A switch-type power semiconductor device comprising a silicon layer having opposing first and second surfaces, the first surface being divided into an active region and a junction termination region, further comprising a silicon layer bonded to the The metal layer on the second surface is characterized in that: the active region is surrounded by the junction terminal region; the second surface is divided into a first ion-doped region corresponding to the active region and a first ion-doped region corresponding to the active region. The junction terminal region directly corresponds to a second ion-doped region whose concentration of doping ions is lower than that of the first ion-doped region, and the surrounding of the first ion-doped region is the second ion-doped region Around, the area of the first ion-doped region is smaller than or equal to the area of the active region. 2. The switching power semiconductor device according to claim 1, characterized in that: the minimum distance from the edge of the active region to the edge of the silicon layer is c, and the edge of the first ion-doped region to the silicon layer The minimum distance between layer edges is d, the difference between d and c is not less than 10 μm. 3. The switching power semiconductor device according to claim 1, wherein the silicon layer is any one of a silicon dioxide layer, a silicon nitride layer, and a polysilicon layer. 4. The switching power semiconductor device according to claim 1, wherein the metal layer is any one of a Ti+Ni+Ag layer, an Al+Ti+Ni+Ag layer, and a Ti+Au layer. 5 . The switching power semiconductor device according to claim 3 , wherein the silicon layer has a thickness of 50 μm˜1000 μm. 6 . The switching power semiconductor device according to claim 4 , wherein the metal layer has a thickness of 1.4 μm˜2.7 μm.