CN204810134U - DVDT detects and protection device - Google Patents

Abstract

The utility model discloses a DV/DT detection and protection device, comprising: a DV/DT detection circuit for detecting the voltage variation of DV/DT; the circuit includes several high-voltage MOS tubes, resistors, clamping diodes and parasitic Capacitor, wherein the gate terminal of the high-voltage MOS tube is connected to the input signal, the drain terminal of the high-voltage MOS tube is connected to a resistor and the source terminal is connected to a common ground; both ends of the resistor are connected to a clamping diode; the parasitic capacitance is connected to the high-voltage MOS tube Between the drain terminal and the source terminal; the DV/DT comparison circuit is connected with the DV/DT detection circuit, and is used to determine the DV/DT level to which the voltage variation belongs according to the voltage variation, and is configured to control the operation of the output drive adjustment circuit mode signal; the output drive adjustment circuit is used to adjust and output drive capability according to the control signal. The circuit of the utility model has the advantages of simple implementation, high reliability and integration, no need for additional peripheral devices, and is suitable for various applications such as bridge circuits and intelligent power modules.

Description

A DV/DT detection and protection device

technical field

The utility model relates to a DV/DT detection device, in particular to a DV/DT detection and protection device, which belongs to the technical field of intelligent power drive modules.

Background technique

With the continuous advancement of electronic power technology, high-voltage gate drive circuits and intelligent power modules (power drive modules that seal high-voltage gate drive circuits and power devices) play an important role in many fields such as motors, automation, and power systems. increasingly important role.

The high-voltage half-bridge topology is the most typical application scenario for high-voltage gate drive circuits. A high-voltage gate drive circuit, a high-side power device (MOS or IGBT), and a low-side power device together form a half-bridge drive topology. As shown in Figure 1, the gate drive circuit mainly includes a high-side drive circuit and a low-side drive circuit according to the working power supply voltage. The output HO of the high-side drive circuit controls the switch of the high-side MOSFETM1, and the output LO of the low-side drive circuit Controls the switch of low-side MOSFETM2. The bootstrap floating power supply formed by the bootstrap diode Dbs and the bootstrap capacitor Cbs is used to provide power to the high-side drive circuit. Therefore, the floating ground VS of the high-side driving circuit changes with the switching state of the power device. As shown in Figure 2, when HO changes from low to high, the LO output is low, the high-side MOSFETM1 is turned on, and the output node VS of the half-bridge drive system switches from the ground potential to the power supply voltage at the rate of DV/DT. In order to improve the efficiency of the half-bridge system and reduce the power consumption of the power device during the switching process, it is necessary to allow the power device to switch at a faster speed. However, VS changes at a rate of DV/DT, and there are two bad mechanisms: First, when VS changes at a rate of DV/DT, a displacement current (Id1) will flow through the parasitic capacitance Cds, and this current will flow in the gate drive circuit If the voltage drop exceeds the threshold of the MOSFET, it will cause false conduction of the MOSFET; the second is that when VS changes at the rate of DV/DT, the parasitic capacitance Cdb will also flow through the displacement Current (Id2), if the voltage drop generated by the current on the parasitic resistor Rb is greater than the turn-on voltage of the parasitic transistor NPN, it will also cause the NPN to be turned on, and then trigger a large current. If the change rate DV/DT of VS exceeds the limited range, the above two mechanisms will cause false conduction of the low-side MOSFETM2, which will cause the high-side and low-side MOSFETs to pass through or cause the latch of M2, and then cause permanent damage to M2. How to make power devices work at a safer DV/DT switching rate, the prior art mainly adjusts the output driving capability of the gate drive circuit through peripheral discrete devices, and then adjusts DV/DT.

However, this method increases the cost of use, and is not conducive to the layout of the printed circuit board (PCB), which is easy to increase various parasitic interference factors; in addition, this method is not suitable for fully integrated intelligent power modules, and cannot be effectively and conveniently Adjust DV/DT to protect power devices.

Contents of the invention

The technical problem to be solved by the utility model is to overcome the deficiencies of the prior art, provide a DV/DT detection and protection device, and solve the problem that the prior art uses peripheral discrete devices to adjust the output drive capability of the grid drive circuit, which is not suitable for The fully integrated intelligent power module cannot effectively and conveniently adjust the DV/DT problem.

The utility model specifically adopts the following technical solutions to solve the above-mentioned technical problems:

A DV/DT detection and protection device, comprising:

The DV/DT detection circuit is used to detect the voltage variation of DV/DT; the circuit includes several high-voltage MOS tubes, resistors, clamping diodes and parasitic capacitors, where the gate terminal of the high-voltage MOS tube is connected to the input signal, and the high-voltage MOS tube The drain terminal of the tube is connected to a resistor and the source terminal is connected to a common ground; both ends of the resistor are connected to a clamp diode; the parasitic capacitance is connected between the drain terminal and the source terminal of the high-voltage MOS tube;

The DV/DT comparison circuit is connected with the DV/DT detection circuit, and is used for determining the DV/DT level to which the voltage variation belongs according to the voltage variation, and configuring a signal for controlling the working mode of the output drive adjustment circuit according to the DV/DT level ;

The output drive adjustment circuit is connected with the DV/DT comparison circuit, and is used for configuring the working mode and output drive capability according to the control signal.

Further, as a preferred technical solution of the present invention: the DV/DT comparison circuit includes several comparison levels and window comparators connected thereto.

Further, as a preferred technical solution of the present utility model: the output drive adjustment circuit includes a first output drive tube for charging and a second output drive tube for discharge, and is connected to the two output drive tubes A drive adjustment unit between the tubes; the drive adjustment unit includes several groups of switch circuits, and the number of the switch circuits corresponds to the number of control signals.

Furthermore, as a preferred technical solution of the present invention: the several groups of switch circuits are connected in series, and each switch circuit is composed of a resistor and a switch tube connected in parallel with the resistor.

Further, as a preferred technical solution of the present invention: the several groups of switch circuits are connected in parallel, and each switch circuit is composed of a logic gate circuit and a third output drive tube controlled by the logic gate circuit.

Further, as a preferred technical solution of the present utility model: the DV/DT detection circuit detection includes first and second high-voltage MOS transistors, first and second resistors, first and second clamping diodes, first and the second parasitic capacitance, wherein the gate terminal of the first high-voltage MOS transistor is connected to the first input signal, the drain terminal of the first high-voltage MOS transistor is connected to the first resistor and the source terminal is connected to the common ground; the two ends of the first resistor Connect the first clamping diode; the first parasitic capacitance is connected between the drain terminal and the source terminal of the first high-voltage MOS transistor; the gate terminal of the second high-voltage MOS transistor is connected to the second input signal, and the second high-voltage The drain terminal of the MOS transistor is connected to the second resistor and the source terminal is connected to the common ground; the two ends of the second resistor are connected to the second clamping diode; the second parasitic capacitance is connected to the drain terminal and the source terminal of the second high-voltage MOS transistor between.

The utility model adopts the above-mentioned technical scheme, and can produce the following technical effects:

(1) The DV/DT detection and protection device provided by the utility model automatically detects the DV/DT in the switching process of the power device, and when the DV/DT exceeds the set threshold, the drive circuit will automatically adjust the output drive capability, Make the power device work in a reasonable and safe DV/DT range; the circuit implementation is simple, the reliability and integration are high, no additional peripheral devices are required, and it is suitable for various applications such as bridge circuits and intelligent power modules.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention , for those skilled in the art, other drawings can also be obtained according to these drawings on the premise of not paying creative work.

FIG. 1 is a half-bridge driving topology in the prior art.

FIG. 2 shows the MOSFET failure mechanism caused by DV/DT in the prior art.

Fig. 3 is a schematic structural diagram of the DV/DT detection and protection device of the present invention.

Fig. 4 is a structural schematic diagram of the DV/DT comparison circuit in the utility model.

Fig. 5 (a) is the normal level conversion process working waveform of DV/DT comparison circuit in the utility model; Fig. 5 (b) is the DV/DT smaller process working waveform of DV/DT comparison circuit in the utility model; Fig. 5(c) is the working waveform of the larger DV/DT process of the DV/DT comparison circuit in the utility model.

Fig. 6 is a schematic diagram of the determination of the DV/DT comparison circuit in the present invention.

FIG. 7 is a schematic diagram of Embodiment 1 of the output drive adjustment circuit in the present invention.

FIG. 8 is a schematic diagram of Embodiment 2 of the output drive adjustment circuit in the present invention.

Detailed ways

The embodiment of the utility model will be described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

The device for DV/DT detection and protection provided by the utility model includes a DV/DT detection circuit, a DV/DT comparison circuit and an output drive adjustment circuit; wherein the DV/DT detection circuit includes several high-voltage MOS tubes, resistors, and clamping diodes and parasitic capacitance. In this embodiment, as shown in Figure 3, the DV/DT detection circuit includes first and second high-voltage MOS transistors, first and second resistors, first and second clamping diodes, and first and second parasitic Capacitor; the first high-voltage MOS transistor MA1, its gate terminal is connected to the input signal IN1, the drain terminal is connected to the first resistor R1, and the other end of the first resistor R1 is connected to the floating power supply VB; the source terminal of the first high-voltage MOS transistor MA1 is connected to the common Ground VSS, both ends of the first resistor R1 are connected to the first clamping diode D1; for the second high-voltage MOS transistor MA2, its gate terminal is connected to the input signal IN2, its drain terminal is connected to the second resistor R2, and the other end of the second resistor R2 is connected to The floating power supply VB; the source terminal of the second high-voltage MOS transistor MA2 is connected to the common ground VSS, and the two ends of the second resistor R2 are connected to the second clamping diode D2. And the first parasitic capacitance Cpar1 is connected between the drain terminal and the source terminal of the first high-voltage MOS transistor MA1, and the second parasitic capacitance Cpar2 is connected between the drain terminal and the source terminal of the second high-voltage MOS transistor MA2; the detection circuit also realizes A high-voltage level conversion function is provided to convert the inputs IN1 and IN2 of the low-voltage domain into signals of the high-voltage domain. The detection circuit detects the voltage change of the displacement current of the parasitic capacitance caused by DV/DT on the resistance to obtain the voltage change.

The voltage variation detected by the drain terminals of the first high-voltage MOS transistor MA1 and the second high-voltage MOS transistor MA2 is sent to the DV/DT comparison circuit for comparison with the internal reference window, and at least one bit of control signal is output to configure the work of the output drive adjustment circuit mode to adjust the output drive capability. The output drive adjustment circuit adjusts and outputs drive capabilities in different working modes according to the control signal to ensure that the power device works within the safe DV/DT range.

In this embodiment, a specific implementation example of the DV/DT comparison circuit in the device is also given, as shown in Figure 4, which includes a comparison level Vref, window comparators Comp1 and Comp2, and the inversion of the two comparators The input terminals are connected to the comparison level Vref, the non-inverting input terminals of the two window comparators are respectively connected to the output nodes A and B of the high-voltage level conversion circuit, and the output CA and CB of the two window comparators are NOR gates The two input terminals of Nor1 are connected, the output terminal of Nor1 is connected to the S terminal of RS-Latch, and the R terminal of RS-Latch is connected to the reset signal UVLO. Its working process is as follows. When the high-side MOSFET is turned on, the output node VS of the half-bridge circuit will change at the rate of DV/DT. Because the high-side drive circuit samples the bootstrap capacitor Cbs to provide a floating power supply, when VS changes at a rate of DV/DT, the power supply VB of the high-side drive circuit also changes at a rate of DV/DT. At this time, due to the change of DV/DT of VB, displacement currents will be generated on the first parasitic capacitance Cpar1 and the second parasitic capacitance Cpar2 of the first high-voltage MOS transistor M1 and the second high-voltage MOS transistor M2 in the high-voltage level conversion circuit, respectively. . This current will flow through the first resistor R1 and the second resistor R2 in the high-voltage level conversion circuit, and a voltage drop equal to The first resistor R1 and the second resistor R2, the first high voltage MOS transistor MA1 and the second high voltage MOS transistor MA2 are all matched as much as possible. Therefore, if there is a voltage change of DV/DT on the floating power supply VB, the voltage drop generated on the two resistors should be basically the same. The generated voltage drop is compared with the comparison level of the window comparator. If the voltage changes on the two resistors meet the conditions at the same time, the NOR gate outputs a high level and sets the RS-Latch to output a high-level active Gate_control signal. As shown in Figure 5(a), when the high-voltage level shifter normally converts the signal, for example, the second high-voltage MOS transistor M2 receives the signal, the first high-voltage MOS transistor M1 is turned off, and only the second resistor R2 has a voltage change at this time , there is no first resistor R1, so the DV/DT comparator circuit outputs a low-level Gate_control. If the DV/DT of the power device switch on VB is relatively small, as shown in Figure 5(b), the generated displacement current is relatively small, and the voltage change on the first resistor R1 and the second resistor R2 cannot reach the comparison of the window comparator level Vref, the DV/DT comparison circuit outputs a low level Gate_control. As shown in Figure 5(c), when the DV/DT of the power device switch is relatively large on VB, the voltage change on the first resistor R1 and the second resistor R2 reaches the comparison level Vref of the window comparator, at this time DV/DT The DT comparison circuit outputs a high-level Gate_control.

The DV/DT comparison circuit can also configure the control signal output when the voltage variation across the first resistor R1 and the second resistor R2 exceeds the internal window comparison level of the DV/DT comparison circuit at the same time, and the output drive adjustment circuit responds to this event, And reduce the output drive capability, and reduce DV/DT to a safe range.

The implementation examples of the DV/DT comparison circuit shown in Fig. 4 and Fig. 5 both include only one window level, and the DV/DT level to be judged is relatively simple. Figure 6 is a schematic diagram of the determination of the DV/DT comparison circuit including multiple window comparison levels. The number of window comparison levels can be set according to the DV/DT level accuracy, so that the DV/DT can be set according to the degree of voltage change on the resistor. The DT level is divided into multiple ranges and outputs a multi-bit Gate_control<n:1> signal. As shown in Figure 6, the determination diagram of the degree of voltage change on the resistance, that is, the DV/DT level is set to multiple ranges from vth1 to vthn, and when the voltage change on the resistance falls into the corresponding range, a DV can be generated /DT level, when the DV/DT level is obtained, the corresponding Gate_control signal will be generated accordingly, thus obtaining Gate_control<1> to Gate_control<n> signal outputs. In Fig. 6, the DV/DT security level is set, and when the DV/DT level exceeds the DV/DT security level, protection is carried out by adjusting the output drive capability.

For the output drive adjustment circuit in the device, the output drive adjustment circuit includes a first output drive tube for charging, a second output drive tube for discharge, and a driver connected between the two output drive tubes. An adjustment unit; the drive adjustment unit includes several groups of switch circuits, and the number of the switch circuits corresponds to the number of control signals. The utility model provides different embodiments, as shown in FIG. 7 and FIG. 8 , which are specific circuit structures of the output drive adjustment circuit.

The output drive adjustment circuit in Figure 7 includes a first output drive transistor MP1 for charging, a second output drive transistor MN1 for discharge, and a drive adjustment unit. As shown in Figure 7, the drive adjustment unit consists of two groups of series Composed of switch circuits, each switch circuit is composed of a resistor and a switch tube connected in parallel with the resistor; in Figure 7, a switch circuit is composed of a switch tube MP2 and a resistor Rd1 connected in parallel with it, and the switch circuit receives the signal from Gate_control<1> . Another switch circuit is composed of a switch tube MP3 and a resistor Rd2 connected in parallel with it, and the switch circuit receives a signal from Gate_control<2>. For the first switching circuit, the first output driving transistor MP1, the switching transistor MP2 and the resistor Rd are used for the charging process of the circuit, and the second output driving transistor MN1 is used for the discharging process of the circuit. For the charging process of the circuit, whether the resistor Rd is short-circuited or not is controlled by the switch tube MP2, and the output drive capability is adjusted through the resistor Rd. When the control signal Gate_control<1> output by the comparison circuit is low, the switch tube MP2 conducts When the resistor Rd is turned on, the resistor Rd is short-circuited. When the Gate_control<1> output by the comparison circuit is at a high level, the resistor Rd is connected in series with the first output drive transistor MP1, and the driving capability is reduced. For the second switch circuit, its principle is the same as above.

The output drive adjustment circuit in Figure 8 includes the first output drive transistor MP1 for charging, the second output drive transistor MN1 for discharge, and the drive adjustment unit. As shown in Figure 8, the drive adjustment unit consists of two groups connected in parallel In Figure 8, the first switch circuit is composed of a logic gate circuit NOR1 and an output drive tube MP2 controlled by the logic gate circuit NOR1, and the switch circuit receives a signal from Gate_control<1>. Another switch circuit is composed of a logic gate circuit NOR2 and an output driving transistor MP3 controlled by the logic gate circuit NOR2, and the switch circuit receives a signal from Gate_control<2>. For the first switching circuit, the first output driving transistor MP1, the output driving transistor MP2 and the logic gate circuit NOR1 are used to adjust the driving force of the circuit. As shown in the figure, the control signal Gate_control<1> output by the DV/DT comparison circuit is connected to the logic gate circuit NOR1; the output terminal of the logic gate circuit NOR1 is connected to the gate of the output driving tube MP2; as shown in the figure, the DV/DT When the control signal Gate_control<1> output by the comparison circuit is at low level, the output driving transistor MP2 and the first output driving transistor MP1 are connected in parallel. When the control signal Gate_control<1> output by the DV/DT comparison circuit is at high level, only the first The output driving tube MP1 works, and the driving ability is reduced. For the second switch circuit, its principle is the same as above.

Moreover, the output drive adjustment circuit can also adjust the output drive capability through the power supply voltage, or only adjust the output sinking current capability, but can also make related adjustments to the output pull-down current capability.

When the DV/DT level value of the voltage variation exceeds the DV/DT safety level, it is preferable to gradually reduce the output driving capability to reduce DV/DT, so that the working mode of the output driving adjustment circuit is driven by a stronger output Capability changes to a weaker output drive capability. The reduction of the output drive capability can be achieved by increasing the impedance of the output drive tube or reducing the power supply voltage.

Professionals should further realize that the circuits of each example described in conjunction with the embodiments disclosed herein can be realized by electronic hardware modules, and the composition and connection of each example have been generally described in terms of functions in the above description relation. Specifically, both the calculation and control parts of the electronic hardware module can be implemented through logic hardware, which can be a logic integrated circuit manufactured using existing integrated circuit technology, which is not limited in this embodiment.

Moreover, electronic hardware modules are used in the utility model, and the technology known in the prior art is used for detection, transmission, comparison, and output. There is no improvement on the electronic hardware module itself, and there is no specific method flow. The relevant modules involved in the utility model and the functions realized thereof can be realized by carrying conventional computer software programs or related protocols in the prior art on the improved hardware and the devices formed thereof, and are not a modification of the prior art. Improvements to computer software programs or related protocols. The innovation of the present invention lies in the improvement of the hardware modules in the prior art and their connection and combination relationship, rather than the improvement of the software or protocols carried by the hardware modules to realize related functions.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present utility model in detail. Within the protection scope of the utility model, any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the utility model shall be included in the protection scope of the utility model.

Claims (6)

1. A DV/DT detection and protection device, characterized in that, comprising: The DV/DT detection circuit is used to detect the voltage variation of DV/DT; the circuit includes several high-voltage MOS tubes, resistors, clamping diodes and parasitic capacitors, where the gate terminal of the high-voltage MOS tube is connected to the input signal, and the high-voltage MOS tube The drain terminal of the tube is connected to a resistor and the source terminal is connected to a common ground; both ends of the resistor are connected to a clamp diode; the parasitic capacitance is connected between the drain terminal and the source terminal of the high-voltage MOS tube; The DV/DT comparison circuit is connected with the DV/DT detection circuit, and is used for determining the DV/DT level to which the voltage variation belongs according to the voltage variation, and configuring a signal for controlling the working mode of the output drive adjustment circuit according to the DV/DT level ; The output drive adjustment circuit is connected with the DV/DT comparison circuit, and is used for configuring the working mode and output drive capability according to the control signal. 2. The DV/DT detection and protection device according to claim 1, characterized in that: the DV/DT comparison circuit includes several comparison levels and window comparators connected thereto. 3. The DV/DT detection and protection device according to claim 1, characterized in that: the output drive adjustment circuit includes a first output drive tube for charging and a second output drive tube for discharge, and is connected to A drive adjustment unit between the two output drive tubes; the drive adjustment unit includes several groups of switch circuits, and the number of the switch circuits corresponds to the number of control signals. 4 . The DV/DT detection and protection device according to claim 3 , wherein the plurality of switch circuits are connected in series, and each switch circuit is composed of a resistor and a switch tube connected in parallel with the resistor. 5. The DV/DT detection and protection device according to claim 3, characterized in that: said several groups of switch circuits are connected in parallel, and each switch circuit is driven by a logic gate circuit and a third output controlled by the logic gate circuit tube composition. 6. The DV/DT detection and protection device according to claim 1, characterized in that: said DV/DT detection circuit detection includes first and second high-voltage MOS transistors, first and second resistors, first and second Clamping diodes, first and second parasitic capacitances, wherein the gate terminal of the first high-voltage MOS transistor is connected to the first input signal, the drain terminal of the first high-voltage MOS transistor is connected to the first resistor and the source terminal is connected to the common ground; Both ends of the first resistor are connected to the first clamping diode; the first parasitic capacitance is connected between the drain terminal and the source terminal of the first high-voltage MOS transistor; the gate terminal of the second high-voltage MOS transistor is connected to the second input signal, the drain terminal of the second high-voltage MOS transistor is connected to the second resistor and the source terminal is connected to the common ground; both ends of the second resistor are connected to the second clamping diode; the second parasitic capacitance is connected to the second high-voltage MOS transistor between the sink and source terminals.