CN1929117B - Integrated circuits comprising silicon wafers with annealed glass paste - Google Patents

Abstract

An integrated circuit (IC) package includes an IC die and an annealed glass paste (AGP) layer disposed adjacent the IC die. The molding material encapsulates the AGP layer and at least a portion of the IC die. The AGP layer is disposed on at least one side of the IC wafer. The AGP layer is disposed on a plurality of separate regions on at least one side of the IC wafer. A layer of conductive material is disposed on a portion of the AGP layer.

Description

Integrated circuits comprising silicon wafers with annealed glass paste

technical field

The present invention relates to integrated circuits, and more particularly, to integrated circuits with annealed glass paste disposed on silicon wafers.

Background technique

Accurate frequency references are required in many types of electronic equipment, such as cellular telephones and other handheld devices. Crystal oscillators are often used to provide precise frequency references in these electronic devices. However, crystal oscillators have several inherent disadvantages, including bulkiness, fragility, and high cost. In addition, the size and cost of crystal oscillators are related to the resonant frequency, such that as frequency increases, size decreases while cost and fragility can increase rapidly. As the size of electronic devices continues to decrease, the use of crystal oscillators is becoming more and more problematic due to their size, fragility and cost constraints.

Semiconductor oscillators are a poor alternative to crystal oscillators and are generally unsuitable for accurate frequency references because their oscillation frequency varies widely, especially with temperature .

Contents of the invention

According to one aspect of the present invention, there is provided an integrated circuit package comprising: an integrated circuit; a glass layer; an epoxy layer adhering the glass layer to the integrated circuit; and enclosing the An encapsulating material for the integrated circuit and at least a portion of the glass layer. wherein the integrated circuit further comprises: a temperature sensor that senses the temperature of the integrated circuit; a memory module that stores oscillator calibrations and selects one of the oscillator calibrations as a function of the sensed temperature; and oscillating and an oscillator module that generates a reference signal whose frequency is based on one of the selected oscillator calibrations. And, wherein the glass layer includes a cavity defining an air gap, and the cavity is adjacent to the portion of the integrated circuit that includes the oscillator module.

circuit, and encapsulation material enclosing at least a portion of said integrated circuit and having low dielectric loss. wherein the integrated circuit further comprises: a temperature sensor that senses a temperature of the integrated circuit; a memory module that stores data related to oscillator calibrations and selects one of the oscillator calibrations as the sensed temperature a function; and an oscillator module that generates a reference signal whose frequency is based on the selected one of the oscillator calibrations.

According to yet another aspect of the present invention, there is provided a further integrated circuit package comprising: an integrated circuit including an oscillator module that generates a reference signal whose frequency is based on one of a plurality of oscillator calibration settings and an encapsulating material enclosing at least a portion of said integrated circuit and having low dielectric loss.

Description of drawings

FIG. 1 is a block diagram illustrating one aspect of a crystal oscillator emulator;

Figure 2 is a table showing the relationship between temperature and correction factors;

Figure 3 is a graph showing the relationship between temperature and correction factors;

4 is a block diagram illustrating an aspect of a crystal oscillator emulator;

Figure 5 is a two-dimensional view of one aspect of a crystal oscillator emulator connected to an external impedance;

Figure 6 is a detailed block diagram of one aspect of a crystal oscillator emulator connected to an external impedance;

7A and 7B are graphs showing the relationship between external impedance values and digital values;

8 is a block diagram of an aspect of an oscillator component for generating an output having a periodic waveform;

Figure 9 is a block diagram of an aspect of a spread spectrum generator;

Figure 10 is a flowchart for simulating the operation of a crystal oscillator;

Figure 11 is a block diagram of an aspect of a low power oscillator;

Figure 12 is a block diagram of another aspect of a low power oscillator;

13 is a functional block diagram of an integrated circuit including one or more circuits and a crystal oscillator emulator for generating a clock signal for the one or more circuits;

14 is a functional block diagram of an integrated circuit including a processor and a crystal oscillator emulator for generating a clock signal for the processor;

15 is a functional block diagram of an integrated circuit including a processor and a crystal oscillator emulator for generating a clock signal for the processor and setting the clock rate using external components;

16 is a functional block diagram of an integrated circuit including one or more circuits, a crystal oscillator emulator, and a clock divider for generating a clock signal at one or more other clock frequencies;

17 is a functional block diagram of an integrated circuit including a processor, one or more circuits, a crystal oscillator emulator, and a clock divider for generating clock signals at other clock frequencies;

18 is a functional block diagram of an integrated circuit including a processor, a graphics processor, one or more circuits, memory, and a crystal oscillator emulator to generate a clock signal;

19 is a functional block diagram of an integrated circuit including a processor and the low power oscillator of FIG. 11;

20 is a functional block diagram illustrating an integrated circuit packaged in a prior art packaging material;

21 is a functional block diagram showing an integrated circuit with a temperature-compensated on-chip semiconductor oscillator packaged in a packaging material with low dielectric loss according to the present invention;

FIG. 22 illustrates an exemplary implementation of the integrated circuit package of FIG. 21 in more detail;

23 is a side cross-sectional view of another integrated circuit package including an on-chip semiconductor oscillator according to the present invention;

24 is a side cross-sectional view of another integrated circuit package including an on-chip semiconductor oscillator according to the present invention;

Figure 25 is a plan cross-sectional view showing the integrated circuit package of Figure 24 in greater detail;

26 is a functional block diagram illustrating tuning of capacitors for an on-chip semiconductor oscillator based on temperature compensation;

27 is a functional block diagram of a fractional phase-locked loop (PLL) including a temperature compensation input;

Figure 28 is a functional block diagram of a Delta-Sigma fractional phase-locked loop including a temperature compensation input;

Figure 29 is a flow chart illustrating the steps for measuring sample calibration points and using a linear curve fitting algorithm to generate calibration data between the sample calibration points;

Figure 30 is a flow chart illustrating the steps for measuring sample calibration points and using a higher order curve fitting algorithm to generate calibration data between the sample calibration points;

Figure 31 A is a functional block diagram of a hard disk drive;

Figure 31B is a functional block diagram of a digital versatile disc (DVD);

Figure 31C is a functional block diagram of a high-definition television;

Figure 31D is a functional block diagram of a vehicle control system;

Figure 31E is a functional block diagram of a cellular telephone;

Figure 31F is a functional block diagram of a set-top box;

Figure 31G is a functional block diagram of a media player;

32A is a side cross-sectional view of another integrated circuit package including an annealed glass paste and/or epoxy layer formed on at least a portion of a silicon wafer;

32B is a side view of another integrated circuit package including a layer of annealed glass paste and/or epoxy formed on at least a portion of a silicon wafer and a layer of conductive material formed on at least a portion of the annealed glass paste and/or epoxy layer Sectional view;

32C is a side cross-sectional view of another integrated circuit package including spaced apart layers of annealed glass paste formed on selected portions of a silicon wafer;

32D is a side cross-sectional view of another integrated circuit package including spaced apart layers of annealed glass paste and/or epoxy and conductive material formed on selected portions of a silicon wafer;

33A is a side cross-sectional view of another integrated circuit package including annealed glass paste and/or epoxy layers and layers of conductive material adjacent to circuitry of a silicon wafer;

33B is a side cross-sectional view of another integrated circuit package including an annealed glass paste and/or epoxy layer and a layer of conductive material adjacent to an oscillator of a silicon wafer;

33C is a side cross-sectional view of another integrated circuit package including annealed glass paste and/or epoxy layer and conductive material layer adjacent to an inductor of a silicon wafer;

33D is a side cross-sectional view of another integrated circuit package including a layer of annealed glass paste and/or epoxy and conductive material adjacent to an inductor in an oscillator circuit of a silicon wafer;

34A-34D are side cross-sectional views of another integrated circuit package including a glass or silicon layer creating an air gap and annealed glass paste and/or epoxy portions;

35A-35B are side cross-sectional views of another integrated circuit package including a C-shaped layer of glass or silicon creating an air gap;

36A-36C are side cross-sectional views of a wafer comprising a plurality of integrated circuit packages including glass or silicon layers creating air gaps and annealed glass paste and/or epoxy portions;

37A-37B are side cross-sectional views of integrated circuit packages that include annealed glass paste and/or epoxy portions that have been coated with conductive material; and

FIG. 38 illustrates exemplary steps of a method for manufacturing the integrated circuit package of FIGS. 32A-32D .

Like numbers in the various drawings indicate like elements.

Detailed ways

FIG. 1 illustrates one aspect of a crystal oscillator emulator 10 for generating an output signal 12 with a precise frequency. The crystal oscillator emulator 10 can be built on a single semiconductor die using any process, including a complementary metal oxide semiconductor (CMOS) process.

Crystal oscillator emulator 10 may include a semiconductor oscillator 14 for generating output signal 12 . Any type of semiconductor oscillator can be used, including LC oscillators, RC oscillators, and ring oscillators. The semiconductor oscillator 14 includes a control input 16 for varying the frequency of the output signal. The control input 16 may be any electrical input affecting a controlled change in the frequency of the output signal, such as the supply voltage of the ring oscillator and the voltage input to the varactor diode of the LC oscillator.

The non-volatile memory 18 includes calibration information 20 used to control the output signal frequency as a function of temperature. Any type of non-volatile memory can be used, including content addressable memory (CAM). The calibration information 20 may include correction factors to be provided to the control input 16 of the semiconductor oscillator 14 to control the output signal frequency. The calibration information 20 can be a function of the temperature change from the calibration temperature to the operating temperature, or it can be a function of the absolute temperature.

Temperature sensor 22 may sense the temperature of the semiconductor die. Preferably, the temperature sensor is located near the semiconductor oscillator 14 on the semiconductor die. Any type of temperature sensor 22 may be used, including thermistors and infrared detectors. The temperature sensor 22 may be configured to measure a change in temperature from a baseline temperature or a current temperature.

FIG. 2 shows a storage technique 30 for storing calibration information 20 in non-volatile memory 18 . The storage technology 30 can be any form of database including CAMs, indexing schemes, lookup tables and hash tables.

FIG. 3 shows a series of exemplary graphs 32 of correction factor values versus temperature for maintaining a constant output signal frequency of crystal oscillator emulator 10 . The data used to construct the curves can be obtained by any means including device level testing and batch mode testing.

Exemplary device level testing may include testing each device to determine a correction factor to be applied to the semiconductor oscillator to maintain the output frequency constant over temperature. In one approach, the baseline value of the semiconductor oscillator control input is determined for a predetermined frequency and at a predetermined temperature (eg, minimum operating temperature) of a semiconductor die of the device. Baseline values can be measured directly or interpolated from measurements of another device characteristic. Baseline values can also be measured for each potential output frequency. Also, the baseline value for each potential output frequency may be extrapolated from the baseline value for the predetermined frequency, eg by using known circuit relationships. The baseline value for each potential output frequency can be stored as an absolute value or a ratio, frequency factor to calculate multiple baseline values from a single baseline value.

Subsequently, the temperature of the semiconductor die is raised in discrete steps from about the lowest operating temperature to about the highest operating temperature. The number of discrete steps is preferably limited to about 6 temperature levels to reduce test cost, but any number of discrete steps may be used. Preferably, an on-chip heater is used to heat the semiconductor die, but any means of changing the temperature of the semiconductor die may be used. At each discrete step, the semiconductor die temperature and a correction factor used to maintain the output at a constant frequency can be measured.

The correction factor is preferably a ratio which is applied to the baseline value to obtain the adjusted value of the control input. Correction factors can vary from any baseline value (eg, 1). Preferably, a correction factor is calculated for each temperature step and applied to the semiconductor oscillator to maintain the output signal at any one of a number of predetermined frequencies. For example, if a correction factor of 1.218 is determined to correspond to a temperature change of 45°C, the control input of the semiconductor oscillator may be adjusted as a function of the correction factor, eg by varying the control input in proportion to the correction factor. In another alternative, a correction factor may be applied to a baseline value corresponding to the desired output frequency to generate a calibration value for which the control input is adjusted. In another alternative, a correction factor may be measured corresponding to each of several output frequencies at each temperature step.

Batch mode testing of crystal oscillator emulator 10 to obtain calibration information 20 can advantageously reduce costs by reducing the number of measurements made on a batch of semiconductor die. In batch mode testing, test results on a subset of crystal oscillator emulators 10 from the same batch of semiconductor die can be used for all devices in the batch. The subset tested in the crystal oscillator emulator can range from one to any proportion of the total number of devices. For example, a single crystal oscillator emulator 10 may be tested and the resulting batch calibration information stored in each device in the batch. In addition, each crystal oscillator emulator 10 can be tested against a subset of the calibration information, such as output frequency at baseline temperature. A subset of device-specific calibration information may be used to modify batches of calibration information stored in each device.

FIG. 4 shows another aspect of the crystal oscillator emulator 40 . Crystal oscillator emulator 40, corresponding elements numbered in the range 40-52, are functionally similar to crystal oscillator emulator 10, but crystal oscillator emulator 40 may also include one or more heaters 54, controller 56 and Selecting input 58, these elements exist individually or in combination.

A heater 54 may be located on the semiconductor die adjacent to the semiconductor oscillator 44 to provide a localized heating source. Any type of heater 54 can be used, including transistor heaters and resistive heaters. Heater 54 may operate in response to input from temperature sensor 52 to control the temperature of the semiconductor die. Heater 54 may increase the temperature of the semiconductor die to a level corresponding to one of the temperature levels for which the correction factor has been determined. Additionally, crystal oscillator emulator 40 may be housed in a package with high thermal resistance.

In one instance, heater 54 may increase the temperature of the semiconductor die to a maximum operating temperature. Here, only the correction factor corresponding to the maximum operating temperature has to be determined during device or batch level testing, thereby reducing costs.

Heater 54 may also be controlled to increase the temperature of the semiconductor die to one of several predetermined temperature levels for which correction factors have been determined. The second temperature sensor may sense an external temperature, such as ambient temperature or component temperature. Heater 54 may then increase the temperature of the semiconductor die to a temperature closest to the predetermined temperature level while continuously varying the control input during the temperature jump using extrapolated values calculated from the correction factors.

The controller 56 may add additional functionality, such as by controlling the heater 54 in response to a plurality of temperature sensors or manipulating the calibration information 50 to derive the value of the control input corresponding to the intermediate temperature. Controller 56 may be any type of entity, including processors, logic circuits, and software modules.

The select input 58 may be used to select a particular output frequency from a range of output frequencies. The output frequency can be selected as a function of the impedance of external components connected to the selected input. External components may be used directly as part of the semiconductor oscillator to select the output frequency, or may be used indirectly to select the output frequency, for example a selection of impedance values within a predetermined range may correspond to a predetermined output frequency. The external component can be any component, but it is preferably a passive component such as a resistor or capacitor.

FIG. 5 shows an aspect of a crystal oscillator emulator 100 having, for example, two select pins 102 and 104 for connection to two external impedances 106 and 108 . One or more pins may be used to interface to external components. Crystal oscillator emulator 100 probes or obtains information from external components connected to select pins 102 and 104 . The retrieved information may have three or more predetermined level ranges corresponding to the selected emulator characteristic level. For example, a single pin connected to an external resistor can be used to select any of 16 output frequency levels. The resistance of the external resistor is preferably selected as one of 16 predetermined standard values. Each of the 16 resistor values corresponds to one of the 16 output frequency levels. Additionally, low precision passive components are preferably used as external components to reduce cost and inventory. Each external component may have a plurality (N) of predetermined nominal values, where each predetermined nominal value corresponds to a selection of a predetermined characteristic level. If one pin is used, N different feature levels can be selected. If two pins are used, N*N different feature levels can be selected, and so on. Examples of types of device characteristics that may be selected include output frequency, frequency tolerance, and baseline correction factor. For example, crystal oscillator emulator 100 may have a select pin 102 connected to an external resistor, which may have a nominal value selected from a group of 16 predetermined values. Each of the 16 predetermined values has a range of measured values corresponding to one of 16 predetermined output frequency levels that may range from 1 MHz to 100 MHz.

External impedances 106 and 108 are preferably resistors, capacitors, or a combination of resistors and capacitors, but may also be any component that behaves primarily inductively, resistively, capacitively, or a combination thereof. External impedances 106 and 108 may be connected to pins 102 and 104 directly or indirectly from any energy source such as Vdd and ground, or any suitable reference. For example, external impedance 106 may be connected to Vdd through a resistor/transistor network and to select pin 102 through a capacitor network.

The crystal oscillator emulator 100 may determine a predetermined selection value corresponding to the measured value of the impedance connected to the selection pin. Preferably, the impedance is chosen to have a standard value (eg nominal resistance value) corresponding to resistors with a tolerance of 10% (eg 470, 560, 680...) to reduce component and inventory costs. In order to take into account measurement tolerances and tolerances of external impedances, the range of impedance values may correspond to a single selected value. The selection value is preferably a digital value, but may also be an analog value. For example, measured resistance values from 2400 ohms to 3000 ohms may be associated with a numerical value corresponding to two. Whereas the measured resistance values from 3001 ohms to 4700 ohms can be associated with a numerical value corresponding to 3. The measured resistance includes variations due to external impedances and tolerances of the internal measurement circuitry. The impedance measured at each select pin is used to determine the corresponding digital value. The range of digital values may include 3 or more digital values, and a preferred range is 10 to 16 digital values per select pin. The digital values corresponding to each select pin can be used in combination to describe the memory address. For example, a device with three select pins may describe 1000 memory addresses or lookup table values, where each select pin is used to interface to an impedance value that is mapped to one of 10 digital values. The contents of the memory location corresponding to the memory address are used to set the value of an output or internal characteristic of the device. Another exemplary device may include two select pins, where each select pin is configured to interface to an external impedance mapped to a digital value within a range of 10 values. Combined, the digital values may describe 1000 memory addresses or lookup table values, where each memory address or lookup table value may contain data for setting characteristics of the crystal oscillator emulator 100 .

FIG. 6 shows a block diagram of one aspect of crystal oscillator emulator 120 . Crystal oscillator emulator 120 includes a select pin 122 for interfacing to an external impedance 124 that is used to select the configuration of crystal oscillator emulator 120 . External impedance 124 is similar to external impedances 106 and 108 in function and scope.

Measurement circuitry 126 connected to select pin 122 measures the electrical characteristic as a function of external impedance 124 . For example, a current may be supplied to the external impedance, and the voltage developed across the external impedance 124 may then be measured. Also, a voltage can be applied across the external impedance 124 and the current measured. Any measurement technique used to measure passive components can be used to measure electrical characteristics, including dynamic and static techniques. Exemplary measurement techniques include sequential circuits, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Preferably, the measurement circuit has a high dynamic range. Measurement circuit 126 may generate an output whose value corresponds to the value of external impedance 124 . Outputs can be digital or analog. The same output value preferably represents a range of external impedance values to compensate for value variations due to process, temperature and power factors such as tolerances in external impedance values, interconnect losses and measurement circuit tolerances. For example, all measured external impedance values ranging from greater than 22 ohms to 32 ohms can be correlated to a digital output value of "0100". Whereas all measured external impedance values ranging from greater than 32 ohms to 54 ohms can be correlated to the digital output value "0101". Actual external impedance values are a subset of measured external impedance values to account for value variations. For example, in the above case, actual external impedance values may range from 24 ohms to 30 ohms, and from 36 ohms to 50 ohms. In each case, inexpensive low-precision resistors can be chosen with resistance values in the middle of the above range, such as 27 ohms and 43 ohms. This allows the use of inexpensive low-precision components to select from a range of high-precision outputs. The selected value can be used directly as a variable value to control the device characteristics of the crystal oscillator emulator 120 . The variable value can also be determined indirectly from the selection value.

Storage circuit 127 may include variable values that may be selected as a function of selected values. Storage circuitry 127 may be any type of storage structure, including content addressable memory, static and dynamic memory, and look-up tables.

For cases where the output value generated by measurement circuit 126 has a one-to-one correspondence with the external impedance value, digital value determiner 128 may then set the output value to a selected value corresponding to a range of external impedance values.

FIG. 7A shows the relationship of the set of impedance values 150 and the associated selected values 154 . Sets of impedance values 150 may have a one-to-one correspondence with sets of digital output values 152 that are converted into selected values 154 associated with each set of impedance values 150 . The impedance values ranging from the minimum impedance value to the maximum impedance value are divided into three or more groups, where each group has a nominal impedance. The nominal impedance values for each group may be selected such that there is some spacing between the nominal impedance values. Here, there is an interval of 16 ohms between the nominal values of 27 ohms and 43 ohms of the set of impedance values. The spacing between groups of impedance values is preferably based on a geometric progression, but any arithmetic relationship may be used to establish the spacing between groups, eg logarithmic, linear and exponential. The interval between impedance groups can be based on any impedance value in the group, including nominal, average, median, start, and end. Factors affecting the selection of impedance ranges and spacings for groups may include various tolerances, such as tolerances of external impedances, tolerances of internal voltage and current sources, and tolerances of measurement circuits. Tolerances may be due, for example, to process, temperature and power variations.

FIG. 7B shows the relationship between the impedance value range 156 and the associated selected value 158 . Impedance value range 156 has a direct correspondence with selected value 158 . The impedance values ranging from the minimum impedance value to the maximum impedance value are divided into three or more groups, where each group has a nominal impedance. The nominal impedance values for each group may be selected to have some spacing between the nominal impedance values. Here, there is an interval of 16 ohms between the nominal values of 27 ohms and 43 ohms of the set of impedance values. This direct correspondence between the impedance value range 156 and the associated selected value 158 can be achieved using, for example, a non-linear analog-to-digital converter (not shown).

Referring back to FIG. 6 , the address generator 130 may determine the memory location corresponding to the digital output value associated with the external impedance connected to the select pin. The memory locations can be combined in any way, such as a list for a single select pin, a lookup table for two select pins, and a three-level table for three select pins.

Controller 132 may set the device characteristics of crystal oscillator emulator 120 as a function of variable values. The variable value can be generated directly by the measurement circuit, indirectly determined from the selected value, and determined from the contents of the memory location corresponding to the external impedance value connected to the selected pin.

The select pin 122 can also be used to implement additional functions such as power down (PD), power enable, mode selection, reset, and synchronous operation. In this regard, the select pin 122 becomes a multi-purpose select pin 122 for configuring the crystal oscillator emulator 120 and implementing additional functions.

In one aspect, a first range of impedance values connected to multi-purpose select pin 124 can be used to configure crystal oscillator emulator 120, and the operation of additional functions can be controlled by the voltage or current applied to multi-purpose select pin 124. Or impedance value control outside the first range of impedance values.

FIG. 8 illustrates one aspect of the oscillator component 200 for generating an output having a periodic waveform. The oscillator component 200 includes a crystal oscillator emulator 202 for driving a phase locked loop (PLL) 204 . Crystal oscillator emulator 202 may be similar in function and structure to aspects of the crystal oscillator emulators described above. Oscillator assembly 200 may include any type of PLL 204, such as a digital PLL and an analog PLL.

Multipurpose select pins 206 and 208 may be used to select operating parameters of PLL 204, such as a frequency division factor. Multipurpose select pins 206 and 208 may also be used for crystal oscillator emulator 202 control and operation, such as output frequency selection and reference clock reception for calibration. External resistors 210 and 212 may be connected to multipurpose select pins 206 and 208 to select the operating frequency. The range of values for external resistors 210 and 212 corresponds to a selection of different operating frequencies. Each external resistor 210 and 212 can be used to select one of 16 predetermined operating frequencies. In combination, external resistors 210 and 212 can select from 256 operating frequencies. Each of the multi-purpose select pins 206 and 208 can receive signals in different voltage ranges in order to control multiple functions. For example, a multipurpose select pin 206 can be connected to an external resistor 210 on which a voltage ranging from 0 to 2 volts can be applied to determine the resistance, and the multipurpose select pin 206 can also receive voltages operating between 2 and 3 volts. Reference clock signal in the volt range. Decoder 214 may detect signals on multipurpose select pins 206 and 208 .

Figure 9 shows a spread spectrum oscillator 300 for generating an output signal with a variable frequency. The spread spectrum oscillator 300 includes a crystal oscillator emulator 302 connected to a PLL 304. A frequency control device connected to the crystal oscillator emulator 302 can dynamically control the output frequency of the crystal oscillator emulator 302 . The frequency control device, which may be any device or technology including a varactor diode, controls the bias current source of the semiconductor oscillator and controls the control input voltage applied to the resonant capacitor of the semiconductor oscillator.

Figure 10 illustrates the operation of one aspect of the crystal oscillator emulator. At block 400, a semiconductor oscillator is used to generate an output signal having a periodic waveform. Continuing to block 402, the semiconductor oscillator may be calibrated to generate a constant frequency over a predetermined temperature range. In one aspect, calibration may include varying the temperature of the semiconductor die over a predetermined temperature range and measuring calibration information for maintaining a constant output frequency. Die temperature can be measured near the semiconductor oscillator. Calibration information may include the relationship between control input values and die temperature for maintaining a constant output frequency. Calibration information may be stored in non-volatile memory on the semiconductor die. At block 404, the operating frequency may be determined by probing the external components. Continuing to block 406, the semiconductor oscillator generates an output signal having an operating frequency. At block 408, the temperature of the semiconductor die is determined in the vicinity of the semiconductor oscillator. Continuing to block 410, the semiconductor die may be heated or cooled to control the temperature of the die to one or more predetermined temperature levels. At block 412, the control input may be controlled as a function of die temperature to compensate for changes in the operating frequency of the output signal caused by temperature changes. Stored calibration information can be used to control control inputs. The calibration information can be used directly for the die temperature corresponding to the stored temperature. For other die temperatures, the control input value can be extrapolated from stored calibration information. Continuing to block 414, the frequency of the output signal may be dynamically changed as a function of the frequency control signal.

Figure 11 illustrates one aspect of a low power oscillator 320 for generating a periodic signal. Low power oscillator 320 includes crystal oscillator emulator 322 for calibrating active silicon oscillator 324 . Crystal oscillator emulator 322 is normally powered off to reduce power consumption. At predetermined intervals, the crystal oscillator emulator 322 is switched to a powered on state to calibrate the active silicon oscillator 324 . The active silicon oscillator 324 consumes less power than the crystal oscillator emulator 322, so having the active silicon oscillator 324 on continuously and the crystal oscillator emulator 322 on only intermittently reduces low power oscillations The total power consumption of the device 320. Any type of active silicon oscillator can be used, including ring oscillators and RC oscillators. Crystal oscillator emulator 322 may be configured in accordance with any of the various aspects of the invention as described and illustrated in this specification.

Summer 326 may determine the frequency error between the active silicon oscillator output and the crystal oscillator emulator output. Controller 328 may generate a control signal to control the frequency of active silicon oscillator 324 based on the frequency error. Controller 328 may also receive temperature information from crystal oscillator emulator 322 . The temperature information may include temperatures such as the temperature of the semiconductor and the ambient temperature. Controller 328 may include calibration information for active silicon oscillator 324 that is similar to calibration information for crystal oscillator emulator 322 . The frequency error can be used to set the initial value of the control signal, and then the temperature information combined with the AS oscillator calibration information can be used to update the control signal when the crystal oscillator emulator 322 is powered off. In one aspect, the temperature sensing circuitry of crystal oscillator emulator 322 may be continuously powered such that continuous temperature information may be provided to controller 328 . Control signal 334 may be digital or analog. If the control signal is digital, a digital-to-analog converter (DAC) 330 may convert the control signal to analog.

The regulator 332 can control the power supply of the active silicon oscillator 324 in response to the control signal 334 to adjust the operating frequency. The supply of voltage and/or current to active silicon oscillator 324 may be controlled. For example, regulator 332 may control the voltage level of the supply voltage.

In operation, active silicon oscillator 324 is normally on to generate a periodic output signal. Crystal oscillator emulator 322 is normally powered off. In the shutdown state, all or part of the crystal oscillator emulator 322 may be powered down to save power. At predetermined times, power is supplied to the crystal oscillator emulator 322 . The semiconductor oscillator of crystal oscillator emulator 322 is then calibrated using the stored calibration information. The frequency of the output signal of the crystal oscillator emulator 322 is compared to the frequency of the output signal of the active silicon oscillator 324 to determine the frequency error of the active silicon oscillator 324 . Control signal 334 changes in response to the frequency error, causing the supply voltage from voltage regulator 332 to shift, causing the output frequency of active silicon oscillator 324 to change, and reducing the frequency error.

Figure 12 shows an aspect of another low power oscillator 350 for generating a periodic signal. Low power oscillator 350 includes crystal oscillator emulator 352 in communication with charge pump oscillator 354 . Crystal oscillator emulator 352 is normally powered down to reduce power consumption. During the powered down state, all or part of crystal oscillator emulator 352 may be powered down. At predetermined intervals, crystal oscillator emulator 352 may be powered on and used to calibrate charge pump oscillator 354 . The predetermined interval may be determined as a function of any circuit parameter such as operating time, semiconductor temperature variation, ambient temperature variation, semiconductor temperature and supply voltage variation.

Charge pump oscillator 354 may include charge pump 356 , loop filter 358 , voltage controlled oscillator (VCO) 360 and phase detector 362 . Charge pump oscillator 354 is similar in operation to a conventional charge pump oscillator, except that the reference input of phase detector 362 receives a reference clock signal from crystal oscillator emulator 352 .

Multiplexer 364 receives output signals from crystal oscillator emulator 352 and charge pump oscillator 354 . One of the output signals is selected and passed through multiplexer 364 to phase locked loop 366 . Phase locked loop 366 generates an output signal that is a function of output signals from crystal oscillator emulator 352 and charge pump oscillator 354 .

In operation, the charge pump oscillator 354 is normally on to generate a periodic output signal. Crystal oscillator emulator 352 is normally powered off. In the shutdown state, all or part of the crystal oscillator emulator 352 may be powered down to reduce power consumption. At predetermined times, power is supplied to the crystal oscillator emulator 352 . The semiconductor oscillator of crystal oscillator emulator 352 is then calibrated using the stored calibration information. The output signal of crystal oscillator emulator 352 is compared to the output signal of charge pump oscillator 354 to determine the phase error of charge pump oscillator 354 . The VCO 360 is then controlled to reduce the phase error so that the output signal of the charge pump oscillator 354 is calibrated to the output signal of the crystal oscillator emulator 352. One of the output signals can then be selected and provided to PLL 366.

Referring now to FIGS. 13-15 , an integrated circuit 500 includes a crystal oscillator emulator 502 that generates a clock signal. One or more circuits 504 in integrated circuit 500 receive the clock signal. The crystal oscillator emulator 502 can be implemented in the manner described above in connection with FIGS. 1 to 12 . Circuitry 502 may include processor 512 shown in FIG. 14 or other circuitry. External components 506 may optionally be used to select the clock frequency of crystal oscillator emulator 502 as shown in FIGS. 13 and 15 .

Referring now to FIGS. 16-18 , integrated circuit 518 includes clock divider 520 that generates clock frequencies at one or more other clock frequencies for circuits 522-1, 522-2, . . . 522) clock signal. Circuits 522 may be interconnected with each other in any manner. Clock divider 520 divides the clock by an integer (eg, X) and/or multiplies the clock signal by Y for 1/X, Y and/or Y/X scaling. Clock divider 520 may also use one or more other ratios and/or divisors to generate different clock signals for other circuits 522 . Clock divider 520 outputs the N−1 clock signals shown to N−1 circuits 522 in integrated circuit 518 .

In FIG. 17 , one of the circuits includes a processor 530 . Processor 530 may be connected to clock divider 520 but not to crystal oscillator emulator 502 and/or to both clock divider 520 and crystal oscillator emulator 502 . Additional circuits 532 - 1 , 532 - 2 , . . . , and 532 -N communicate with clock divider 520 .

In FIG. 18 , crystal oscillator emulator 502 provides clock signals for processor 530 , graphics processor 540 , memory 542 and/or one or more circuits 544 in integrated circuit 518 . A clock divider (not shown) may also be provided. Processor 530, graphics processor 540, memory 542, and/or other circuitry 544 may be interconnected in any suitable manner.

Referring now to FIG. 19, an integrated circuit 600 includes one or more circuits 602-1, 602-2, ... and 602-N (collectively circuits 602) and a low power oscillator 320, as described above in connection with FIG. way to work. One of the circuits may include a processor, shown as 610 . As mentioned above, a clock divider (not shown) may also be provided.

Integrated circuits (ICs) are typically encased in packaging materials. The encapsulation material may include plastic. The IC substrate may include pads connected to leads of the lead frame via bondwires. The IC substrate, bonding wires and some of the leads may be encased in plastic. The properties of packaging materials typically used to package ICs may change over time. These variations can cause the oscillation frequency of the on-chip oscillator to drift over time. Variations in packaging may be due to changes in the dielectric loss of the packaging material over time. Variations in packaging may also be due to the water absorption of the packaging material at different humidity levels. As a result, the packaging material may limit the achievable calibration accuracy.

Referring now to FIG. 20, an integrated circuit 700 is packaged in an encapsulation material 704 according to the prior art. It can be appreciated that the properties of encapsulation material 704 may change over time and/or as a function of environmental conditions. For example, when encapsulation material 704 includes a plastic material, the dielectric loss of the plastic material may vary over time, which may adversely affect calibration accuracy. The term "dielectric loss" as used herein refers to energy loss that ultimately causes a temperature rise in a dielectric placed in an alternating electric field. Heating is due to "molecular friction" of the dipoles within the material as the dipoles try to reorient themselves with the oscillating (electric) field of the incident wave. For example, when things are heated in a microwave, the dipoles associated with the water in the food vibrate and are heated. Certain materials, such as certain plastics, are not suitable for use in microwaves because they absorb too much heat. These materials have high dielectric loss properties. Other materials, such as other types of plastics, experience little or no heating. These materials have lower dielectric loss properties. Since the circuits described here can operate at microwave frequencies, low dielectric loss materials are preferred.

Water absorption of plastic materials over time may also adversely affect calibration accuracy. Since water has a high dielectric loss, increasing the water content in the encapsulation material tends to increase the dielectric loss of the encapsulation material. Among other features, the encapsulation material can also be a low stress material. Highly stressed materials are prone to bending, which may affect the circuit characteristics of adjacent circuits, for example by changing the channel length. As used herein, the term "low stress" refers to a stable packaging material that is not prone to altering the electrical characteristics of the integrated circuit with changes in stress. In some implementations, the encapsulation material has a dielectric loss factor (DLF) less than or equal to Teflon (polytetrafluoroethylene) at relevant operating frequencies (eg, greater than 1 GHz).

聚三氟氯乙烯(PCTFE)、

聚全氟乙丙烯(FEP)、聚四氟乙烯(PFA)、和

乙烯-四氟乙烯共聚物(ETFE)、低介电损失塑料、高质量玻璃、空气和/或其他材料。可以考虑使用任意其他介电损失小于或等于Teflon的封装材料。封装材料还可能具有相对较低的吸水性。Referring now to FIG. 21 , an integrated circuit 710 having an on-chip semiconductor oscillator 711 with temperature compensation is shown packaged in a packaging material 714 with low dielectric loss in accordance with the present invention. The encapsulation material 714 may be a plastic encapsulation material with low dielectric loss. The term "low dielectric loss" as used herein refers to a material with a dielectric loss less than or equal to Teflon at the relevant operating frequency of the IC. The operating frequency of the IC may be greater than 1GHz and/or 2.4GHz. Encapsulation material 714 may also include

Polychlorotrifluoroethylene (PCTFE),

Polyfluoroethylene propylene (FEP), polytetrafluoroethylene (PFA), and

Ethylene-tetrafluoroethylene copolymer (ETFE), low dielectric loss plastics, high quality glass, air and/or other materials. Any other encapsulation material with a dielectric loss less than or equal to Teflon can be considered. Encapsulating materials may also have relatively low water absorption.

Referring now to FIG. 22 , an exemplary implementation of the integrated circuit package of FIG. 21 is shown in more detail. Integrated circuit package 718 includes integrated circuit 724 including pad 728 . Leads 732 of lead frame 733 are connected to pads 728 of the integrated circuit by bond wires 734 . It will be appreciated that the integrated circuit includes the above described on-chip semiconductor oscillator with temperature compensation. Portions of leads 732 , bond wires 734 and integrated circuit 724 are encapsulated in encapsulation material 736 . Encapsulation material 736 may be a plastic encapsulation material with low dielectric loss. It can be appreciated that in this and/or other embodiments, other types of packaging may be employed, such as ball grid array (BGA), flip chip, and/or any other suitable packaging technology.

Referring now to FIG. 23, another integrated circuit package 738 includes an on-chip semiconductor oscillator 741 with temperature compensation in accordance with the present invention. In this embodiment, semiconductor oscillator 741 includes an integrated circuit inductor 742 . The glass layer 744 is bonded to the integrated circuit substrate 740 by a very thin layer of epoxy 750 . The epoxy layer 750 may have low dielectric loss. Glass layer 744 , epoxy layer 750 and integrated circuit substrate 740 are encapsulated in encapsulation material 760 . In this case, due to the distance between the inductor 742 and the encapsulation material 760 , the requirement on the dielectric loss of the encapsulation material is less stringent. Thus, the requirements for changes in the dielectric loss and/or other properties of the encapsulation material 760 as a function of time are less stringent. However, the encapsulation material may be a low dielectric loss material. Although the glass layer is shown over the entire integrated circuit, the glass layer may also be localized in a smaller area immediately adjacent to the semiconductor oscillator.

Referring now to FIGS. 24 and 25, another integrated circuit package including an on-chip semiconductor oscillator according to the present invention is shown. This embodiment is similar to the embodiment shown and described above in connection with FIG. 23 . However, the glass layer 744 defines a cavity 746 . Cavity 746 is adjacent to, aligned with, and spread over inductor 742 . An air cavity 752 is formed between the inductor 742 and the glass layer 744 . A thin epoxy layer 750 is formed between the glass layer 744 and the integrated circuit substrate 740 , excluding the region of the cavity 746 . The glass layer 744 may be etched to define the cavity and dipped in epoxy. Similarly, the glass layers may comprise multiple layers of glass with cavities formed in at least one layer.

Referring now to FIG. 26, the capacitors of the on-chip semiconductor oscillator can be adjusted based on the temperature compensation described above. However, it will be appreciated that other methods exist to adjust the frequency of oscillation independently of adjustments to the capacitors and/or inductors of the semiconductor oscillator.

Referring now to FIG. 27, integrated circuit 830 includes a fractional phase locked loop 831 with a temperature compensated input. Fractional phase locked loop 831 includes a phase frequency detector 836 which receives the output of integrated circuit oscillator 832 operating in the manner described above. The phase frequency detector 836 generates a differential signal based on the difference between the reference frequency and the VCO frequency. This differential signal is output to charge pump 840 . The output of the charge pump 840 is input to an optional loop filter 844 . The output of the loop filter 844 is input to a voltage controlled oscillator (VCO), which generates a VCO output having a frequency that is related to the voltage applied to it. A scaling circuit 850 selectively divides the VCO frequency by N or N+1. Although divisors N and N+1 are used, other values are possible for the divisor.

The output of scaling circuit 850 is fed back to phase frequency detector 836 . The temperature sensor 854 measures the temperature of the integrated circuit 830 in a region near the IC oscillator 832 . Temperature sensor 854 outputs a temperature signal that is used to address calibration information 858 stored in memory 856 . The selected calibration information is used to adjust scaling circuit 850 . The selected calibration information adjusts the ratio of divisors N and N+1 used by scaling circuit 850 .

Referring now to FIG. 28, a Delta-Sigma fractional phase locked loop 858 is shown for use with an integrated circuit 860 including a temperature compensation input. The selected calibration information is used to adjust the output of the Sigma Delta modulator 870. The selected calibration information may adjust the modulation between the divisor N and N+1 used by scaling circuit 850 .

Referring now to FIG. 29 , a flowchart 900 shows steps for measuring sample calibration points and generating calibration data using a linear curve fitting algorithm. Control begins in step 902 . In step 904, control measures sample calibration points at a plurality of temperatures. In step 906, a linear curve fitting algorithm is used to generate curves for other temperature points between these sample points.

Referring now to FIG. 30 , a flowchart 920 shows steps for measuring sample calibration points and generating calibration data using a higher order curve fitting algorithm. The steps shown in FIG. 29 can be implemented using a computer including a processor and a memory. Control begins in step 922. In step 924, control measures sample calibration points at a plurality of temperatures. In step 926, a higher order curve fitting algorithm is used to generate curves for other temperature points between these sample points. In step 928, control ends.

Referring now to FIGS. 31A-31G , various exemplary implementations of the invention are shown. Referring now to FIG. 31A , the present invention may be implemented in a hard disk drive 1000 . The present invention may implement any integrated circuits, such as signal processing and/or control circuits, which are generally identified as 1002 in FIG. 31A. In some implementations, signal processing and/or control circuitry 1002 and/or other circuitry (not shown) in HDD 1000 can process data, perform encoding and/or encryption, perform computations, and/or and/or the format of the data arrangement received from the magnetic storage medium 1006 .

HDD 1000 can communicate via one or more wired or wireless communication links 1008 with a host device (not shown), such as a computer, a mobile computing device such as a personal digital assistant, cellular telephone, media or MP3 player and/or other devices. HDD 1000 may be connected to memory 1009, such as random access memory (RAM), low-latency non-volatile memory such as flash memory, read-only memory (ROM), and/or other suitable electronic data storage devices.

Referring now to FIG. 31B , the present invention may be implemented in a digital versatile disk (DVD) drive 1010 . The present invention can implement any integrated circuit such as signal processing and/or control circuits (which are generally identified as 1012 in FIG. 31B ) and/or a mass data storage device of DVD drive 1010 . Signal processing and/or control circuitry 1012 and/or other circuitry (not shown) in DVD 1010 may process data, perform encoding and/or encryption, perform calculations, and/or perform data processing for reading from and/or writing to the optical storage medium 1016 data arrangement format. In some implementations, signal processing and/or control circuitry 1012 and/or other circuitry (not shown) in DVD 1010 may also perform other functions, such as encoding and/or decoding, and/or any other signal processing functions.

DVD drive 1010 may communicate with an output device (not shown), such as a computer, television or other device, via one or more wired or wireless communication links 1017 . DVD 1010 may communicate with a mass data storage device 1018 that stores data in a non-volatile manner. Mass data storage device 1018 may include a hard disk drive (HDD). The HDD may have the configuration shown in Fig. 31A. The HDD may be a mini HDD comprising one or more platters less than about 1.8" in diameter. DVD 1010 may be connected to memory 1019, such as RAM, ROM, low-latency non-volatile memory such as flash memory, and and/or other suitable electronic data storage devices.

Referring now to FIG. 31C , the present invention may be implemented in a high definition television (HDTV) 1020 . The present invention can implement any integrated circuit such as signal processing and/or control circuits (which are generally identified as 1022 in FIG. 31C ), a WLAN interface, and/or a mass data storage device of the HDTV 1020. HDTV 1020 receives an HDTV input signal in a wired or wireless format and generates an HDTV output signal for display 1026. In some implementations, signal processing and/or control circuitry 1022 and/or other circuitry (not shown) of HDTV 1020 may process data, perform encoding and/or encryption, perform calculations, format data, and/or perform Any type of HDTV processing required.

The HDTV 1020 may communicate with a mass data storage device 1027 that stores data in a non-volatile manner, such as an optical and/or magnetic storage device. At least one HDD may have the configuration shown in FIG. 31A, and/or at least one DVD may have the configuration shown in FIG. 31B. The HDD may be a mini HDD comprising one or more platters with a diameter of less than about 1.8″. HDTV 1020 may be connected to memory 1028, such as RAM, ROM, low-latency non-volatile memory such as flash memory, and/or other suitable An electronic data storage device. The HDTV 1020 may also support a connection to a WLAN via a WLAN network interface 1029.

Referring now to FIG. 3 ID, the present invention implements any integrated circuit in the control system of the vehicle 1030, the WLAN interface, and/or the mass data storage device of the vehicle control system. In certain implementations, the present invention implements a powertrain control system 1032 that receives input from one or more sensors (eg, temperature sensors, pressure sensors, rotational sensors, airflow sensors, and/or any other suitable sensors) and/or generate one or more output control signals (eg, engine operating parameters, transmission operating parameters, and/or other control signals).

The invention may also be implemented in other control systems 1040 of the vehicle 1030 . Control system 1040 may also receive signals from input sensors 1042 and/or output control signals to one or more output devices 1044 . In some implementations, the control system 1040 can be an anti-lock braking system (ABS), navigation system, telematics system, vehicle telematics system, lane departure system, adaptive cruise control system, such as a stereo, DVD, compact disc and other vehicle entertainment systems. Other implementations are also contemplated.

The powertrain control system 1032 may communicate with a mass data storage device 1046 that stores data in a non-volatile manner. Mass data storage devices 1046 may include optical and/or magnetic storage devices such as hard disk drives HDD and/or DVD. At least one HDD may have the configuration shown in FIG. 31A, and/or at least one DVD may have the configuration shown in FIG. 31B. The HDD may be a mini HDD comprising one or more platters less than about 1.8" in diameter. The powertrain control system 1032 may be connected to memory 1047, such as RAM, ROM, low latency non-volatile memory such as flash memory and/or other suitable electronic data storage devices. The powertrain control system 1032 may also support a WLAN connection via a WLAN network interface 1048. The control system 1040 may also include mass data storage devices, memory, and/or a WLAN interface (both not shown).

Referring now to FIG. 31E , the present invention may be implemented in a cellular telephone 1050 which may include a cellular antenna 1051 . The present invention may implement any integrated circuit such as signal processing and/or control circuits (which are generally identified as 1052 in FIG. 31E ), a WLAN interface, and/or a mass data storage device of the cellular telephone 1050 . In some implementations, the cellular telephone 1050 includes a microphone 1056, an audio output 1058 such as a speaker and/or an audio output plug, a display 1060, and/or other input devices such as a keyboard, pointing device, voice activation, and/or other class of input devices 1062 . Signal processing and/or control circuitry 1052 and/or other circuitry (not shown) in cellular telephone 1050 may process data, perform encoding and/or encryption, perform calculations, format data, and/or perform other cellular telephone functions.

The cellular telephone 1050 may communicate with a mass data storage device 1064 that stores data in a non-volatile manner, such as an optical and/or magnetic storage device such as a hard disk drive HDD and/or DVD. At least one HDD may have the configuration shown in FIG. 31A, and/or at least one DVD may have the configuration shown in FIG. 31B. The HDD may be a mini HDD comprising one or more platters with a diameter of less than about 1.8″. Cellular phone 1050 may be connected to memory 1066, such as RAM, ROM, low-latency non-volatile memory such as flash memory, and/or Other suitable electronic data storage devices. Cellular telephone 1050 may also support connection to WLAN via WLAN network interface 1068 .

Referring now to FIG. 31F , the present invention may be implemented in a set top box 1080 . The present invention may implement any integrated circuit such as signal processing and/or control circuits (which are generally identified as 1084 in FIG. 31F ), a WLAN interface, and/or a mass data storage device of the set-top box 1080 . Set-top box 1080 receives signals from sources (e.g., broadband sources) and outputs standard and/or high-definition audio/video signals suitable for display 1088, such as a television and/or monitor and/or other video and/or Audio output device. Signal processing and/or control circuitry 1084 and/or other circuitry (not shown) of set-top box 1080 may process data, perform encoding and/or encryption, perform calculations, format data, and/or perform any other set-top box functions.

The set top box 1080 may communicate with a mass data storage device 1090 that stores data in a non-volatile manner. The mass data storage device 1090 may include optical and/or magnetic storage devices such as hard disk drives HDD and/or DVD. At least one HDD may have the configuration shown in FIG. 31A, and/or at least one DVD may have the configuration shown in FIG. 31B. The HDD may be a mini HDD comprising one or more platters with a diameter of less than about 1.8″. The set-top box 1080 may be connected to memory 1094, such as RAM, ROM, low-latency non-volatile memory such as flash memory, and/or other A suitable electronic data storage device.

Referring now to FIG. 31G , the present invention may be implemented in a media player 1100 . The present invention may implement any integrated circuit such as signal processing and/or control circuits (which are generally identified as 1104 in FIG. 31G ), a WLAN interface, and/or a mass data storage device of the media player 1100. In some implementations, the media player 1100 includes a display 1107 and/or user input 1108, such as a keyboard, touch pad, and the like. In some implementations, media player 1100 may employ a graphical user interface (GUI), typically employing menus, drop-down menus, icons, and/or point-and-click interfaces, via display 1107 and/or user input 1108. The media player 1100 also includes an audio output 1109, such as a speaker and/or an audio output plug. Signal processing and/or control circuitry 1104 and/or other circuitry (not shown) of media player 1100 may process data, perform encoding and/or encryption, perform calculations, format data, and/or perform any other media player Function.

The media player 1100 may communicate with a mass data storage device 1110 that stores data (eg, compressed audio and/or video content) in a non-volatile manner. In some implementations, compressed audio files include files conforming to MP3 format or other suitable compressed audio and/or video formats. The mass data storage devices may include optical and/or magnetic storage devices such as hard disk drives HDD and/or DVD. At least one HDD may have the configuration shown in FIG. 31A, and/or at least one DVD may have the configuration shown in FIG. 31B. The HDD may be a mini HDD comprising one or more platters with a diameter of less than about 1.8″. The media player 1100 may be connected to memory 1114, such as RAM, ROM, low-latency non-volatile memory such as flash memory, and/or or other suitable electronic data storage device. Media player 1100 may also support connection to a WLAN via WLAN network interface 1116. Other implementations than those described above are also contemplated.

Referring now to FIGS. 32A-32D , integrated circuit packages are shown incorporating annealed glass paste or epoxy as a layer and/or "islands" adjacent to one or more selected features of a silicon wafer. One or more "islands" of annealed glass paste or epoxy layers may be provided on portions of one or both sides of the silicon wafer. In FIG. 32A , another integrated circuit package 1200 includes a silicon wafer 1204 . A layer or portions 1206 of annealed glass paste is formed on a silicon wafer 1204 . Molding material 1208 may be used to encapsulate all or part of silicon wafer 1204 . Annealing the glass paste layer 1206 also reduces stress variation over time. Annealing the glass paste layer 1206 tends to insulate all or part of the silicon wafer 1204 from changes in the dielectric properties of the mold material 1208 (eg, dielectric loss).

The silicon wafer 1204 may include the semiconductor oscillator described above. Annealed glass paste layer 1206 may include glass paste with a relatively low annealing temperature. The low annealing temperature may be below a temperature that would damage the silicon wafer 1204 . The glass paste layer 1206 may include glass frit. The glass paste layer may be applied in any suitable manner. The glass paste layer may be applied using a screen printing method, a dipping method, a color separation coating method, and/or using any other suitable method.

In FIG. 32B , another integrated circuit package 1210 includes a layer or coating 1212 of conductive material that is applied to a layer 1206 of glass paste or epoxy. The conductive material layer 1212 may include a conductive epoxy layer. The layer of conductive material 1212 may be applied as a liquid and then cured. The layer of conductive material 1212 may include conductive epoxy paint. The layer of conductive material 1212 may be applied in any suitable manner, including dipping the silicon wafer 1204 in a container (eg, a plate) containing the conductive material. The conductive material layer 1212 tends to reduce electromagnetic interference from external devices.

In FIG. 32C , integrated circuit package 1220 includes annealed glass paste layer 1206 that is applied to selected portions of silicon wafer 1204 . In FIG. 32D , integrated circuit package 1230 includes annealed glass paste or epoxy portion 1206 and conductive material 1212 . The conductive material 1212 may cover the annealed glass paste layer 1206 with or without touching the silicon wafer 1204 .

Referring now to FIGS. 33A-33D , further integrated circuit packages are shown. In FIG. 33A , another integrated circuit package 1240 includes a layer of annealed glass paste 1206 and a layer of conductive material 1212 positioned adjacent to a circuit component 1242 of a silicon wafer 1204 . In FIG. 33B , another integrated circuit package 1250 includes a layer of annealed glass paste 1206 and a layer of conductive material 1212 positioned adjacent to an oscillator 1252 on a silicon wafer 1204 .

In FIG. 33C , another integrated circuit package 1260 includes a layer of annealed glass paste 1206 and a layer of conductive material 1212 positioned adjacent to an inductor 1262 on a silicon wafer 1204 . Inductor 1262 may be an on-chip inductor, such as a spiral inductor. In FIG. 33D , another integrated circuit package 1270 includes a layer of annealed glass paste 1206 and a layer of conductive material 1212 positioned adjacent to an oscillator circuit 1272 with an inductor 1274 .

Annealing the paste layer also tends to reduce possible stress variations over time. Annealing the glass paste layer insulates all or part of the silicon wafer from changes in the dielectric properties (eg, dielectric loss) of the casting material. This is especially beneficial when trying to calibrate using temperature (as described above).

Referring now to FIGS. 34A-34D , further integrated circuit packages are shown that include annealed glass paste and/or epoxy portions and glass or silicon layers that create air gaps in portions of the silicon wafer. In FIGS. 34A-34B , integrated circuit packages 1300 and 1330 include silicon wafer 1304 . Annealed glass paste portions 1306 are formed on silicon wafer 1304 in some spatially separated relationship. AGP portion 1306 can be formed as described above. A casting material 1308 may be used. Post-processing of the AGP portion 1306 may be performed (eg, polishing or other steps) to provide a planar outer surface.

Glass or silicon layer 1310 is supported over silicon wafer 1304 by means of AGP portion 1306 . Epoxy or other bonding material may be used to adhere glass or silicon layer 1310 to AGP portion 1306 . AGP portion 1306 and glass or silicon layer 1310 form an air gap 1324 over oscillator 1320 (FIG. 34A) and/or any other circuitry 1322 (FIG. 34B). The air gap 1324 provides the material (air) with the lowest possible dielectric loss. In contrast, when using a crystal oscillator, air is required to allow the crystal to resonate, in other words, air is used to allow mechanical oscillation.

In FIGS. 34C-34D , integrated circuit packages 1340 and 1360 include silicon wafer 1304 . Epoxy portions 1342 are formed on silicon wafer 1304 in some spatially separated relationship. Epoxy portion 1342 may be formed as described above. Post-processing of epoxy portion 1342 may be performed (eg, polishing or other steps) to provide a flat outer surface. Glass or silicon layer 1310 is supported over silicon wafer 1304 by means of epoxy portion 1342 . Epoxy or other bonding material may be used to bond glass or silicon layer 1310 to epoxy portion 1342 . Epoxy portion 1342 and glass or silicon layer 1310 form air gap 1324 over oscillator 1320 (FIG. 34C) and/or any other circuitry 1322 (FIG. 34D).

Referring now to FIGS. 35A-35B , further integrated circuit packages are shown that include glass or silicon portions that create air gaps. In FIG. 35A , integrated circuit package 1380 includes a “C” shaped glass or silicon portion 1382 that defines an air gap 1384 . The "C" shaped glass or silicon portion 1382 may comprise multiple segments joined together. Air gap 1384 is located above oscillator 1320 . In FIG. 35B , integrated circuit package 1390 includes a “C” shaped glass or silicon layer 1382 that defines an air gap 1384 . Air gap 1384 is located above circuit 1322 .

Referring now to FIGS. 36A-36C , there is shown a method for fabricating the integrated circuit package described above. Integrated circuit structure 1400 includes silicon wafer 1404 , a plurality of spaced apart AGP and/or epoxy portions 1410A and 1410B (collectively portions 1410 ), and glass or silicon layer 1408 . Integrated circuit structure 1400 is diced into multiple segments along dashed lines 1414 to create multiple integrated circuits, which may be encapsulated in the aforementioned molding material (not shown).

In FIG. 36B, silicon wafer 1404 may include one or more bond pads 1420. The cutouts of layer 1408 at 1414-1 and 1414-2 may be offset relative to the cutouts of the silicon wafer at 1414-3 to provide for Bonding wires (not shown) are attached to the gaps of the bonding pads 1420 . In FIG. 36C , one of the integrated circuits 1450 singulated from the integrated circuit structure 1400 is shown.

Referring now to FIGS. 37A-37B , an integrated circuit package 1450 includes a silicon wafer with a plurality of spaced apart annealed glass paste and/or epoxy portions 1410 coated with a layer of conductive material 1456 . In FIG. 37A , portion 1410 is dipped in container 1454 containing conductive material 1456 . Silicon wafer 1408 may be diced along one or more tangent lines 1462, and may include bond pads 1460, as shown.

Referring now to FIG. 38, the steps of a method 1500 for fabricating the integrated circuit package of FIGS. 32A-33D are shown. Control begins in step 1502. At step 1504 , a layer of glass paste 1206 is applied to one or more surfaces of silicon wafer 1204 and/or selected areas of silicon wafer 1204 . At step 1506, the glass paste layer 1206 is annealed by placing the silicon wafer 1204 and the glass paste layer 1206 in an oven. The temperature of the oven may be set to a temperature sufficient to cure the glass paste layer 1206 . For example, a temperature of about 400° C. for a predetermined period of time is sufficient to anneal the glass frit without damaging the silicon wafer 1204 . In step 1508 , layer 1212 of conductive material is applied to layer 1206 of annealed glass paste. At step 1510, all or part of the silicon wafer 1204 is encased in a molding material 1208, such as plastic, other materials described herein, and/or other suitable molding materials. In step 1520, control ends.

In each of the embodiments described above, the silicon wafer can be replaced by other wafers or other substrates, and the annealed glass paste can be replaced by epoxy.

A number of embodiments of the invention have been described. However, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.

This application claims U.S. Provisional Application No. 60/714,454 filed September 6, 2005, U.S. Provisional Application No. 60/756,828 filed January 6, 2006, and U.S. Provisional Application No. 60/756,828 filed October 27, 2005. 60/730,568, and this application is a continuation-in-part of U.S. Patent Application No. 10/892,709, filed July 16, 2004, which is U.S. Patent Application No. 10/892,709, filed October 15, 2002 A continuation-in-part of Application No. 10/272,247, which is hereby incorporated by reference in its entirety for all of the above applications.

Claims (4)

1. An integrated circuit package comprising: integrated circuits, including: a temperature sensor that senses the temperature of the integrated circuit; a memory module that stores oscillator calibrations and selects one of the oscillator calibrations as a function of the sensed temperature; and an oscillator module that generates a reference signal whose frequency is based on one of said selected oscillator calibrations; glass layer; an epoxy layer adhering the glass layer to the integrated circuit; and an encapsulating material encapsulating at least a portion of said integrated circuit and said glass layer, and Wherein the glass layer includes a cavity defining an air gap, and the cavity is adjacent to the portion of the integrated circuit that includes the oscillator module. 2. The integrated circuit package of claim 1, wherein the glass layer is located adjacent to a portion of the integrated circuit that includes the oscillator module. 3. The integrated circuit package of claim 1, wherein the oscillator module includes an on-chip inductor, and wherein the glass layer is located adjacent to a portion of the integrated circuit that includes the on-chip inductor. 4. The integrated circuit package of claim 1, wherein the cavity is adjacent to a portion of the integrated circuit that includes an inductor of the oscillator module.

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