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CN1925167A - Semiconductor element and method of forming the same - Google Patents

Semiconductor element and method of forming the same Download PDF

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CN1925167A
CN1925167A CNA2006100035909A CN200610003590A CN1925167A CN 1925167 A CN1925167 A CN 1925167A CN A2006100035909 A CNA2006100035909 A CN A2006100035909A CN 200610003590 A CN200610003590 A CN 200610003590A CN 1925167 A CN1925167 A CN 1925167A
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semiconductor device
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CN100589251C (en
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郑光茗
郑钧隆
庄学理
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device and a method of forming the same, the semiconductor device comprising: a conductor pattern; an L-shaped spacer including a vertical portion and a horizontal portion, the vertical portion being disposed on the lower sidewall of the conductor pattern to expose the upper sidewall of the conductor pattern; and a top spacer disposed on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2: 1. The invention provides a simple and easily controlled spacer to increase the area of metal silicide formation, the formed spacer can reduce undercut caused by side wall etching, the complexity of spacer process can not be increased, and the invention can be realized by only changing the thickness ratio of the insulating layer.

Description

半导体元件及其形成方法Semiconductor element and method of forming the same

技术领域technical field

本发明有关于一种半导体制程技术，特别有关于一种具有侧壁间隙壁的半导体元件及其形成方法。The invention relates to a semiconductor manufacturing process technology, in particular to a semiconductor element with a sidewall spacer and a forming method thereof.

背景技术Background technique

金属硅化物已普遍用来降低栅极电阻以及栅极间源极及漏极的电阻。然而，随着半导体元件尺寸逐渐缩小，两栅极间的距离也随之缩小，由于栅极间隙壁具有一定的宽度，因此形成金属硅化物的可用空间比栅极间距缩小的更快，因此在栅极间形成金属硅化物也日趋困难，造成在这些区域中电阻变的过大且分布不均。此外，以干蚀刻形成间隙壁时，由于厚度越来越薄蚀刻条件控制不良时很容易造成栅极间的间隙壁宽度不一致，进而降低电阻的均匀性。Metal silicides have been commonly used to reduce the gate resistance and the resistance of the source and drain between the gates. However, as the size of semiconductor elements shrinks gradually, the distance between the two gates also shrinks. Since the gate spacer has a certain width, the available space for forming metal silicide shrinks faster than the gate pitch, so in It is also increasingly difficult to form metal silicides between the gates, resulting in excessive and uneven distribution of resistance in these regions. In addition, when the spacer is formed by dry etching, the width of the spacer between the gates is likely to be inconsistent due to the thinner and thinner etching conditions and poor control of the etching conditions, thereby reducing the uniformity of resistance.

图1显示半导体元件的截面图，在半导体基底10上形成两晶体管栅极图案12，包括栅极电极14形成在栅极介电层16上。氧化衬层18及氮化硅层20依序形成在栅极图案12及半导体基底10上，其中，氮化硅层20厚度大于氧化衬层18，例如依80nm制程的设计规则氮化硅层18及氧化衬层20的厚度分别约650埃和130埃。1 shows a cross-sectional view of a semiconductor device. Two transistor gate patterns 12 are formed on a semiconductor substrate 10 , including a gate electrode 14 formed on a gate dielectric layer 16 . An oxide lining layer 18 and a silicon nitride layer 20 are sequentially formed on the gate pattern 12 and the semiconductor substrate 10, wherein the thickness of the silicon nitride layer 20 is greater than that of the oxide lining layer 18, for example, the silicon nitride layer 18 is designed according to the design rules of the 80nm process. and the thickness of the oxide lining layer 20 are about 650 angstroms and 130 angstroms, respectively.

如图2和图3所示，以传统的间隙壁蚀刻制程以形成L形的氧化物间隙壁18a及较厚的氮化物间隙壁20a。在形成源极或漏极区域22后，将金属硅化物24形成在露出的栅极电极14及源极或漏极区域表面上。由于金属硅化物的间距d取决于间隙壁的宽度，因此间隙壁的宽度变化会降低电阻的均匀度。如图2所示的传统间隙壁由于常造成间隙壁的宽度不一致，需要复杂的制程参数微调来降低宽度的差异。因此业界亟需要一种宽度较易控制的间隙壁设计，也需要缩小间隙壁宽度来增加金属硅化物形成的空间。As shown in FIG. 2 and FIG. 3 , the L-shaped oxide spacer 18 a and the thicker nitride spacer 20 a are formed by conventional spacer etching process. After forming the source or drain region 22, a metal silicide 24 is formed on the exposed surface of the gate electrode 14 and the source or drain region. Since the distance d of the metal silicide depends on the width of the spacer, the variation of the width of the spacer will reduce the uniformity of the resistance. As shown in FIG. 2 , the traditional spacers often have inconsistent widths of the spacers, and complex fine-tuning of process parameters is required to reduce the width difference. Therefore, the industry urgently needs a spacer design whose width is easier to control, and also needs to reduce the width of the spacer to increase the space for the formation of metal silicide.

传统间隙壁也会产生顶部损失的问题，回到图2，干蚀刻后只有一小部分栅极电极侧壁露出。由于露出的区域有限，较难形成金属硅化物以致于无法得到高效能的晶体管，因此需较大的区域来形成金属硅化物。The traditional spacer also has the problem of top loss. Going back to Figure 2, only a small part of the sidewall of the gate electrode is exposed after dry etching. Due to the limited exposed area, it is difficult to form the metal silicide so that high-performance transistors cannot be obtained. Therefore, a larger area is required to form the metal silicide.

图4显示另一传统间隙壁所产生的另一问题。蚀刻穿过层间介电层28以及接触蚀刻停止层26形成接触窗30，并露出源极或漏极区域22。由于蚀刻停止层26一般为氮化硅，因此在蚀刻移除蚀刻停止层时氮化物间隙壁20a侧壁会受到蚀刻，会产生底切部分(undercut)30a。侧壁蚀刻造成可靠度的问题，特别是在接触窗未对准时。FIG. 4 shows another problem caused by another conventional spacer. Etching through ILD layer 28 and contacting etch stop layer 26 forms contact opening 30 and exposes source or drain region 22 . Since the etch stop layer 26 is generally silicon nitride, the sidewall of the nitride spacer 20 a will be etched when the etch stop layer is removed by etching, resulting in an undercut 30 a. Sidewall etching poses reliability problems, especially when contacts are misaligned.

发明内容Contents of the invention

为解决上述问题，本发明提供一种半导体元件，包括：一导体图案；一L形间隙壁，包括一垂直部分及一水平部分，该垂直部分置于该导体图案的较低侧壁上，露出该导体图案的上层侧壁；以及一顶部间隙壁，置于该L形间隙壁上，其中该L形间隙壁的该垂直部分对于该顶部间隙壁的宽度至少约2∶1。In order to solve the above problems, the present invention provides a semiconductor element, comprising: a conductor pattern; an L-shaped spacer comprising a vertical portion and a horizontal portion, the vertical portion is placed on the lower sidewall of the conductor pattern, exposing The upper sidewall of the conductor pattern; and a top spacer disposed on the L-shaped spacer, wherein the vertical portion of the L-shaped spacer has a width of at least about 2:1 to the top spacer.

本发明所述的半导体元件，该L形间隙壁的该垂直部分对于该顶部间隙壁的宽度比约2～4∶1。According to the semiconductor device of the present invention, the width ratio of the vertical portion of the L-shaped spacer to the top spacer is about 2˜4:1.

本发明所述的半导体元件，该垂直部分的宽度对于该导体图案所露出的上层侧壁的高度比约1～2∶1。In the semiconductor device of the present invention, the ratio of the width of the vertical portion to the height of the exposed upper layer sidewall of the conductor pattern is about 1˜2:1.

本发明所述的半导体元件，该水平部分包括该顶部间隙壁下的底切部分，其中该底切部分的宽度对于该水平部分的高度比低于约0.3。According to the semiconductor device of the present invention, the horizontal portion includes an undercut portion under the top spacer, wherein the ratio of the width of the undercut portion to the height of the horizontal portion is lower than about 0.3.

本发明所述的半导体元件，该L形间隙壁及该顶部间隙壁彼此间具有蚀刻选择性。In the semiconductor device of the present invention, the L-shaped spacer and the top spacer have etching selectivity to each other.

本发明所述的半导体元件，该导体图案经金属硅化。In the semiconductor device of the present invention, the conductor pattern is silicided.

本发明所述的半导体元件，该垂直部分的宽度约350～450埃，而该顶部间隙壁的宽度约100～200埃。In the semiconductor device of the present invention, the width of the vertical portion is about 350-450 angstroms, and the width of the top spacer is about 100-200 angstroms.

本发明所述的半导体元件，该L形间隙壁的该垂直部分约露出200～400埃的该导体图案。According to the semiconductor device of the present invention, the vertical portion of the L-shaped spacer exposes about 200-400 angstroms of the conductor pattern.

本发明更提供一种形成半导体元件的方法，包括在一半导体基底上形成一导体图案；在该导体图案及该半导体基底上顺应性的形成厚度比至少约2∶1的一第一绝缘层及一第二绝缘层；非等向性蚀刻该第二绝缘层，形成一顶部间隙壁；以及非等项性蚀刻该第一绝缘层，形成一L形间隙壁，其中该L形间隙壁的顶部表面低于该导体图案。The present invention further provides a method for forming a semiconductor element, comprising forming a conductor pattern on a semiconductor substrate; conformally forming a first insulating layer and a first insulating layer having a thickness ratio of at least about 2:1 on the conductor pattern and the semiconductor substrate. a second insulating layer; anisotropically etching the second insulating layer to form a top spacer; and anisotropically etching the first insulating layer to form an L-shaped spacer, wherein the top of the L-shaped spacer The surface is below the conductor pattern.

本发明所述的形成半导体元件的方法，L形间隙壁包括一垂直部分及一水平部分。According to the method for forming a semiconductor element of the present invention, the L-shaped spacer includes a vertical portion and a horizontal portion.

本发明所述的形成半导体元件的方法，该L形间隙壁的该垂直部分对于该顶部间隙壁的宽度比约2～4∶1。According to the method for forming a semiconductor device of the present invention, the width ratio of the vertical portion of the L-shaped spacer to the top spacer is about 2˜4:1.

本发明所述的形成半导体元件的方法，该垂直部分的宽度对于该导体图案所露出的上层侧壁的高度比约1～2∶1。According to the method for forming a semiconductor element of the present invention, the ratio of the width of the vertical portion to the height of the upper sidewall exposed by the conductor pattern is about 1-2:1.

本发明所述的形成半导体元件的方法，该水平部分为该顶部间隙壁下的底切部分，其中该底切部分的宽度对于该水平部分的高度比低于约0.3。According to the method of forming a semiconductor device of the present invention, the horizontal portion is an undercut portion under the top spacer, wherein the ratio of the width of the undercut portion to the height of the horizontal portion is lower than about 0.3.

本发明所述的形成半导体元件的方法，该L形间隙壁及该顶部间隙壁彼此间具有蚀刻选择性。According to the method for forming a semiconductor element of the present invention, the L-shaped spacer and the top spacer have etching selectivity to each other.

本发明所述的形成半导体元件的方法，该导体图案经金属硅化。According to the method for forming a semiconductor element of the present invention, the conductor pattern is silicided by metal.

由上述可得知，本发明提供一简单且易控制间隙壁来增加金属硅化物形成的面积。由于间隙壁厚度的缩小，也使本发明的间隙壁结构可应用在下一代。此外，本发明所形成的间隙壁可降低因侧壁蚀刻所产生的底切。再者，本发明不会增加间隙壁制程的复杂度，简单来说，只需改变绝缘层的厚度比即可达成本发明。From the above, it can be seen that the present invention provides a simple and easy-to-control spacer to increase the area where the metal silicide is formed. Due to the shrinkage of the spacer thickness, the spacer structure of the present invention can also be applied to the next generation. In addition, the spacers formed by the present invention can reduce undercuts caused by sidewall etching. Furthermore, the present invention does not increase the complexity of the spacer process. Simply speaking, the present invention can be achieved only by changing the thickness ratio of the insulating layer.

附图说明Description of drawings

图1至图4显示传统半导体元件的剖面图，并描绘出传统间隙壁所产生的问题。1 to 4 show cross-sectional views of conventional semiconductor devices and illustrate problems caused by conventional spacers.

图5至图9显示以本发明实施例形成凹陷L形间隙壁的方法。5 to 9 show a method for forming a recessed L-shaped spacer according to an embodiment of the present invention.

具体实施方式Detailed ways

为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合附图作详细说明如下：In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and is described in detail in conjunction with the accompanying drawings as follows:

接下来以本发明的较佳实施例来描述在场效应晶体管的栅极图案上侧壁间隙壁的形成。然而，本发明也可应用至集成电路中各种导体图案，例如，局部内连接线或其他用以连接各半导体元件的多晶硅。本文中所述的“在基板上”、“在一层状结构上”或“在一薄膜上”均是描述与底层表面的相对位置，而不管两者之间是否还存在其他结构，由此可知，这种表达方式可解读为上下两结构直接接触，也可解读为两结构间尚具有其他组成而没有直接接触。Next, the formation of the sidewall spacer on the gate pattern of the field effect transistor will be described with a preferred embodiment of the present invention. However, the present invention can also be applied to various conductor patterns in integrated circuits, such as local interconnection lines or other polysilicon used to connect semiconductor devices. The words "on a substrate", "on a layered structure" or "on a thin film" described herein describe the relative position to the underlying surface, regardless of whether there are other structures between the two, thus It can be seen that this expression can be interpreted as the direct contact between the upper and lower structures, or it can be interpreted as there are other components between the two structures without direct contact.

如图5所示，半导体基底100上具有晶体管栅极图案102。虽然基底上一般具有相邻的栅极，但为了简化图示，图中只显示一栅极图案。半导体基底100一般为硅、受应变硅、硅锗、绝缘层上硅(SOI)或其他适合的材料。栅极图案102包括，栅极电极106，置于栅极介电层104之上。栅极介电层104包括氧化硅，而栅极电极106包括掺杂多晶硅，一般简称为多晶硅。As shown in FIG. 5 , there is a transistor gate pattern 102 on the semiconductor substrate 100 . Although there are generally adjacent gates on the substrate, only one gate pattern is shown in the figure for simplicity of illustration. The semiconductor substrate 100 is generally made of silicon, strained silicon, silicon germanium, silicon-on-insulator (SOI), or other suitable materials. The gate pattern 102 includes a gate electrode 106 disposed on the gate dielectric layer 104 . The gate dielectric layer 104 includes silicon oxide, and the gate electrode 106 includes doped polysilicon, generally referred to simply as polysilicon.

可在形成本发明侧壁间隙壁之前，先在半导体基底100中布植杂质离子，以形成LDD(Lightly doped source and drain)(未显示)。布植制程时可如先前技术利用栅极图案作为掩膜。Impurity ions may be implanted in the semiconductor substrate 100 before forming the sidewall spacers of the present invention to form LDD (Lightly doped source and drain) (not shown). During the implantation process, the gate pattern can be used as a mask as in the prior art.

图5显示本发明重要的发明特征，在半导体基底100上及栅极图案102上顺应性沉积第一绝缘层108及第二绝缘层110，其中第一绝缘层108厚度大于第二绝缘层110。第一绝缘层108及第二绝缘层110的厚度比至少约2∶1，较佳约2～4∶1。例如80nm制程的设计规则，第一绝缘层108及第二绝缘层110的厚度分别约350～450埃以及100～200埃。在本发明一较佳实施例中，第一绝缘层108是以TEOS为反应性气体，利用低压化学气相沉积(LPCVD)形成的氧化硅，而第二绝缘层110是利用低压化学气相沉积法形成的氮化硅或氮氧化硅。然而，在其他实施例中第一及第二绝缘层还可为任何两种具有高蚀刻选择性的材料。FIG. 5 shows the important inventive features of the present invention. The first insulating layer 108 and the second insulating layer 110 are conformally deposited on the semiconductor substrate 100 and the gate pattern 102 , wherein the thickness of the first insulating layer 108 is greater than that of the second insulating layer 110 . The thickness ratio of the first insulating layer 108 and the second insulating layer 110 is at least about 2:1, preferably about 2˜4:1. For example, according to the design rule of 80nm process, the thicknesses of the first insulating layer 108 and the second insulating layer 110 are about 350-450 angstroms and 100-200 angstroms respectively. In a preferred embodiment of the present invention, the first insulating layer 108 is silicon oxide formed by low-pressure chemical vapor deposition (LPCVD) using TEOS as a reactive gas, and the second insulating layer 110 is formed by low-pressure chemical vapor deposition. silicon nitride or silicon oxynitride. However, in other embodiments, the first and second insulating layers can also be any two materials with high etch selectivity.

图6显示本发明另一重要的特征，将第一绝缘层108及第二绝缘层110分别蚀刻成L形间隙壁108a及一顶部间隙壁110a。首先，非等向性蚀刻第二绝缘层110，在第一绝缘层108的侧壁上形成顶部间隙壁110a，接着以顶部间隙壁110a作为蚀刻掩膜，非等向性蚀刻第一绝缘层108，以在栅极图案102及间隙壁110a间形成L形间隙壁108a。特别的是，非等向性蚀刻降低栅极图案102及间隙壁110a间第一绝缘层108的垂直厚度，因此露出部分上层侧壁102a约200～400埃。L形间隙壁108a包括一垂直部分V，介于栅极图案102及顶部间隙壁110a之间，以及一水平部分H，在顶部间隙壁110a下延伸。L形间隙壁108a的蚀刻较佳利用相对于第一绝缘层具有高蚀刻选择性的蚀刻制程。FIG. 6 shows another important feature of the present invention. The first insulating layer 108 and the second insulating layer 110 are respectively etched into an L-shaped spacer 108 a and a top spacer 110 a. First, the second insulating layer 110 is anisotropically etched to form a top spacer 110a on the sidewall of the first insulating layer 108, and then the first insulating layer 108 is anisotropically etched using the top spacer 110a as an etching mask. , so as to form an L-shaped spacer 108a between the gate pattern 102 and the spacer 110a. In particular, the anisotropic etching reduces the vertical thickness of the first insulating layer 108 between the gate pattern 102 and the spacer 110a, thus exposing a portion of the upper sidewall 102a of about 200˜400 angstroms. The L-shaped spacer 108a includes a vertical portion V interposed between the gate pattern 102 and the top spacer 110a, and a horizontal portion H extending under the top spacer 110a. The etching of the L-shaped spacer 108a preferably utilizes an etching process with high etching selectivity relative to the first insulating layer.

相较于图1及图2所示的传统间隙壁的制程，本发明具有多种优点，第一，较厚的第一绝缘层108可使L形间隙壁108a的顶部较易移除。因此可露出栅极图案102的侧壁部分102a，在后续制程中提供较大的金属硅化反应区域。本发明中，L形间隙壁垂直部分V的宽度X与露出的侧壁部分102a的高度Y之比较佳约1～2∶1。Compared with the conventional spacer manufacturing process shown in FIG. 1 and FIG. 2 , the present invention has many advantages. First, the thicker first insulating layer 108 makes it easier to remove the top of the L-shaped spacer 108 a. Therefore, the sidewall portion 102a of the gate pattern 102 can be exposed to provide a larger metal silicide reaction area in subsequent processes. In the present invention, the ratio of the width X of the vertical portion V of the L-shaped spacer to the height Y of the exposed sidewall portion 102a is preferably about 1˜2:1.

第二，如图5及图6所示，间隙壁的轮廓取决于薄的第二绝缘层110。相较于图1中较厚的氮化层20，本发明在晶圆上形成的厚度较均匀，可缩短蚀刻时间或降低蚀刻功率，因此降低间隙壁宽度的变化。由此可知，本发明间隙壁的宽度较易控制，并改善相邻栅极间的电阻均匀性。Second, as shown in FIGS. 5 and 6 , the profile of the spacer depends on the thin second insulating layer 110 . Compared with the thicker nitride layer 20 in FIG. 1 , the present invention forms a more uniform thickness on the wafer, which can shorten the etching time or reduce the etching power, thus reducing the variation of the spacer width. It can be seen that the width of the spacers in the present invention is easier to control and improves the resistance uniformity between adjacent gates.

第三，由于间隙壁宽度较易控制，间隙壁蚀刻的限制较低，因此，可降低间隙壁的总厚度，例如第一绝缘层108及第二间隙壁110的总厚度，以在相邻两栅极间获得更多空间进行金属硅化，特别是在栅极间距随设计规则缩小时，例如，以氧化硅作为第一绝缘层108，以氮化硅作为第二绝缘层110，如图1的传统方法需要氧化硅及氮化硅层的总厚度约780埃(氧化层约130埃、氮化硅层约650埃)以获得栅极间距约1630埃，而本发明依相同的设计规则只需总厚度约530埃的氧化硅(400埃)及氮化硅(130埃)，厚度可减少约30％。Third, since the width of the spacer is easier to control, the limitation of spacer etching is lower. Therefore, the total thickness of the spacer, such as the total thickness of the first insulating layer 108 and the second spacer 110, can be reduced to achieve Gain more space between the gates for metal silicide, especially when the gate pitch shrinks with the design rules, for example, silicon oxide is used as the first insulating layer 108, and silicon nitride is used as the second insulating layer 110, as shown in Figure 1 The traditional method needs the total thickness of the silicon oxide and silicon nitride layers to be about 780 angstroms (about 130 angstroms for the oxide layer and about 650 angstroms for the silicon nitride layer) to obtain a gate pitch of about 1630 angstroms, while the present invention only needs to use the same design rules. The total thickness of silicon oxide (400 angstroms) and silicon nitride (130 angstroms) is about 530 angstroms, and the thickness can be reduced by about 30%.

图6显示本发明实施例的半导体元件，包括栅极图案102于半导体基底100之上。一L形间隙壁108a相邻于栅极图案102，包括一垂直部分V及一水平部分H，其中垂直部分V位于栅极图案102较低的侧壁上，并露出上层侧壁102a。顶部间隙壁110a紧靠并突出L形间隙壁108a，因此在顶部间隙壁110a及栅极图案102上层侧壁间形成一缺口。L形间隙壁108a垂直部分V与顶部间隙壁110a的宽度比至少约2∶1(X/W)，较佳约2～4∶1。而垂直部分V的宽度与上层侧壁露出部分高度Y之比约1～2∶1(X/Y)。FIG. 6 shows a semiconductor device according to an embodiment of the present invention, including a gate pattern 102 on a semiconductor substrate 100 . An L-shaped spacer 108 a is adjacent to the gate pattern 102 and includes a vertical portion V and a horizontal portion H, wherein the vertical portion V is located on the lower sidewall of the gate pattern 102 and exposes the upper sidewall 102 a. The top spacer 110 a is close to and protrudes from the L-shaped spacer 108 a , thus forming a gap between the top spacer 110 a and the upper sidewall of the gate pattern 102 . The width ratio of the vertical portion V of the L-shaped spacer 108a to the top spacer 110a is at least about 2:1 (X/W), preferably about 2˜4:1. The ratio of the width of the vertical portion V to the height Y of the exposed portion of the upper sidewall is about 1˜2:1 (X/Y).

如图7所示，形成间隙壁108a及110a后，接着在半导体基底100中相邻于栅极图案102两侧布植形成源极或漏极区域112。之后以传统已知的方法，在源极或漏极区域112与栅极图案102上形成栅极硅化物层116以及接面金属硅化物层114，其中金属硅化物层114及116包括CoSi2、TiSi2、WSi2、NiSi2、MoSi2、TaSi2或PtSi。如以上所述，由于L形间隙壁108a的顶部表面露出栅极图案102的上层侧壁102a，以及两相邻栅极间有更宽广的空间，具有足够的硅化面积。因此金属硅化物层114及116可稳定的形成，且栅极硅化物层116的厚度大于如图1所示未凹陷的间隙壁厚度。As shown in FIG. 7 , after the spacers 108 a and 110 a are formed, the source or drain region 112 is implanted next to the two sides of the gate pattern 102 in the semiconductor substrate 100 to form. Afterwards, a gate silicide layer 116 and a junction metal silicide layer 114 are formed on the source or drain region 112 and the gate pattern 102 by a conventionally known method, wherein the metal silicide layers 114 and 116 include CoSi 2 , TiSi 2 , WSi 2 , NiSi 2 , MoSi 2 , TaSi 2 or PtSi. As mentioned above, since the top surface of the L-shaped spacer 108a exposes the upper sidewall 102a of the gate pattern 102 and there is a wider space between two adjacent gates, there is sufficient silicide area. Therefore, the metal silicide layers 114 and 116 can be stably formed, and the thickness of the gate silicide layer 116 is greater than the thickness of the unrecessed spacer as shown in FIG. 1 .

图8至图9显示本发明较佳实施例的另一优点。如第8图所示，在形成金属硅化物层114及116后，接着在整个基底上沉积接触蚀刻停止层118及层间介电层120。蚀刻停止层118一般为氮化硅，而层间介电层120一般为氧化物或低介电常数材料。如图9所示，以传统非等向性蚀刻蚀刻至源极或漏极区域112，形成接触窗开口122。自源极或漏极区域蚀刻移除氮化物蚀刻停止层118时，L形间隙壁108a的水平部分H若为氧化物可当作蚀刻停止层并抑制侧壁蚀刻。由上述可知，只会产生有限的底切(undercut)，且只出现在顶部间隙壁110a之下。在一较佳实施例中，底切的宽度U与水平部分H的高度Z的比值小于约0.3(U/Z)。Figures 8 to 9 show another advantage of the preferred embodiment of the present invention. As shown in FIG. 8, after forming the metal silicide layers 114 and 116, a contact etch stop layer 118 and an interlayer dielectric layer 120 are then deposited on the entire substrate. The etch stop layer 118 is typically silicon nitride, and the interlayer dielectric layer 120 is typically oxide or a low-k material. As shown in FIG. 9 , a contact opening 122 is formed by conventional anisotropic etching down to the source or drain region 112 . When the nitride etch stop layer 118 is etched away from the source or drain region, the horizontal portion H of the L-shaped spacer 108a if it is oxide can act as an etch stop layer and inhibit sidewall etching. From the above, it can be seen that only a limited undercut is generated, and only occurs under the top spacer wall 110a. In a preferred embodiment, the ratio of the width U of the undercut to the height Z of the horizontal portion H is less than about 0.3 (U/Z).

由上述可得知，本发明提供一简单且易控制间隙壁来增加金属硅化物形成的面积。由于间隙壁厚度的缩小，也使本发明的间隙壁结构可应用在下一代。此外，本发明所形成的间隙壁可降低因侧壁蚀刻所产生的底切。再者，本发明不会增加间隙壁制程的复杂度，简单来说，只需改变绝缘层的厚度比即可达成本发明。From the above, it can be seen that the present invention provides a simple and easy-to-control spacer to increase the area where the metal silicide is formed. Due to the shrinkage of the spacer thickness, the spacer structure of the present invention can also be applied to the next generation. In addition, the spacers formed by the present invention can reduce undercuts caused by sidewall etching. Furthermore, the present invention does not increase the complexity of the spacer process. Simply speaking, the present invention can be achieved only by changing the thickness ratio of the insulating layer.

虽然本发明已通过较佳实施例说明如上，但该较佳实施例并非用以限定本发明。本领域的技术人员，在不脱离本发明的精神和范围内，应有能力对该较佳实施例做出各种更改和补充，因此本发明的保护范围以权利要求书的范围为准。Although the present invention has been described above through preferred embodiments, the preferred embodiments are not intended to limit the present invention. Those skilled in the art should be able to make various changes and supplements to the preferred embodiment without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is subject to the scope of the claims.

附图中符号的简单说明如下：A brief description of the symbols in the drawings is as follows:

半导体基底～10Semiconductor substrate ~ 10

栅极电极～14Gate electrode ~ 14

氧化衬层～18Oxide lining ~ 18

L形间隙壁～18aL-shaped spacer ~ 18a

氮化硅层～20Silicon nitride layer ~ 20

氮化物间隙壁～20aNitride spacer ~ 20a

源极或漏极区域～22Source or drain region ~ 22

金属硅化物～24Metal silicide ~ 24

蚀刻停止层～26Etch stop layer ~ 26

层间介电层～28Interlayer dielectric layer ~ 28

接触窗～30Contact window ~ 30

半导体基底～100Semiconductor substrate ~ 100

栅极图案～102Gate pattern ~ 102

上层侧壁～102aUpper sidewall ~ 102a

栅极介电层～104Gate dielectric layer ~ 104

栅极电极～106Gate electrode ~ 106

第一绝缘层～108The first insulating layer ~ 108

L形间隙壁～108aL-shaped spacer ~ 108a

第二绝缘层～110Second insulating layer ~ 110

顶部间隙壁～110aTop spacer ~ 110a

源极或漏极区域～112Source or drain region ~ 112

接面金属硅化物层～114Junction metal silicide layer ~ 114

栅极硅化物层～116Gate silicide layer ~ 116

接触蚀刻停止层～118Contact etch stop layer ~ 118

层间介电层～120Interlayer dielectric layer ~ 120

接触窗开口～122Contact window opening ~ 122

Claims (15)

1.一种半导体元件，其特征在于，该半导体元件包括：1. A semiconductor element, characterized in that the semiconductor element comprises: 一导体图案；a conductor pattern; 一L形间隙壁，包括一垂直部分及一水平部分，该垂直部分置于该导体图案的较低侧壁上，露出该导体图案的上层侧壁；以及An L-shaped spacer includes a vertical portion and a horizontal portion, the vertical portion is placed on the lower sidewall of the conductor pattern, exposing the upper layer sidewall of the conductor pattern; and 一顶部间隙壁，置于该L形间隙壁上，其中该L形间隙壁的该垂直部分对于该顶部间隙壁的宽度比至少为2∶1。A top spacer is disposed on the L-shaped spacer, wherein the ratio of the vertical portion of the L-shaped spacer to the width of the top spacer is at least 2:1. 2.根据权利要求1所述的半导体元件，其特征在于，该L形间隙壁的该垂直部分对于该顶部间隙壁的宽度比为2～4∶1。2 . The semiconductor device according to claim 1 , wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is 2˜4:1. 3.根据权利要求1所述的半导体元件，其特征在于，该垂直部分的宽度对于该导体图案所露出的上层侧壁的高度之比为1～2∶1。3 . The semiconductor device according to claim 1 , wherein the ratio of the width of the vertical portion to the height of the upper sidewall exposed by the conductor pattern is 1˜2:1. 4 . 4.根据权利要求1所述的半导体元件，其特征在于，该水平部分包括该顶部间隙壁下的底切部分，其中该底切部分的宽度对于该水平部分的高度之比低于0.3。4. The semiconductor device according to claim 1, wherein the horizontal portion comprises an undercut portion under the top spacer, wherein a ratio of a width of the undercut portion to a height of the horizontal portion is lower than 0.3. 5.根据权利要求1所述的半导体元件，其特征在于，该L形间隙壁及该顶部间隙壁彼此间具有蚀刻选择性。5. The semiconductor device according to claim 1, wherein the L-shaped spacer and the top spacer have etch selectivity to each other. 6.根据权利要求1所述的半导体元件，其特征在于，该导体图案经金属硅化。6. The semiconductor device according to claim 1, wherein the conductive pattern is silicided. 7.根据权利要求1所述的半导体元件，其特征在于，该垂直部分的宽度为350～450埃，而该顶部间隙壁的宽度为100～200埃。7. The semiconductor device according to claim 1, wherein the width of the vertical portion is 350-450 angstroms, and the width of the top spacer is 100-200 angstroms. 8.根据权利要求1所述的半导体元件，其特征在于，该L形间隙壁的该垂直部分露出200～400埃的该导体图案。8 . The semiconductor device according to claim 1 , wherein the vertical portion of the L-shaped spacer exposes 200˜400 Å of the conductor pattern. 9.一种形成半导体元件的方法，其特征在于，该形成半导体元件的方法包括：9. A method for forming a semiconductor element, characterized in that the method for forming a semiconductor element comprises: 在一半导体基底上形成一导体图案；forming a conductor pattern on a semiconductor substrate; 在该导体图案及该半导体基底上顺应性的形成厚度比至少为2∶1的一第一绝缘层及一第二绝缘层；conformally forming a first insulating layer and a second insulating layer with a thickness ratio of at least 2:1 on the conductive pattern and the semiconductor substrate; 非等向性蚀刻该第二绝缘层，形成一顶部间隙壁；以及anisotropically etching the second insulating layer to form a top spacer; and 非等向性蚀刻该第一绝缘层，形成一L形间隙壁，其中该L形间隙壁的顶部表面低于该导体图案。Anisotropically etching the first insulating layer to form an L-shaped spacer, wherein the top surface of the L-shaped spacer is lower than the conductor pattern. 10.根据权利要求9所述的形成半导体元件的方法，其特征在于，L形间隙壁包括一垂直部分及一水平部分。10. The method for forming a semiconductor device according to claim 9, wherein the L-shaped spacer comprises a vertical portion and a horizontal portion. 11.根据权利要求10所述的形成半导体元件的方法，其特征在于，该L形间隙壁的该垂直部分对于该顶部间隙壁的宽度比为2～4∶1。11 . The method for forming a semiconductor device according to claim 10 , wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is 2˜4:1. 12.根据权利要求10所述的形成半导体元件的方法，其特征在于，该垂直部分的宽度对于该导体图案所露出的上层侧壁的高度之比为1～2∶1。12 . The method for forming a semiconductor device according to claim 10 , wherein the ratio of the width of the vertical portion to the height of the upper sidewall exposed by the conductor pattern is 1˜2:1. 13 . 13.根据权利要求10所述的形成半导体元件的方法，其特征在于，该水平部分为该顶部间隙壁下的底切部分，其中该底切部分的宽度对于该水平部分的高度之比低于0.3。13. The method for forming a semiconductor element according to claim 10, wherein the horizontal portion is an undercut portion under the top spacer, wherein the ratio of the width of the undercut portion to the height of the horizontal portion is lower than 0.3. 14.根据权利要求9所述的形成半导体元件的方法，其特征在于，该L形间隙壁及该顶部间隙壁彼此间具有蚀刻选择性。14. The method for forming a semiconductor device according to claim 9, wherein the L-shaped spacer and the top spacer have etch selectivity to each other. 15.根据权利要求9所述的形成半导体元件的方法，其特征在于，该导体图案经金属硅化。15. The method for forming a semiconductor device according to claim 9, wherein the conductive pattern is silicided.
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US6924178B2 (en) * 2003-12-08 2005-08-02 International Business Machines Corporation Oxide/nitride stacked in FinFET spacer process
US7259050B2 (en) * 2004-04-29 2007-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of making the same

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CN101927977B (en) * 2009-06-24 2012-05-30 鑫创科技股份有限公司 Method for fabricating a CMOS microelectromechanical system (MEMS) device
CN103378150A (en) * 2012-04-23 2013-10-30 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method for manufacturing same
CN103378150B (en) * 2012-04-23 2016-04-20 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacture method thereof

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TW200709412A (en) 2007-03-01
TWI297213B (en) 2008-05-21
US20070045754A1 (en) 2007-03-01
US7298011B2 (en) 2007-11-20

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