CN1914794A - Gate control circuit with soft start/stop function - Google Patents

Abstract

A control terminal driver circuit for a switching amplifier includes a driver for each of a pair of output power transistors responsive to a PWM information signal. The circuit operates in response to an operating state signal indicating a start up condition for the amplifier to vary the amplitude of the drive pulses for the output transistors between a zero value and a maximum value for normal operation of the amplifier over a start up interval, and to reverse the process during a shut down interval. A DC offset detector is provided to detect a DC offset at amplifier output, and an error circuit responsive to an output of the DC offset detector controls the relative amplitude of the driver outputs during at least a portion of the start up interval to substantially eliminate the DC offset. Also disclosed is a switching amplifier including a control terminal driver circuit as described above.

Description

Door control circuit with soft start/shutdown

Cross References to Related Applications

[0001] This application claims to be filed on December 18, 2003, serial number 60/530,449, titled Rights and Priority of U.S. Provisional Patent Application for a Door Drive with Soft-Start Function, the complete contents of which are incorporated herein by reference .

technical field

[0002] This invention relates to switching amplifiers and more in-depth content about such amplifiers, wherein an improved technique is used to eliminate the noise generated when the amplifier powers up or powers down. This invention is described in the context of audio amplifiers, but the invention is also valid at other frequencies in switching amplifiers, or other applications where the high and low sides of connected power transistors (e.g., MOSFETs) are used to drive power from load between transistor common nodes.

Background technique

[0003] Switching amplifiers, generally regarded as Class D amplifiers, are characterized by an output stage in the form of two transistors, usually MOSFETs, connected in series between the positive and negative terminals of the power supply. In the case of an audio amplifier, the common node between the MOSFETs is connected through a low-pass filter to drive a loudspeaker. In operation, the two output transistors act as switches, ie they are driven alternately between fully conducting and fully non-conducting states. Therefore, the voltage at the common output node alternates between positive and negative supply voltages, in addition to losses caused by the resistance (Rds) of the MOSFET.

[0004] Amplification of the audio signal is achieved by pulse width modulation (PWM) of the gate driver signal for the power transistor, and the amplified signal is restored with a low pass filter. For convenience, its conversion frequency is chosen to be high (eg, 250-300KHz) compared to the audio signal.

[0005] Except during switching transitions, the output transistor is either fully on or completely off, so the class D amplifier exhibits low power consumption and high efficiency. Efficiencies as high as 75% or even as high as 90% can be easily achieved with good circuit design. Furthermore, modern Class D amplifiers exhibit excellent audio response and distortion values comparable to other types of well-designed audio amplifiers. Class D amplifiers have been known for about 50 years, but are finding more and more use in specific applications where high heat dissipation (due to high current usage) must be avoided, such as flat-screen televisions, while also Applications such as mobile phones and other portable audio devices where battery life must be maximized for economical utility and user benefit.

1 shows a conventional Class D amplifier 10 having a half-bridge topology (topology) with two MOSFET (Metal Oxide Semiconductor Field Effect Transistor) output transistors 12 and 14 and passing through an LC filter 18. The speaker 16 is driven. The audio input signal is provided at 20 , transmitted simultaneously with a negative feedback signal from a feedback circuit 22 , connected to an input of a comparator 26 via an error amplifier 24 . The other input to comparator 26 is provided by triangular wave pulse generator 28 to provide a pulse width modulated input signal to gate driver circuit 30 for controlling the operation of MOSFETs 12 and 14 .

[0007] FIG. 2 shows the output stage of a class D amplifier 40 in a full-bridge or half-bridge (H-bridge) topology. Here, two MOSFET output transistor pairs 42a-42b and 44a-44b drive a speaker 46 through respective LC filters 48a-48b. This provides increased audio output power at the same supply voltage while allowing for more open loop operation, but at the apparent cost of more complex and expensive circuitry.

[0008] One issue in class D amplifier design is how to deal with switching noise during power up and down of the output transistor. Typically, this would be resolved by using a relay between the output loop and the speaker, but this approach would add significantly to the size and cost of the amplifier.

[0009] It has been considered optional to provide soft start and soft stop by gradually varying the gate drive of the output transistors. For example, it has been proposed to provide a circuit for gradually increasing the pulse width of the gate driver signal during the turn-on interval and gradually decreasing the pulse width of the gate driver signal during the turn-off interval. However, this approach does not work in the half-bridge topology of Figure 1 because the inherent DC offset from the switching duty cycle causes an objectionable clicking noise like switching noise ( clicking noise).

[0010] Another possibility is to gradually increase the gate voltage of the MOSFET by increasing the strength of the gate driver pulse during the start-up interval until the switching operation is completed, and turn off the amplifier by the reverse process. However, since the voltage value Vth of the MOSFETs changes in unit voltage, voltage imbalances, i.e. DC offsets may still exist, which must be addressed in both half-bridge and full-bridge layouts. Therefore, there is still a need for a suitable method to eliminate the use of relays in class D amplifiers to achieve a low-cost and more compact design.

Contents of the invention

[0011] The present invention addresses this need by providing feedback compensation for DC offsets in half-bridge and full-bridge topologies. According to the present invention, the gate driver pulse amplitude of the MOSFET output stage is raised and lowered during the turn-on and turn-off intervals to provide a special structure for soft-start and turn-off of the amplifier. In a half-bridge configuration, the DC feedback compensation loop is connected between the common node of the MOSFET or the output of the audio filter and the amplification factor control loop that controls the rate at which the gate driver pulse amplitude is increased or decreased. In a full-bridge configuration, a DC feedback loop is connected between paired MOSFET drivers to provide a differential input signal. The feedback circuit averages the output signal or behaves differently to produce an error signal indicative of the DC offset level. This error signal is used to adjust the slope of the gate driver so that the high and low sides of the MOSFET balance DC offsets during the turn-on and turn-off intervals.

[0012] The soft start/shutdown function is realized according to the present invention as part of a gate driver integrated circuit (IC), which includes pulse width modulation circuits, MOSFETs, and other auxiliary circuits, and these components are combined into a complete D class amplifier.

[0013] Therefore, it is an object of the present invention to provide an improved gate driver circuit for a pair of high and low end power transistors connected in series, which can be used in switching applications to eliminate the need for switching on and off. A relay to disconnect the amplifier's class D amplifier from the speaker.

[0014] A further object is to provide an improved gate driver circuit that can be used in both half-bridge and full-bridge topologies.

[0015] A further object is to provide an improved gate driver circuit, wherein the amplitude of the gate driver pulse increases in slope at start-up and decreases in turn-off, while a negative feedback circuit is provided to judge and compensate any Any DC offset in the speaker drive circuit.

[0016] It is an object of the present invention to provide a system that provides soft start and shutdown, and therefore does not require a relay to disconnect the amplifier from the loudspeaker during the startup and shutdown intervals, thereby eliminating the audible noise during the above intervals. Class D audio amplifier.

[0017] Another object of the present invention is to provide an amplifier that can be used in either a half-bridge or a full-bridge topology.

[0018] Another object of the present invention is to provide an amplifier that realizes the opening and closing functions by increasing the slope of the gate driver pulse amplitude in the startup interval and reducing the slope of the gate driver pulse amplitude in the closing interval, and wherein the negative feedback Used to determine and compensate for any DC offset in the speaker drive circuit.

Description of drawings

According to the following specific embodiments and accompanying drawings, other purposes and characteristics of the present invention will be obvious, wherein:

Fig. 1 represents the circuit diagram of the class D amplifier that has conventional half-bridge layout;

Fig. 2 represents the circuit diagram of the class D amplifier output stage with conventional half-bridge (H-bridge) or full-bridge layout;

Fig. 3 represents the partial circuit diagram of the D class amplifier that the present invention can realize with soft start and shut-off function;

Fig. 4 represents the structural diagram of the slope control circuit shown in Fig. 3;

[0024] FIG. 5 is a waveform diagram of MOSFET high-side and low-side and slope increase and decrease of DC offset control.

Detailed ways

[0025] Referring to FIG. 3, shown at 50, a portion of a class D amplifier in a half-bridge configuration drives a speaker 52 shown as a load _RL through an LC filter 54. The high side 56 and low side 58 of the MOSFET outputs are connected in series in their current paths, between the positive and negative poles + and -VB of the output (load) supply, and the common node 60 is connected to the filter 54 . Gating circuit 62, preferably in the form of a separate chip, includes gate drivers 64 and 66 for MOSFETs 56 and 58, and auxiliary gate driver power circuits 78 and 82 of any conventional or desired configuration.

[0026] The gate control circuit 62 also includes a feedback loop (loop) 72 and a ramp control circuit 76. Feedback loop 72 is functionally and structurally separate from audio feedback loop 22 illustrated in FIG. 1 and includes any suitable type of DC detector connected to the output of audio restoration filter 54 as shown. Thus, by way of conductor 88 as an input to ramp control circuit 76, a signal indicative of any DC offset is provided. However, it will be appreciated that the input of DC detector 74 can be selectively connected to the input of filter 54 as indicated by dashed line 90 .

[0027] Gate drivers 64 and 66 each receive an audio-modulated pulse width modulated signal at respective inputs 68 and 70 from a suitable pulse width modulation (PWM) circuit (not shown). The operation of a class D amplifier in response to a pulse width modulated audio signal is conventional and further description is omitted for brevity.

Referring to Fig. 3 and Fig. 4, ramp control circuit 76 comprises an error amplifier 86, and error amplifier receives DC error signal input from DC detector 74 at conductor 88 and from main controller such as microprocessor (not shown) Output MOSFET on-off control signal on lead 91. The output of error amplifier 86 is connected by lead 94 to level Shifter 92 which in turn provides a gate control signal to logic power MOSFET 78 associated with the high side of gate driver circuit 64. The power-on-power-off control signal on lead 91 is also provided directly as the gate control signal on lead 84 to the logic power MOSFET 82 associated with the low-side gate driver circuit 66

[0029] Referring now again to FIG. 5, the waveform on line (a) represents the power-on-power-off control signal from time T1 to time T5, assuming that the amplifier is turned off. As illustrated, this signal is in the form of a ramp up from time T1 to time T3 (ie, the start-up time interval), and then maintains a fixed level value during the normal operating time interval from time T3 to time T4. Also, if desired, when the power supplied to MOSFETs 56 and 58 is completely removed, a conventional muting time interval from system start-up at time T0 to time T1 may also be provided to allow stabilization of other circuit elements, as an additional measures to eliminate audible startup noise.

[0030] When the system is turned off, the power-on-power-off control signal on conductor 91 takes the form of a decreasing ramp in the time interval T4 to T5 shown.

[0031] The waveforms in Figures 5(b) and (c) in turn illustrate the gate driver signals for MOSFETs 56 and 58, respectively. By increasing the conductance slope of the logic power MOSFETs 64 and 66 during the turn-on time interval T1-T3, and by decreasing the conductance slope of the logic power MOSFETs 64 and 66 during the turn-off time interval T4-T5, the pulse width on leads 68 and 70 The modulating signal is effectively amplitude modulated.

[0032] In order to avoid the above-mentioned DC offset problem, the DC error compensation signal on the wire 88 is combined with the power-off slope signal in the error amplifier 86 to provide different instantaneous conductivity standards for the transistors 78 and 82. This increases the supply voltage to one of the gate drivers 64 or 66 and thus creates an asymmetry at the MOSFET output at node 60 . The different voltages on lead 84 and the output of error amplifier 86 on lead 94 are shown by line (d) of FIG. 5 . Here, it is assumed that the conductance of MOSFET 56 must increase slightly faster than MOSFET 58 . When the DC offset is reduced and finally eliminated, for example, at T2 time, the output of the DC detector 74 is zero, and the power-on-power-off slope signal value on the lead 84 and the error amplifier 86 on the lead 94 The output reaches equivalence.

[0033] In the off state, the DC offset compensation acts again as described above to influence any unavoidable asymmetry in the gate driver voltage to balance the DC offset.

[0034] While the invention has been described with respect to its particular application, many other variations and modifications, as well as other uses, will become apparent to those skilled in the art. It is therefore intended that the invention not be limited by the details described therein, but rather be given the full scope permitted by the appended claims.

Claims (21)

1. switching amplifier comprises:

Two have the output transistor of current path and control terminal separately, and current path is connected in series between the positive and negative terminals of power supply, and public output node is connected and can be connected with between the transistor that drives load;

The drive circuit that is used for control terminal;

The signal source of pulse-width modulation PWM signal is provided, and its duty ratio is expressed as information signal;

The control terminal drive circuit that is used for each output transistor;

The control terminal drive circuit, described output transistor is being opened and driven between the closing state fully to the response pulse-width signal fully to produce pulse modulation control terminal driving pulse, and transistor is opened and another is closed simultaneously;

The control terminal drive circuit, further in response to a working state signal, make amplifier elapsed boot time at interval back operate as normal at interval to change the amplitude of control terminal driving pulse between null value and maximum the start-up time of described working state signal indication amplifier;

Feedback circuit, it comprises the wave detector in response to the direct current offset at output node place; And

Error circuit, it is in response to the output of the wave detector relative amplitude with control control terminal driving pulse during arriving complete cancellation of DC offset at interval the start-up time at least a portion.

2. switching amplifier as claimed in claim 1, it further comprises the low pass filter that is connected and is suitable for being connected to load with output node.

3. switching amplifier as claimed in claim 2, wherein said wave detector is connected to output node.

4. switching amplifier as claimed in claim 2, wherein said wave detector is connected to the output of low pass filter.

5. switching amplifier as claimed in claim 1, wherein said load is a loud speaker.

6. switching amplifier as claimed in claim 1, wherein said control terminal drive circuit comprises power circuit separately, it changes the amplitude of control terminal driving pulse separately in response to the working state signal amplitude.

7. switching amplifier as claimed in claim 6, wherein said working state signal are the slope form that rises in the interval in start-up time, are the slope forms that descends in the shut-in time interval, are the values of stable state in the work of normal amplifier.

8. switching amplifier as claimed in claim 7, wherein said power circuit in response to the slope that descends the amplitude of control terminal driving pulse is reduced to null value from maximum at interval in the shut-in time.

9. during the output that switching amplifier as claimed in claim 8, wherein said error circuit further respond wave detector is arrived complete cancellation of DC offset at interval with the shut-in time at least a portion, the relative amplitude of control control terminal driving pulse.

10. switching amplifier as claimed in claim 6, wherein:

Error circuit comprises an error amplifier, and described error amplifier has first input that is connected to the wave detector output and second input that is connected to working state signal,

Working state signal is connected to one of them of the output transistor that is connected directly to power circuit, and

The output of error amplifier is connected to the power circuit of another power transistor.

11. switching amplifier as claimed in claim 10, it further comprises the translation device that error circuit is connected to power circuit.

12. switching amplifier as claimed in claim 1, wherein:

Working state signal is included as amplifier indication shut-in time part at interval; And

Drive circuit, it is worked at interval in the described shut-in time and is reduced to null value with the amplitude with the control terminal driving pulse from maximum.

13. switching amplifier as claimed in claim 12, wherein said error circuit is in response to the output of the wave detector relative amplitude with control terminal driving pulse during arriving complete cancellation of DC offset at interval at least a portion shut-in time.

14. the gate control circuit of a switching amplifier, it comprises two MOSFET output transistors, transistor has separately source electrode and the gate terminal to the leakage current path, current path is connected in series between the both positive and negative polarity of power end, and be suitable for driving the load that is connected the public output node between transistor

Wherein gate control circuit is configured and is provided with, make amplifier be operated in described MOSFET and alternately be in complete conducting state and complete cut-off state, and another MOSFET is in opposite conducting state fully with the response pulse-width signal, and its duty ratio is expressed as information signal; Described gate control circuit comprises:

The gate driver that is used for each MOSFET, its response pulse-width signal be used for generation MOSFET pulse-width modulation the door driving pulse;

Be connected slope control circuit with the actuating doors driver;

Described slope control circuit is made response to working state signal, and the entry condition of these signal indication amplifiers is to change the amplitude of width-modulation pulse sequence between the null value that runs well at interval in amplifier start-up time and the maximum; With

The direct current offset wave detector, it is suitable for being connected to detect direct current offset at public output node place; And

Error circuit, it is in response to the output of direct current offset wave detector, with the relative amplitude of the gate drive pulses that control is relevant during start-up time, a part at interval arrived complete cancellation of DC offset at least.

15. gate control circuit as claimed in claim 14, wherein said control terminal drive circuit comprises power circuit separately, this power circuit in response to the amplitude of working state signal to change the amplitude of control terminal driver pulse separately.

16. gate control circuit as claimed in claim 14, wherein said working state signal is the form of acclivity in start-up time in the interval, is the form on decline slope in the shut-in time interval, and the state value of stable state is arranged in the amplifier operate as normal.

17. gate control circuit as claimed in claim 16, wherein said gate driver circuit, which is reduced to null value with the amplitude of control terminal driving pulse from maximum in response to the slope that descends in the shut-in time interval.

18. gate control circuit as claimed in claim 15, wherein:

Described error circuit comprises an error amplifier, and this error amplifier has first input that is connected to wave detector output and is suitable for receiving second input of working state signal,

Working state signal is directly connected to the power circuit of one of them driver of MOSFET; And

The output of error amplifier is connected on the power circuit of another mosfet driver.

19. gate control circuit as claimed in claim 15 further comprises the translation device that error circuit is connected to one of power circuit.

20. switching amplifier as claimed in claim 14, wherein:

Working state signal comprises the shut-in time part at interval of indicating amplifier; And

Gate driver circuit, which can be worked in the shut-in time interval, is reduced to null value with the amplitude with the control terminal driving pulse from maximum.

21. switching amplifier as claimed in claim 20, wherein said error circuit at least a portion shut-in time at interval in further in response to the output of wave detector, with the relative amplitude of control control terminal driving pulse.

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