CN1968021B - A delay-locked loop, voltage-controlled delay line and delay unit - Google Patents

Abstract

The present invention is applicable to the communication field, and provides a delay-locked loop, a voltage-controlled delay line and a delay unit, including a bias generator and a voltage-controlled delay line. The bias generator generates a bias voltage and inputs it to the voltage-controlled The delay line is used to control the voltage-controlled delay line to generate a delay. The voltage-controlled delay line includes one or more cascaded delay units, and the delay unit includes a symmetrical active load delay unit. The first control terminal, the differential signal output selection path and the second control terminal, and only one of the first control terminal and the second control terminal can be turned on or off at the same time. The present invention adjusts the number of delay units in the voltage-controlled delay line by controlling the on-off of the delay unit, thereby realizing the flexible configuration of the delay output of the voltage-controlled delay line.

Description

A delay-locked loop, voltage-controlled delay line and delay unit

technical field

The invention belongs to the communication field, and in particular relates to a delay-locked loop, a voltage-controlled delay line and a delay unit.

Background technique

As the amount of data transmission increases, the requirement for a synchronous clock frequency becomes higher and higher. In order to transmit more data at a lower clock frequency, the design begins to use the double edge (rising edge and falling edge) of the clock to collect data, which can be compared with the single edge (rising or falling edge) at the same clock frequency ) way to transmit twice as much data. At the data receiving end, in order to recover the data accurately, the clock needs to be delayed by a certain amount of time (for example, 1/4 cycle), and the duty cycle of the clock basically does not change.

Figure 1 shows the structure of a typical delay-locked loop (Delay Locked Loop, DLL), including a phase detector 101, a charge pump 102, a loop filter 103, a bias generator (Bias Generator) 104 and a voltage-controlled delay Line (Voltage Controlled Delay Line, VCDL) 105 . The phase detector 101 judges the phases of the source clock signal SCLK and the delayed clock signal FCLK, and outputs corresponding control signals UP and DN for the charge pump 102 , which are converted into current by the charge pump 102 . The charge pump 102 charges or discharges the loop filter 103 under the control of the control signals UP and DN to obtain the control voltage V _ctr of the voltage-controlled delay line 105, and the bias generator 104 generates bias voltages V _BP and V _BN Input to the voltage controlled delay line 105. The bias voltages V _BP and V _BN generated by the bias generator 104 control the voltage-controlled delay line 105 to generate a delay, so that the clock duty cycle does not change substantially.

FIG. 2 shows the structure of the bias generator 104, which controls the voltage-controlled delay line 105 to generate a corresponding delay by changing the bias current and then changing the bias voltage.

The voltage-controlled delay line 105 adopts a symmetrical active load delay cell (Delay Cell) with a differential structure as shown in FIG. 3 , uses an N-channel MOS transistor as an input transistor, and a P-channel MOS transistor as a load transistor. The power supply voltage VDD is connected to the sources of MOS transistors T6, T7, T8, and T9, and the drain of T6 is connected to the drain and gate of T7 to form VCR 1 (Voltage Controlled Resistor, voltage-controlled resistor), and the corresponding MOS transistor T8 Form VCR2 with T9, VCR1 and VCR2 form a symmetrical active load, and the bias voltage V _BP is connected to the gates of T7 and T8. The differential signals VINPA and VINNA are input to the gates of the input differential pair transistors T2 and T3, the gates of T2 and T3 are connected to the output terminals VOUTN and VOUTP, and the differential signals amplified by the MOS transistors T2 and T3 are output. The drains of T2 and T3 are respectively connected to the drains of T7 and T8, and the source is connected to the drain of the P-channel MOS transistor T1. T1 provides tail current, the source of T1 is grounded to GND, and the bias voltage V _BN is connected to the gate of T1.

In the application, it is necessary to configure the delay of the delay-locked loop according to the actual situation, so that the voltage-controlled delay line can output different delays. In the existing voltage-controlled delay line, due to the fixed delay unit, the delay configuration cannot be realized. , it is difficult to meet the needs of practical applications.

Contents of the invention

The purpose of the present invention is to provide a delay locked loop, aiming to solve the problem that in the existing phase locked loop, the delay configuration cannot be realized because the delay unit of the voltage-controlled delay line is fixed.

Another object of the present invention is to provide a voltage-controlled delay line.

Another object of the present invention is to provide a delay unit.

The present invention is achieved in this way, a delay-locked loop, including a bias generator and a voltage-controlled delay line, the bias generator generates a bias voltage input to the voltage-controlled delay line, and controls the voltage-controlled delay line to generate Delay, the voltage-controlled delay line includes one or more cascaded delay units, the delay unit includes a symmetrical active load delay unit, and the delay unit further includes:

The first control terminal is connected in series in the symmetrical active load delay unit, and performs on-off control on the differential signal input and output paths of the symmetrical active load delay unit;

The differential signal output selection path is connected to the output terminal of the symmetrical active load delay unit, receives the differential signal, and outputs the amplified differential signal; and

The second control terminal is connected in series in the differential signal output selection path, and performs on-off control on the differential signal input and output paths of the differential signal output selection path;

Only one of the first control terminal and the second control terminal can be turned on or off at the same time.

The delay-locked loop further includes a slave loop that receives an input clock signal and outputs a delayed clock signal under the control of the same bias voltage of the bias generator, and the slave loop includes one or more An independent voltage-controlled delay line, the voltage-controlled delay line includes one or more cascaded delay units.

The voltage-controlled delay line of the delay-locked loop is consistent with the load of the voltage-controlled delay line of the slave loop.

The opening and closing of the first control terminal and the second control terminal are controlled by coding.

The bias generator is a Replica circuit.

The input transistor of the delay unit is an N-channel MOS transistor, and the load transistor is a P-channel MOS transistor, or the input transistor is a P-channel MOS transistor, and the load transistor is an N-channel MOS transistor.

A voltage-controlled delay line comprising one or more cascaded delay units, the delay unit comprising a symmetrical active load delay unit, the delay unit further comprising:

The first control terminal is connected in series in the symmetrical active load delay unit, and performs on-off control on the differential signal input and output paths of the symmetrical active load delay unit;

The differential signal output selection path is connected to the output terminal of the symmetrical active load delay unit, receives the differential signal, and outputs the amplified differential signal; and

The second control terminal is connected in series in the differential signal output selection path, and performs on-off control on the differential signal input and output paths of the differential signal output selection path;

Only one of the first control terminal and the second control terminal can be turned on or off at the same time.

The input transistor of the delay unit is an N-channel MOS transistor, and the load transistor is a P-channel MOS transistor, or the input transistor is a P-channel MOS transistor, and the load transistor is an N-channel MOS transistor.

A kind of delay unit, described delay unit comprises a symmetrical active load delay unit, and described delay unit further comprises:

The first control terminal is connected in series in the symmetrical active load delay unit, and performs on-off control on the differential signal input and output paths of the symmetrical active load delay unit;

The differential signal output selection path is connected to the output terminal of the symmetrical active load delay unit, receives the differential signal, and outputs the amplified differential signal; and

The second control terminal is connected in series in the differential signal output selection path, and performs on-off control on the differential signal input and output paths of the differential signal output selection path;

Only one of the first control terminal and the second control terminal can be turned on or off at the same time.

The input transistor of the delay unit is an N-channel MOS transistor, and the load transistor is a P-channel MOS transistor, or the input transistor is a P-channel MOS transistor, and the load transistor is an N-channel MOS transistor.

The voltage-controlled delay line in the present invention is realized by a delay unit with a gating function, and by controlling the on-off of the delay unit to adjust the number of delay units in the voltage-controlled delay line, the delay output of the voltage-controlled delay line is realized. Flexible configuration. Through the master-slave loop structure, multiple clock paths work in parallel. At the same time, the bias generator adopts a Replica circuit, which avoids the nonlinear control of the delay, and makes the step size of the clock frequency change uniform.

Description of drawings

Fig. 1 is a typical structural diagram of a delay-locked loop in the prior art;

Fig. 2 is a circuit structure diagram of a bias generator in the prior art;

Fig. 3 is a circuit structure diagram of a voltage-controlled delay line in the prior art;

Fig. 4 is the circuit structure diagram of the delay unit provided in one embodiment of the present invention;

Fig. 5 is a circuit structural diagram of a delay unit provided in another embodiment of the present invention;

Fig. 6 is an example circuit structure diagram of a voltage-controlled delay line in the present invention;

Fig. 7 is the structural diagram of the delay locked loop adopting master-slave loop structure among the present invention;

Fig. 8 is the example circuit structural diagram that adopts from loop voltage control delay line among the present invention;

FIG. 9 is a circuit structure diagram of a bias generator in the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In the present invention, the voltage-controlled delay line is implemented by a delay unit with a gating function, and the number of delay units in the voltage-controlled delay line is adjusted by controlling the on-off of the selected path in the delay unit, thereby realizing the control of the voltage-controlled delay line. Flexible configuration of delayed output.

Figure 4 shows the structure of the delay unit provided by the present invention, the input differential pair transistors T4 and T5 of the P-channel MOS transistors T4 and T5 connected in series to the symmetrical active load delay unit form the first control terminal, and control the input symmetrical active load On-off of the differential signals VINPA, VINNA of the delay unit to the output terminals VOUTP, VOUTN. The drains of T4 and T5 are respectively connected to the drains of T7 and T8 and the output terminals VOUTP and VOUTN, and the sources are respectively connected to the drains of T2 and T3. The on-off control signal SELA is connected to the gates of T4 and T5.

T1'~T5' constitute another differential signal output selection channel corresponding to T1~T5, and the input differential pair transistors T4' and T5' constitute the second control terminal, which controls the communication of the input differential signal VINPB, VINNB to the output terminals VOUTP, VOUTN broken. The drains of T4' and T5' are respectively connected to the output terminals VOUTN and VOUTP, and the sources are respectively connected to the drains of T2' and T3'. The on-off control signal SELB is connected to the gates of T4' and T5'. The differential signals VINPB and VINNB are input to the gates of the input differential pair transistors T2' and T3', amplified by the input differential pair transistors T2' and T3' and then output. The drains of T2' and T3' are respectively connected to the sources of T4' and T5', and the source is connected to the drain of T1'. T1' provides tail current, the source of T1' is grounded to GND, and the bias voltage V _BN is connected to the gate of T1'.

Only one of SELA and SELB can be logic high level "1" (the same voltage as the power supply VDD) at the same time. When SELA is logic high level and SELB is logic low level "0" (the same voltage as ground GND), the input differential signals VINPA, VINNA are transmitted to the output terminals VOUTP, VOUTN, and the input differential signals VINPB, VINNB are closed due to SELB It is shielded when it is off, and vice versa, so that the delay unit has the function of 2 selection 1.

In Figure 4, the N-channel MOS tube is used as the input tube, and the P-channel MOS tube is used as the load tube, or the P-channel MOS tube is used as the input tube, and the N-channel MOS tube is used as the load tube, as shown in Figure 5, to realize The principle is the same as above and will not be repeated here.

Fig. 6 shows an example structure of the voltage-controlled delay line 105, which adopts 24 stages of delay units to be cascaded, and through corresponding on-off control of S1-S24, different delays can be output as required. For example, when S1 and S25 are high level and S2 is low level, 2-level delay can be output; when S1, S2, S26 is high level, and S25 is low level, 3-level delay can be output, etc. Controlled by coding.

In order to realize parallel operation of multiple clock channels, in one embodiment of the present invention, the delay-locked loop adopts a master-slave loop structure, as shown in FIG. 7 . The slave loop 12 is composed of one or more voltage delay control delay lines 12.1, 12.2...12.n controlled by the same control voltage of the master loop 11, wherein, CLK1...CLKN is the same as The input clock signal of the same frequency as the main loop 11 source clock SCLK, CKO1...CKON is the corresponding delayed clock signal, ADJ1...ADJN is to adjust the slave loop voltage control delay line The control terminal for the number of delay units.

If the number of delay units of the voltage-controlled delay line in the main loop 11 is N _m , and the number of delay units of each voltage-controlled delay line in the slave loop 12 is N _s , the voltage control of the main loop 11 at this time The delay time of each delay unit in the delay line is T/N _m , because the delay unit in each voltage-controlled delay line in the slave loop 12 and the delay unit in the voltage-controlled delay line of the master loop 11 are in The circuit structure, load, and size are all the same, so the delay time of each voltage-controlled delay line in the slave loop is (T/N _m )×N _s , and the slave loop 12 can be changed by changing the value of N _s Delay for each voltage-controlled delay line. Each voltage-controlled delay line in the slave loop 12 is independent of each other, and the delay can be adjusted separately. The adjustment of the delay is realized by changing the number of delay units. The step size is uniform and the delay can be configured linearly. At the same time, it can also ensure that the load of the master-slave voltage-controlled delay line remains strictly uniform, and avoid inconsistent delays between the master loop and the slave loop.

For example, when the main loop voltage-controlled delay line 105 and the slave loop voltage-controlled delay line adopt the structures shown in Fig. 6 and Fig. 8 respectively, when the control terminal S3 of the delay unit DC3 is at a high level, the control terminal S26 of the DC25 When it is also at high level, VINPA and VINNA of DC3 and VINPA and VINNA of DC25 are the loads of DC2, and this type of load is load one. When the control terminal S2 of the delay unit DC2 is at high level and the control terminal S25 of DC25 is at low level, the delay unit DC1 has no signal extracted, VINPA, VINNA of DC2 and VINPB and VINNB of DC25 are the loads of DC1. The type of load is load two. In the voltage-controlled delay line 105 of the entire main loop 11, there are 8 delay units for load one and 16 delay units for load two. In this way, the ratio of the number of delay units with load one to the number of delay units with load two in the master loop 11 is 8:16. To satisfy the strict unity of the voltage-controlled delay line load of the master-slave loop, it is necessary to make each slave loop The ratio of the number of delay units with load one to the number of delay units with load two in a voltage-controlled delay line is the same as that of the main loop 11.

In the 3-level delay, the control terminal status of each delay unit in the loop voltage-controlled delay line is shown in the following table:

console name S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 Control terminal level high high Low Low Low high Low Low Low high Low

Then the clock passes through DC1, DC6, and DC8 to obtain a three-level delay. The delay unit with load one is DC1, and the delay unit with load two is DC6 and DC8, and the ratio is 1:2.

In the 6-level delay, the control terminal status of each delay unit in the loop voltage-controlled delay line is shown in the following table:

console name S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 Control terminal level high high high high high high Low Low high Low high

The clock gets 6 levels of delay through DC1, DC2, DC3, DC4, DC7, and DC8. The delay units with load one are DC1 and DC4, the delay units with load two are DC2, DC3, DC7 and DC8, and the ratio is 2:4.

Therefore, in the master-slave loop, the ratio of the delay unit with load one and the delay unit with load two is completely equal (1:2=2:4=8:16), and the loads remain strictly consistent, which is well realized The uniformity of the master-slave loop delay step is achieved. The purpose of coding the control terminal SEL is to keep the ratio of the number of delay units of two different loads constant within the range of variable delay, so as to ensure the uniformity of the delay step. Since the delay control of the voltage-controlled delay line 105 by the bias generator 104 adopts the transition from the bias current to the bias voltage and then to the delay control, there is a non-linear problem from the control voltage to the delay, which makes the step size of the clock frequency change uneven unanimous. As an embodiment of the present invention, the bias generator 104 is implemented using a Replica circuit, which is a general term for a class of circuits. For the relevant content of the Replica circuit, refer to IEEE VOL.27, No.11, Nov, 1992, 1599, Ian A . Young, Jeffrey K. Greason, and Keng L. Wong, "APLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors".

As shown in FIG. 9, T1, T2, T3, T11, T12, T13 and T14 are N-channel MOS transistors, and T4-T10 are P-channel MOS transistors. The power supply voltage VDD is connected to the sources of T1, T11, T12, T13 and T14, the drain of T1 is connected to the sources of T1 and T2, and the bias voltage VB1 is connected to the gate of the drain of T1. The voltage at point A is connected to the gate of T2, and the drain of T2 is connected to the drain and gate of the P-channel MOS transistor. The drain of T3 is connected to the drain of T5 and the gate of T6. The sources of T4, T5, and T6 are grounded. The reference voltage V _ref is connected to the gate of T3. The gate of T4 is connected to the gate of T5. The drain of T6 is connected to the source and gate of T7 and the source of T8, and the power supply voltage VDD is connected to the gate of T8. The source of T9 is connected to the drain of T7, the gate is connected to the power supply voltage VDD, and the drain is connected to the drain of T13 and the drain and gate of T14. The gate of T10 is connected to the gate of T9, the drain is connected to the drain of T11 and the drain and gate of T12. The gates of T12 and T13 are connected.

T1-T5 form an error amplifier, compare the voltage at point A with the reference voltage V _ref , feed back the comparison result to T6, and control the tail current of T6, so that the voltage at point A is equal to V _ref . The circuit formed by T6～T14 is basically the same as the circuit formed by the delay unit. When the circuit is working, only one side circuit in the symmetrical path of T7, T9, T13, T14 or T8, T10, T11, T12 is required to work. The present invention will T7 is connected in the form of turning off, that is, the channels of T7, T9, T13, and T14 are turned off, and T8, T10, T11, and T12 are turned on.

For example, when V _ctr (V _BP ) becomes smaller, the VCR composed of T11 and T12 becomes smaller, resulting in a smaller voltage drop across the VCR, and an increase in the voltage at point A, which increases V _BN through the error amplifier and increases the tail current of T6. , so that the voltage difference on the VCR becomes larger, so that the voltage at point A decreases; when the voltage at point A is equal to V _ref , the voltage at point A remains unchanged.

Conversely, when V _BP becomes larger, the VCR composed of T11 and T12 becomes larger, causing the voltage difference on VCR to increase, and the voltage at point A decreases. The error amplifier makes V _BN lower, and the tail current of T6 becomes smaller, so that the VCR The voltage difference becomes smaller, so that the voltage at point A increases; when the voltage at point A is equal to V _ref , the voltage at point A remains unchanged.

The delay of the delay unit is proportional to the size of VCR and inversely proportional to the tail current of T6. When V _BP becomes smaller, VCR becomes smaller, and the tail current of T6 becomes larger, so the delay is smaller than that of single V _BP control. Conversely, when V _BP becomes larger, VCR becomes larger, and T6 tail current becomes smaller, so the delay is larger than that under single V _BP control, thus the range of delay can be increased.

Since the bias generator does not use the conversion from the control voltage V _ctr → current → bias voltages V _BP and V _BN , the problem of delay nonlinearity caused by the nonlinearity of V→I→V is eliminated, and the clock frequency change step size Keep it even and consistent.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (10)

1. delay phase-locked loop, comprise biasing generator and voltage controlled delay line, described biasing generator produces bias voltage and is input to voltage controlled delay line, control described voltage controlled delay line and produce time-delay, described voltage controlled delay line comprises the delay unit of one or more cascade, described delay unit comprises a symmetrical active load delay unit, it is characterized in that described delay unit further comprises:

First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;

Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And

Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;

Described first control end and second control end can only have simultaneously one open-minded.

2. delay phase-locked loop as claimed in claim 1, it is characterized in that, described delay phase-locked loop further comprises one from loop, receive the clock signal of input, clock signal after output time-delay under the bias voltage control of described biasing generator, describedly comprise one or more independently voltage controlled delay line from loop, described voltage controlled delay line from loop comprises the delay unit of one or more cascade.

3. delay phase-locked loop as claimed in claim 2 is characterized in that, the voltage controlled delay line of described delay phase-locked loop is consistent with the load of described voltage controlled delay line from loop.

4. delay phase-locked loop as claimed in claim 1 is characterized in that, opening and turn-off by coding of described first control end and second control end controlled.

5. as the described delay phase-locked loop of the arbitrary claim of claim 1 to 4, it is characterized in that described biasing generator is the Replica circuit.

6. as the described delay phase-locked loop of the arbitrary claim of claim 1 to 4, it is characterized in that the input pipe of described delay unit is the N-channel MOS pipe, the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.

7. voltage controlled delay line comprises the delay unit of one or more cascade, and described delay unit comprises a symmetrical active load delay unit, it is characterized in that described delay unit further comprises:

First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;

Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And

Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;

Described first control end and second control end can only have simultaneously one open-minded.

8. voltage controlled delay line as claimed in claim 7 is characterized in that, the input pipe of described delay unit is the N-channel MOS pipe, and the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.

9. delay unit, described delay unit comprises a symmetrical active load delay unit, it is characterized in that described delay unit further comprises:

First control end is serially connected in the described symmetrical active load delay unit, and the differential signal input and output path of described symmetrical active load delay unit is carried out break-make control;

Differential signal output selection path is connected with the output of described symmetrical active load delay unit, receives differential signal, the differential signal after output is amplified; And

Second control end is serially connected in the described differential signal output selection path, and the differential signal input and output path of described differential signal being exported the selection path carries out break-make control;

Described first control end and second control end can only have simultaneously one open-minded.

10. delay unit as claimed in claim 9 is characterized in that, the input pipe of described delay unit is the N-channel MOS pipe, and the load pipe is the P channel MOS tube, and perhaps input pipe is the P channel MOS tube, and the load pipe is the N-channel MOS pipe.

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