CN1845459B - Voltage level shifter - Google Patents

Abstract

A voltage level shifter made of the same type of thin film transistors includes two input terminals, two power supply terminals, six thin film transistors and an output terminal. Another voltage level shifter made of the same type of thin film transistors includes two input terminals, an output terminal, two power supply terminals, two input units, a first thin film transistor, a failure unit, a feedback unit and a second thin film transistor.

Description

voltage level shifter

technical field

The present invention relates to a voltage level shifter, in particular to a voltage level shifter implemented by a same-type thin film transistor.

Background technique

In recent years, Thin-Film Transistor Liquid Crystal Display (TFT LCD) has been widely used in electronic products such as personal computer monitors, televisions, mobile phones, and digital cameras. When the thin film transistor array is in operation, there is a clock signal to control the scan of the thin film transistor array to display pixels in sequence. Since the clock signal for scanning requires a relatively high voltage level, the low voltage clock signal with a general logic level must first pass through A peripheral driving circuit (that is, a voltage level shifter) converts the voltage level and then supplies it to the thin film transistor array.

As shown in FIG. 1 , it shows a known circuit diagram of a voltage level shifter, which is composed of NMOS thin film transistors 101 , 103 and PMOS thin film transistors 105 , 107 . Since both NMOS and PMOS thin film transistors are included, a multi-doped MOS process is usually used during fabrication. When the voltage level shifter circuit is integrated on the display TFT substrate, it requires more processing steps, resulting in an increase in the production cost of the liquid crystal display.

To sum up, if the voltage level shifter is made with the known technology, there will be a problem of high production cost. Therefore, a voltage level shifter that uses the same type of thin film transistor to reduce the production cost is an important technology in this technical field. urgent issues to be resolved.

Contents of the invention

An object of the present invention is to provide a voltage level shifter made of the same type thin film transistor, comprising a first input terminal, a second input terminal, a first power supply terminal, a second power supply terminal, a A first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor and an output terminal; the first input terminal is used to input a first input signal; the second input is used to input a second input signal; the first thin film transistor includes a gate, a source and a drain, wherein the drain of the first thin film transistor is coupled to the first input terminal and the first thin film The gate of the transistor; the second thin film transistor includes a gate, a source and a drain, wherein the source of the second thin film transistor is coupled to the first power supply terminal, and the gate of the second thin film transistor is coupled to the first The source of a thin film transistor; the third thin film transistor includes a gate, a source and a drain, wherein the source of the third thin film transistor is coupled to the drain of the second thin film transistor, and the drain of the third thin film transistor Coupled to the second power supply terminal; the fourth thin film transistor includes a gate, a source and a drain, wherein the source of the fourth thin film transistor is coupled to the gate of the second thin film transistor, and the fourth thin film transistor The drain is coupled to the second power supply terminal, the gate of the fourth thin film transistor is coupled to the gate of the third thin film transistor; the fifth thin film transistor includes a gate, a source and a drain, wherein the fifth thin film The gate and drain of the transistor are coupled to the second input terminal, the source of the fifth thin film transistor is coupled to the gate of the fourth thin film transistor; the sixth thin film transistor includes a gate, a source and a drain, Wherein the gate of the sixth thin film transistor is coupled to the first input terminal, the drain of the sixth thin film transistor is coupled to the second power supply terminal, and the source of the sixth thin film transistor is coupled to the source of the fifth thin film transistor; The output end is coupled to the source of the third thin film transistor.

Another object of the present invention is to provide another voltage level shifter made of the same type thin film transistor, the voltage level shifter includes a first input terminal, a second input terminal, an output terminal, a first A power supply terminal, a second power supply terminal, a first input unit, a second input unit, a first thin film transistor, a failure unit, a feedback unit and a second thin film transistor; the first input unit passes through the first The input terminal receives a first input signal and outputs a first switching control signal; the second input unit receives a second input signal through the second input terminal and outputs a second switching control signal; the first thin film transistor includes a gate, A source and a drain, wherein the gate of the first thin film transistor is coupled to the first input unit and receives the first switching control signal, the drain of the first thin film transistor is coupled to the output terminal, and the source of the first thin film transistor The pole is coupled to the first power supply end; the failure unit is coupled to the first input unit, the second input unit, the first thin film transistor and the second power supply end, and is used to control the failure of the first thin film transistor; the feedback unit according to the output An output signal at the end transmits a feedback signal to the first input unit and the failure unit; the second thin film transistor includes a gate, a source and a drain, wherein the gate of the second thin film transistor is coupled to the second input unit and After receiving the second switching control signal, the drain of the second thin film transistor is coupled to the second power supply end, and the source of the second thin film transistor is coupled to the output end.

After referring to the accompanying drawings and the implementation methods described later, those skilled in the art can understand other objectives of the present invention, as well as the technical means and implementation aspects of the present invention.

Description of drawings

Fig. 1 shows a known circuit diagram of a voltage level shifter;

Figure 2A shows a circuit diagram of a first embodiment of the present invention;

FIG. 2B to FIG. 2D show input and output terminal waveform diagrams of the first embodiment of the present invention;

Fig. 3 A shows the circuit diagram of the second embodiment of the present invention;

3B to 3D show input and output terminal waveform diagrams of the second embodiment of the present invention;

Figure 4A shows a circuit diagram of a third embodiment of the present invention;

4B to 4D show the input and output terminal waveform diagrams of the third embodiment of the present invention;

Figure 5A shows a circuit diagram of a fourth embodiment of the present invention; and

5B to 5D show the input and output terminal waveform diagrams of the fourth embodiment of the present invention.

Description of reference symbols

31: The first input unit 33: The second input unit

35: Failure unit 37: Feedback unit

101, 103: NMOS thin film transistors 105, 107: PMOS thin film transistors

201, 301: the first thin film transistor 203, 303: the second thin film transistor

205, 305: the third thin film transistor 207, 307: the fourth thin film transistor

209, 309: fifth thin film transistor 211, 311: sixth thin film transistor

300: The first switching control signal 302: The second switching control signal

304, 306: Feedback signal 313: The seventh thin film transistor

315: Eighth thin film transistor 317: Ninth thin film transistor

319: Tenth thin film transistor 401: Eleventh thin film transistor

403: Twelfth thin film transistor 405: Thirteenth thin film transistor

501: The fourteenth thin film transistor 503: The fifteenth thin film transistor

505: The sixteenth thin film transistor 507: The seventeenth thin film transistor

509: The eighteenth thin film transistor 511: The nineteenth thin film transistor

513: The 20th thin film transistor 515: The 21st thin film transistor

201a, 301a: the drain of the first thin film transistor

201b, 301b: the source of the first thin film transistor

201c, 301c: the gate of the first thin film transistor

203a, 303a: the drain of the second thin film transistor

203b, 303b: the source of the second thin film transistor

203c, 303c: the gate of the second thin film transistor

205a, 305a: the drain of the third thin film transistor

205b, 305b: the source of the third thin film transistor

205c, 305c: the gate of the third thin film transistor

207a, 307a: the drain of the fourth thin film transistor

207b, 307b: the source of the fourth thin film transistor

207c, 307c: the gate of the fourth thin film transistor

209a, 309a: the drain of the fifth thin film transistor

209b, 309b: the source of the fifth thin film transistor

209c, 309c: the gate of the fifth thin film transistor

211a, 311a: the drain of the sixth thin film transistor

211b, 311b: the source of the sixth thin film transistor

211c, 311c: the gate of the sixth thin film transistor

313a: the drain of the seventh thin film transistor 313b: the source of the seventh thin film transistor

313c: the gate of the seventh thin film transistor 315a: the drain of the eighth thin film transistor

315b: the source of the eighth thin film transistor 315c: the gate of the eighth thin film transistor

317a: the drain of the ninth thin film transistor 317b: the source of the ninth thin film transistor

317c: the gate of the ninth thin film transistor 319a: the drain of the tenth thin film transistor

319b: the source of the tenth thin film transistor 319c: the gate of the tenth thin film transistor

401a: the drain of the eleventh thin film transistor

401b: the source of the eleventh thin film transistor

401c: the gate of the eleventh thin film transistor

403a: the drain of the twelfth thin film transistor

403b: the source of the twelfth thin film transistor

403c: the gate of the twelfth thin film transistor

405a: the drain of the thirteenth thin film transistor

405b: the source of the thirteenth thin film transistor

405c: the gate of the thirteenth thin film transistor

501a: the drain of the fourteenth thin film transistor

501b: the source of the fourteenth thin film transistor

501c: the gate of the fourteenth thin film transistor

503a: the drain of the fifteenth thin film transistor

503b: the source of the fifteenth thin film transistor

503c: the gate of the fifteenth thin film transistor

505a: the drain of the sixteenth thin film transistor

505b: the source of the sixteenth thin film transistor

505c: the gate of the sixteenth thin film transistor

507a: the drain of the seventeenth thin film transistor

507b: the source of the seventeenth thin film transistor

507c: Gate of the seventeenth thin film transistor

509a: the drain of the eighteenth thin film transistor

509b: the source of the eighteenth thin film transistor

509c: the gate of the eighteenth thin film transistor

511a: the drain of the nineteenth thin film transistor

511b: the source of the nineteenth thin film transistor

511c: gate of the nineteenth thin film transistor

513a: the drain of the twentieth thin film transistor

513b: source of the twentieth thin film transistor

513c: Gate of the twentieth thin film transistor

515a: the drain of the twenty-first thin film transistor

515b: the source of the twenty-first thin film transistor

515c: the gate of the twenty-first thin film transistor

Vin: the first input terminal Vxin: the second input terminal

Vout: output terminal V _DD : first power supply terminal

V _SS : the second power supply terminal

Detailed ways

FIG. 2A shows the first embodiment of the present invention, which includes a first input terminal Vin, a second input terminal Vxin, a first power supply terminal V _DD , a second power supply terminal V _SS , a first TFT 201 , a second TFT 203 , a third TFT 205 , a fourth TFT 207 , a fifth TFT 209 , a sixth TFT 211 and an output terminal Vout. The first input terminal Vin is used to input a first input signal, and the second input terminal Vxin is used to input a second input signal, wherein the first input signal and the second input signal are opposite phases of each other. The output terminal Vout outputs an output signal. The first thin film transistor 201, the second thin film transistor 203, the third thin film transistor 205, the fourth thin film transistor 207, the fifth thin film transistor 209, and the sixth thin film transistor 211 are thin film transistors of the same type. Transistors are exemplified, however, N-type thin film transistors may also be used. Furthermore, the material of the thin film transistor (such as: amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon or a mixture of the above materials) and the type of thin film transistor (such as: bottom gate (gate) type, top gate (gate) type or similar type) can also be used. The connection relationship of each component is described as follows.

The drain 201a of the first thin film transistor 201 is coupled to the first input terminal Vin, the gate 201c of the first thin film transistor 201 is also coupled to the first input terminal Vin, and the source 203b of the second thin film transistor 203 is coupled to the first input terminal Vin. A power supply terminal V _DD , the gate 203c of the second TFT 203 is coupled to the source 201b of the first TFT 201 , the source 205b of the third TFT 205 is coupled to the drain 203a of the second TFT 203 and the output terminal Vout, the drain 205a of the third thin film transistor 205 is coupled to the second power supply terminal V _SS , the source 207b of the fourth thin film transistor 207 is coupled to the gate 203c of the second thin film transistor 203, the fourth thin film transistor The gate 207c of the transistor 207 is coupled to the gate 205c of the third TFT 205, the drain 207a of the fourth TFT 207 is coupled to the second power supply terminal V _SS , the gate 209c and the drain of the fifth TFT 209 The pole 209a is coupled to the second input terminal Vxin, the source 209b of the fifth TFT 209 is coupled to the gate 207c of the fourth TFT 207, and the gate 211c of the sixth TFT 211 is coupled to the first input terminal Vin , the drain 211a of the sixth thin film transistor 211 is coupled to the second power supply terminal V _SS , the source 211b of the sixth thin film transistor 211 is coupled to the source 209b of the fifth thin film transistor 209 , and the output terminal Vout is coupled to the first The source 205b of the three thin film transistors 205 .

2B to 2D are waveform diagrams of the first input terminal Vin and output terminal Vout voltage versus time under three different critical voltages of the thin film transistor in the first embodiment, wherein the first critical voltage is about -1V (corresponding to FIG. 2B ), the second critical voltage is about -2.5V (corresponding to FIG. 2C ), and the third critical voltage is about -4V (corresponding to FIG. 2D ). In addition, in Fig. 2B to Fig. 2D, the first power supply terminal V _DD is set to about -6V, the second power supply terminal V _SS is set to about 9V, and a PMOS with an electron mobility (ElectronMobility) of 60cm ² /Vsec is used. Waveforms obtained in an experimental environment with thin film transistors and an output capacitive load of 20pF.

It can be seen from FIG. 2B that when the critical voltage of the thin film transistor is -1V, the output signal waveform of the output terminal Vout is still far from the voltage of the first power supply terminal V _DD in the low-level output part, but in the high-level output part. It is quite close to the voltage of the second power supply terminal V _SS . It can be seen from FIG. 2C that when the threshold voltage of the thin film transistor is -2.5V, the output waveforms at both high and low levels are ideal. It can be seen from Figure 2D that when the critical voltage of the thin film transistor is -4V, although the output signal waveform of the output terminal Vout can reach the voltage of the low-level first power supply terminal V _DD , it takes nearly 20 μs, and the output terminal Vout The voltage rise part also takes a long time.

FIG. 3A shows the second embodiment of the present invention, which includes a first input terminal Vin, a second input terminal Vxin, a first power supply terminal V _DD , a second power supply terminal V _SS , and an output terminal. Vout, a first input unit 31, a second input unit 33, a first thin film transistor 301, a failure unit 35, a feedback unit 37 and a second thin film transistor 303, wherein the first input terminal Vin is used to input a The first input signal, the second input terminal Vxin is used to input a second input signal, and the output terminal Vout outputs an output signal. The first input signal and the second input signal are opposite to each other, and the output signal of the output terminal Vout is in phase with the first input signal. Its connection relationship is described as follows.

The first input unit 31 receives the first input signal through the first input terminal Vin, and outputs a first switching control signal 300, and the second input unit 33 is coupled to the second power supply terminal V _SS for receiving the first input signal through the second input terminal. Vxin receives the second input signal and outputs a second switching control signal 302. The gate 301c of the first thin film transistor 301 is coupled to the first input unit 31 for receiving the first control signal 300. The drain of the first thin film transistor 301 The pole 301a is coupled to the output terminal Vout, the source 301b of the first thin film transistor 301 is coupled to the first power supply terminal V _DD , and the failure unit 35 is coupled to the first input unit 31 and the second input unit 33 (receiving the second control signal 302), the first thin film transistor 301 and the second power supply terminal V _SS , the failure unit 35 receives the second switching control signal 302 to control the failure of the first thin film transistor 301, and the feedback unit 37 respectively transmits the output signal according to the output terminal Vout A feedback signal 304, 306 is sent to the first input unit 31 and the failure unit 35, the source 303b of the second thin film transistor 303 is coupled to the output terminal Vout, and the gate 303c of the second thin film transistor 303 is coupled to the second input unit 33 For receiving the second control signal 302 , the drain 303 a of the second thin film transistor 303 is coupled to the second power supply terminal V _SS .

The first input unit 31 includes a third thin film transistor 305 and a fourth thin film transistor 307, the second input unit 33 includes a fifth thin film transistor 309 and a sixth thin film transistor 311, and the failure unit 35 includes a seventh thin film transistor 313 And an eighth thin film transistor 315, the feedback unit 37 includes a ninth thin film transistor 317 and a tenth thin film transistor 319, and all the thin film transistors 301, 303, ,, 319 of the second embodiment are the same type of thin film transistors, more detailed For example, the embodiment of the present invention is an example of a P-type thin film transistor, however, an N-type thin film transistor can also be used. Furthermore, the material of the thin film transistor (such as: amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon Or a mixture of the above materials) and the type of thin film transistor (such as: bottom gate type, top gate type or similar type) can also be used. The connection relationship is described below.

The gate 305c of the third thin film transistor 305 is coupled to the first input terminal Vin and the drain 305a of the third thin film transistor 305, and the source 307b of the fourth thin film transistor 307 is coupled to the gate 301c of the first thin film transistor 301 for To transmit the first switching control signal 300, the gate 307c of the fourth thin film transistor 307 is coupled to the gate 305c of the third thin film transistor 305, and the drain 307a of the fourth thin film transistor 307 is coupled to the source of the third thin film transistor 305 Pole 305b and receive feedback signal 304.

The source 309b of the fifth thin film transistor 309 is coupled to the gate 303c of the second thin film transistor 303 for transmitting the second switching control signal 302, and the gate 309c of the fifth thin film transistor 309 is coupled to the drain of the fifth thin film transistor 309 electrode 309a and the second input terminal Vxin, the gate 311c of the sixth TFT 311 is coupled to the first input terminal Vin, the drain 311a of the sixth TFT 311 is coupled to the second power supply terminal V _SS , the sixth TFT The source 311b of the transistor 311 is coupled to the gate 303c of the second TFT 303 and the source 309b of the fifth TFT 309 .

The source 313b of the seventh thin film transistor 313 is coupled to the gate 301c of the first thin film transistor 301, the source 315b of the eighth thin film transistor 315 is coupled to the drain 313a of the seventh thin film transistor 313 and receives the feedback signal 306. The gate 315c of the eighth thin film transistor 315 and the gate 313c of the seventh thin film transistor 313 are coupled to the gate 303c of the second thin film transistor 303 for receiving the second switching control signal 302, and the drain 315a of the eighth thin film transistor 315 is coupled to Connect to the second power supply terminal V _SS .

The source 317b of the ninth thin film transistor 317 is coupled to the source 305b of the third thin film transistor 305 to provide the feedback signal 304, the gate 317c of the ninth thin film transistor 317 is coupled to the drain 317a of the ninth thin film transistor 317 and the output Terminal Vout, the source 319b of the tenth thin film transistor 319 is coupled to the drain 313a of the seventh thin film transistor 313 and the source 313b of the eighth thin film transistor 315 to provide the feedback signal 306, the gate 319c of the tenth thin film transistor 319 is coupled connected to the drain 319a of the tenth thin film transistor 319 and the output terminal Vout.

3B to 3D are waveform diagrams of the voltages of the first input terminal Vin and the output terminal Vout versus time of the second embodiment under three different critical voltages of the thin film transistor, wherein the first critical voltage is about -1V (corresponding to FIG. 3B ), the second critical voltage is about -2.5V (corresponding to FIG. 3C ), and the third critical voltage is about -4V (corresponding to FIG. 3D ). In addition, in FIGS. 3B to 3D, the first power supply terminal V _DD is set to about -6V, the second power supply terminal V _SS is set to about 9V, and a PMOS thin film transistor with an electron mobility of 60cm ² /Vsec is used and Output the waveform obtained under the experimental environment with a capacitive load of 20pF.

It can be seen from FIG. 3B that when the threshold voltage of the thin film transistor is -1V, the output signal waveform Vout of the output terminal Vout is very close to the voltage level of the first power supply terminal V _DD in the low level output part. From FIG. 3C , it can be seen that when the threshold voltage of the thin film transistor is -2.5V, the waveform is maintained close to the ideal regardless of whether the output level is high or low. It can be seen from FIG. 3D that when the threshold voltage of the thin film transistor is -4V, the output signal waveform of the output terminal Vout still needs a long time to reach the low-level and high-level voltages.

FIG. 4A shows a third embodiment of the present invention. Compared with the second embodiment, the structure of the first input unit 31 and the second input unit 33 is slightly different. As shown in the figure, the first input unit 31 is also It includes an eleventh thin film transistor 401 and a twelfth thin film transistor 403, and the second input unit 33 also includes a thirteenth thin film transistor 405, and its connection relationship is described as follows.

The drain 305a of the third thin film transistor 305 is coupled to the first input terminal Vin, the source 307b of the fourth thin film transistor 307 is coupled to the gate 301c of the first thin film transistor 301 and the failure unit 35, and the fourth thin film transistor 307 The gate 307c is coupled to the gate 305c of the third thin film transistor 305, the drain 307a of the fourth thin film transistor 307 is coupled to the source 305b of the third thin film transistor 305, and the gate 401c of the eleventh thin film transistor 401 is coupled to To the first input terminal Vin and the second input unit 33, the drain 401a of the eleventh thin film transistor 401 is coupled to the first input terminal Vin, and the source 401b of the eleventh thin film transistor 401 is coupled to the fourth thin film transistor 307 the gate 307c of the twelfth thin film transistor 403, the gate 403c of the twelfth thin film transistor 403 is coupled to the gate 305c of the third thin film transistor 305, the source 403b of the twelfth thin film transistor 403 is coupled to the first input terminal Vin, the twelfth The drain 403 a of the TFT 403 is coupled to the gate 305 c of the third TFT 305 .

The source 309b of the fifth thin film transistor 309 is coupled to the gate 303c of the second thin film transistor 303, the drain 309a of the fifth thin film transistor 309 is coupled to the second input terminal Vxin, and the gate 311c of the sixth thin film transistor 311 is coupled to connected to the first input terminal Vin, the drain 311a of the sixth thin film transistor 311 is coupled to the second power supply terminal V _SS , the source 311b of the sixth thin film transistor 311 is coupled to the gate 303c of the second thin film transistor 303, The gate 405c of the thirteenth thin film transistor 405 is coupled to the second input terminal Vxin, the source 405b of the thirteenth thin film transistor 405 is coupled to the gate 309c of the fifth thin film transistor 309, and the drain of the thirteenth thin film transistor 405 The pole 405a is coupled to the second input terminal Vxin.

The connection relationship of other components is the same as that of the second embodiment, so it will not be described in detail.

The eleventh thin film transistor 401 and the twelfth thin film transistor 403 have a bootstrap effect (Bootstrap Effect), and the thirteenth thin film transistor 405 of the second input unit 33 can improve the performance of the circuit. 4B to 4D are waveform diagrams of the voltages of the first input terminal Vin and the output terminal Vout versus time of the third embodiment under three different critical voltages of the thin film transistor, wherein the first critical voltage is -1V (corresponding to FIG. 4B), the second critical voltage is -2.5V (corresponding to FIG. 4C ), and the third critical voltage is -4V (corresponding to FIG. 4D ). In addition, in Figures 4B to 4D, the first power supply terminal V _DD is set to -6V, the second power supply terminal V _SS is set to 9V, and a PMOS thin film transistor with an electron mobility of 60cm ² /Vsec and an output capacitive load are used. Waveform obtained for the experimental environment of 20pF. It can be seen from FIG. 4B to FIG. 4D that no matter whether the threshold voltage of the thin film transistor is low or high, the output signal waveform of the output terminal Vout can obtain good results.

FIG. 5A shows a fourth embodiment of the present invention, which differs from the third embodiment in the second input unit 33 . The second input unit 33 also includes a fourteenth thin film transistor 501, a fifteenth thin film transistor 503, a sixteenth thin film transistor 505, a seventeenth thin film transistor 507, an eighteenth thin film transistor 509, a nineteenth thin film transistor 511, a The twenty thin film transistor 513 and the twenty first thin film transistor 515, all transistors are P-type thin film transistors, and the connection relationship of the second input unit 33 is described as follows.

The drain 309a of the fifth thin film transistor 309 is coupled to the first input terminal Vin, the gate 311c of the sixth thin film transistor 311 is coupled to the second input terminal Vxin, and the source 311b of the sixth thin film transistor 311 is coupled to the fifth The source 309b of the thin film transistor 309, the drain 311a of the sixth thin film transistor 311 are coupled to the second power supply terminal Vss, the gate 405c of the thirteenth thin film transistor 405 is coupled to the first input terminal Vin, and the thirteenth thin film transistor 405 is coupled to the first input terminal Vin. The source 405b of the transistor 405 is coupled to the gate 309c of the fifth TFT 309, and the drain 405a of the thirteenth TFT 405 is coupled to the first input terminal Vin.

The drain 501a of the fourteenth thin film transistor 501 is coupled to the second input terminal Vxin, the source 501b of the fourteenth thin film transistor 501 is coupled to the gate 303c of the second thin film transistor 303, and the source of the fifteenth thin film transistor 503 The electrode 503b is coupled to the gate 303c of the second thin film transistor 303. The drain 503a of the fifteenth thin film transistor 503 is coupled to the second power supply terminal Vss, and the gate 503c of the fifteenth thin film transistor 503 is coupled to the fifth thin film transistor 503. The source 309b of the transistor 309, the source 505b of the sixteenth thin film transistor 505 is coupled to the gate 501c of the fourteenth thin film transistor 501, the gate 505c of the sixteenth thin film transistor 505 is coupled to the gate 501c of the fifth thin film transistor 309 The source 309b, the gate 507c of the seventeenth thin film transistor 507 are coupled to the gate 505c of the sixteenth thin film transistor 505, the drain 507a of the seventeenth thin film transistor 507 is coupled to the second power supply terminal Vss, the tenth The source 507b of the seventh TFT 507 is coupled to the drain 505a of the sixteenth TFT 505, the gate 509c of the eighteenth TFT 509 is coupled to the source 501b of the fourteenth TFT 501 and the eighteenth TFT The drain 509a of the transistor 509, the source 509b of the eighteenth thin film transistor 509 is coupled to the drain 505a of the sixteenth thin film transistor 505, and the source 511b of the nineteenth thin film transistor 511 is coupled to the sixteenth thin film transistor 505 The source 505b of the twentieth thin film transistor 513 is coupled to the gate 511c of the nineteenth thin film transistor 511 and the drain 513a of the twentieth thin film transistor 513, and the source 513b of the twentieth thin film transistor 513 Coupled to the drain 511a of the nineteenth thin film transistor 511 and the second input terminal Vxin, the gate 515c and the drain 515a of the twenty-first thin film transistor 515 are coupled to the second input terminal Vxin, the twenty-first thin film transistor The source 515 b of 515 is coupled to the drain 513 a of the twentieth thin film transistor 513 .

The connection relationship of other components is the same as that of the third embodiment, so it will not be described in detail.

5B to 5D are waveform diagrams of the voltages of the first input terminal Vin and the output terminal Vout versus time of the fourth embodiment under three different critical voltages of the thin film transistor, wherein the first critical voltage is about -1V (corresponding to FIG. 5B ), the second critical voltage is about -2.5V (corresponding to FIG. 5C ), and the third critical voltage is about -4V (corresponding to FIG. 5D ). In addition, in FIGS. 5B to 5D, the first power supply terminal VDD is set to about -6V, the second power supply terminal VSS is set to about 9V, and a PMOS thin film transistor with an electron mobility of 60cm ² /Vsec and an output capacitor are used. The waveform obtained under the experimental environment with a load of 20pF. It can be seen from FIG. 5B to FIG. 5D that no matter whether the threshold voltage of the thin film transistor is low or high, the output signal waveform of the output terminal Vout can maintain a good result.

Referring to Table 1 at the same time, what is listed is the comparison of the currents flowing through the first power supply V _DD in the third embodiment and the fourth embodiment under different threshold voltages of thin film transistors. From this table, it can be seen that the fourth embodiment flows through the first power supply V DD The current of the power supply V _DD is obviously smaller, so power consumption can be saved.

Table I

Thin film transistor threshold voltage (V) The current flowing through the first power supply in the third embodiment (μA) The current flowing through the first power supply in the fourth embodiment (μA) -1 58.0 13.5 -2 8.5 5.2 -3 3.3 1.8 -4 1.3 0.5

In summary, the present invention discloses various circuits of voltage level shifters made of same-type thin film transistors. When this voltage level shifter circuit is integrated on a display TFT substrate, a simpler TFT process, And achieve the characteristics of low power consumption.

The above-mentioned embodiments are only illustrative to illustrate the principles and effects of the present invention, and are not intended to limit the present invention. Those skilled in the art can modify and change the above-mentioned embodiments without violating the technical principle and spirit of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims of the present invention.

Claims (17)

1. voltage level shifter comprises:

One first input end is in order to import one first input signal;

One second input is in order to import one second input signal;

One first power source supply end;

One second source feed end;

One the first film transistor comprises a grid, one source pole and a drain electrode, and wherein transistorized this drain electrode of this first film is coupled to this first input end and transistorized this grid of this first film;

One second thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this source electrode of this second thin-film transistor is coupled to this first power source supply end, and this grid of this second thin-film transistor is coupled to transistorized this source electrode of this first film;

One the 3rd thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this source electrode of the 3rd thin-film transistor is coupled to this drain electrode of this second thin-film transistor, and this drain electrode of the 3rd thin-film transistor is coupled to this second source feed end;

One the 4th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this source electrode of the 4th thin-film transistor is coupled to this grid of this second thin-film transistor, this drain electrode of the 4th thin-film transistor is coupled to this second source feed end, and this grid of the 4th thin-film transistor is coupled to this grid of the 3rd thin-film transistor;

One the 5th thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this grid of the 5th thin-film transistor and this drain electrode are coupled to this second input, and this source electrode of the 5th thin-film transistor is coupled to this grid of the 4th thin-film transistor;

One the 6th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 6th thin-film transistor is coupled to this first input end, this drain electrode of the 6th thin-film transistor is coupled to this second source feed end, and this source electrode of the 6th thin-film transistor is coupled to this source electrode of the 5th thin-film transistor; And

One output is in order to being coupled to this source electrode of the 3rd thin-film transistor,

Wherein the thin-film transistor that this voltage level shifter comprised is identical doping type thin-film transistor.

2. voltage level shifter as claimed in claim 1, wherein this first input signal and this second input signal are anti-phase each other.

3. voltage level shifter as claimed in claim 1, wherein, this first film transistor, this second thin-film transistor, the 3rd thin-film transistor, the 4th thin-film transistor, the 5th thin-film transistor and the 6th thin-film transistor are a homotype thin-film transistor.

4. voltage level shifter as claimed in claim 1, wherein, this first power source supply end provides the voltage of negative potential, and this second source feed end provides the voltage of positive potential.

5. voltage level shifter as claimed in claim 4, wherein, this first power source supply end provides the voltage of pact-6V, and this second source feed end provides the voltage of about 9V.

6. voltage level shifter comprises:

One first input end is in order to import one first input signal;

One second input is in order to import one second input signal;

One output;

One first power source supply end;

One second source feed end;

One first input unit in order to receiving this first input signal, and is exported one first switch-over control signal;

One second input unit is coupled to this second source feed end, receives this second input signal, and exports one second switch-over control signal;

One the first film transistor, comprise a grid, one source pole and a drain electrode, wherein transistorized this grid of this first film is coupled to this first input unit, in order to receive this first switch-over control signal, transistorized this drain electrode of this first film is coupled to this output, and transistorized this source electrode of this first film is coupled to this first power source supply end;

One disabling unit is coupled to this first input unit, this second input unit, this first film transistor and this second source feed end, makes this first film transistor nonfunctional in order to control;

One feedback unit in order to the output signal according to this output, transmits a feedback signal respectively to this first input unit and this disabling unit; And

One second thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of this second thin-film transistor is coupled to this second input unit, in order to receive this second switch-over control signal, this source electrode of this second thin-film transistor is coupled to this output, and this drain electrode of this second thin-film transistor is coupled to this second source feed end;

Wherein the thin-film transistor that this voltage level shifter comprised is identical doping type thin-film transistor.

7. voltage level shifter as claimed in claim 6, wherein, this first input signal and this second input signal are anti-phase each other.

8. voltage level shifter as claimed in claim 6, wherein, signal and this first input signal of this output output are homophase.

9. voltage level shifter as claimed in claim 6, wherein, this first power source supply end provides the voltage of negative potential, and this second source feed end provides the voltage of positive potential.

10. voltage level shifter as claimed in claim 9, wherein, this first power source supply end provides the voltage of pact-6V, and this second source feed end provides the voltage of about 9V.

11. voltage level shifter as claimed in claim 6, wherein, this first input unit also comprises:

One the 3rd thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this grid of the 3rd thin-film transistor is coupled to this drain electrode of this first input end and the 3rd thin-film transistor; And

One the 4th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 4th thin-film transistor is coupled to this grid of the 3rd thin-film transistor, this drain electrode of the 4th thin-film transistor is coupled to this source electrode of the 3rd thin-film transistor and receives this feedback signal, and this source electrode of the 4th thin-film transistor is coupled to transistorized this grid of this first film.

12. voltage level shifter as claimed in claim 6, wherein, this second input unit also comprises:

One the 5th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 5th thin-film transistor is coupled to this drain electrode of this second input and the 5th thin-film transistor, and this source electrode of the 5th thin-film transistor is coupled to this grid of this second thin-film transistor; And

One the 6th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 6th thin-film transistor is coupled to this first input end, this source electrode of the 6th thin-film transistor is coupled to this grid of this second thin-film transistor, and this drain electrode of the 6th thin-film transistor is coupled to this second source feed end.

13. voltage level shifter as claimed in claim 6, wherein, this disabling unit also comprises:

One the 7th thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this source electrode of the 7th thin-film transistor is coupled to transistorized this grid of this first film; And

One the 8th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 8th thin-film transistor is coupled to this grid of the 7th thin-film transistor and this grid of this second thin-film transistor, this drain electrode of the 8th thin-film transistor is coupled to this second source feed end, and this source electrode of the 8th thin-film transistor is coupled to this drain electrode of the 7th thin-film transistor and receives this feedback signal.

14. voltage level shifter as claimed in claim 6, wherein, this feedback unit comprises:

One the 9th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 9th thin-film transistor is coupled to this drain electrode of this output and the 9th thin-film transistor, and this source electrode of the 9th thin-film transistor is coupled to this first input unit; And

The tenth thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this grid of the tenth thin-film transistor is coupled to this drain electrode of this output and the tenth thin-film transistor, and this source electrode of the tenth thin-film transistor is coupled to this disabling unit.

15. voltage level shifter as claimed in claim 6, wherein, this first input unit also comprises:

One the 3rd thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this drain electrode of the 3rd thin-film transistor is coupled to this first input end;

One the 4th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 4th thin-film transistor is coupled to this grid of the 3rd thin-film transistor, this drain electrode of the 4th thin-film transistor is coupled to this source electrode of the 3rd thin-film transistor, and this source electrode of the 4th thin-film transistor is coupled to transistorized this grid of this first film and this disabling unit;

The 11 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 11 thin-film transistor is coupled to this first input end and this second input unit, this drain electrode of the 11 thin-film transistor is coupled to this first input end, and this source electrode of the 11 thin-film transistor is coupled to this grid of the 4th thin-film transistor; And

The 12 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 12 thin-film transistor is coupled to this grid of the 3rd thin-film transistor, this source electrode of the 12 thin-film transistor is coupled to this first input end, and this drain electrode of the 12 thin-film transistor is coupled to this grid of the 3rd thin-film transistor.

16. voltage level shifter as claimed in claim 6, wherein, this second input unit also comprises:

One the 5th thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this drain electrode of the 5th thin-film transistor is coupled to this second input, and this source electrode of the 5th thin-film transistor is coupled to this grid of this second thin-film transistor; And

One the 6th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 6th thin-film transistor is coupled to this first input end, this source electrode of the 6th thin-film transistor is coupled to this grid of this second thin-film transistor, and this drain electrode of the 6th thin-film transistor is coupled to this second source feed end.

The 13 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 13 thin-film transistor is coupled to this second input, this source electrode of the 13 thin-film transistor is coupled to this grid of the 5th thin-film transistor, and this drain electrode of the 13 thin-film transistor is coupled to this second input.

17. voltage level shifter as claimed in claim 6, wherein, this second input unit also comprises:

One the 5th thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this drain electrode of the 5th thin-film transistor is coupled to this first input end;

One the 6th thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 6th thin-film transistor is coupled to this second input, this source electrode of the 6th thin-film transistor is coupled to this source electrode of the 5th thin-film transistor, and this drain electrode of the 6th thin-film transistor is coupled to this second source feed end.

The 13 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 13 thin-film transistor is coupled to this first input end, this source electrode of the 13 thin-film transistor is coupled to this grid of the 5th thin-film transistor, and this drain electrode of the 13 thin-film transistor is coupled to this first input end;

The 14 thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this drain electrode of the 14 thin-film transistor is coupled to this second input, and this source electrode of the 14 thin-film transistor is coupled to this grid of this second thin-film transistor;

The 15 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this source electrode of the 15 thin-film transistor is coupled to this grid of this second thin-film transistor, this drain electrode of the 15 thin-film transistor is coupled to this second source feed end, and this grid of the 15 thin-film transistor is coupled to this source electrode of the 5th thin-film transistor;

The 16 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this source electrode of the 16 thin-film transistor is coupled to this grid of the 14 thin-film transistor, and this grid of the 16 thin-film transistor is coupled to this source electrode of the 5th thin-film transistor;

The 17 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 17 thin-film transistor is coupled to this grid of the 16 thin-film transistor, this drain electrode of the 17 thin-film transistor is coupled to this second source feed end, and this source electrode of the 17 thin-film transistor is coupled to this drain electrode of the 16 thin-film transistor;

The 18 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 18 thin-film transistor is coupled to this source electrode of the 14 thin-film transistor and this drain electrode of the 18 thin-film transistor, and this source electrode of the 18 thin-film transistor is coupled to this drain electrode of the 16 thin-film transistor;

The 19 thin-film transistor comprises a grid, one source pole and a drain electrode, and wherein this source electrode of the 19 thin-film transistor is coupled to this source electrode of the 16 thin-film transistor;

One the 20 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 20 thin-film transistor is coupled to this grid of the 19 thin-film transistor and this drain electrode of the 20 thin-film transistor, and this source electrode of the 20 thin-film transistor is coupled to this drain electrode and this second input of the 19 thin-film transistor; And

One the 21 thin-film transistor, comprise a grid, one source pole and a drain electrode, wherein this grid of the 21 thin-film transistor and this drain electrode are coupled to this second input, and this source electrode of the 21 thin-film transistor is coupled to this drain electrode of the 20 thin-film transistor.

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