CN1678037A - Active Pixel Sensor Circuit - Google Patents

Abstract

The disclosed circuit comprises following parts: silicon substrate including photodiodes capable of converting luminous intensity into voltage signal; arranged on substrate, two metal layers possessing pixel control circuit. The first metal layer comprises row trace and reset trace. The second metal layer comprises column trace and voltage supply trace. Row trace carries signals. In reading period, the signal triggers switch in order to couple photodiodes to column trace and reset voltage at photodiode at reset period. Column trace is interfaced to signal capture circuit in CMOS array of pixels in order to capture digital image in each voltage level corresponding to each photodiode.

Description

Circuit for active pixel sensor

Technical field

The circuit of relate generally to CMOS active pixel sensor of the present invention.More particularly, the present invention relates to reduce metal and the thickness of oxide skin(coating) and/or the pixel capture circuit of quantity in the cmos pixel array.

Background technology

Digital camera and other imaging devices generally have equipment array, for example are arranged in the pixel that is used on the CMOS microchip to catch with memory image.Each equipment and interlock circuit thereof will change in the detected luminous intensity of each location of pixels of image can be digitized the voltage signal of storing, reproducing and handle to be used to, here, the combination of each equipment and interlock circuit thereof is commonly called CMOS active pixel sensor (APS).

Fig. 1 shows a kind of schematic diagram of realizing of traditional three transistor APS 100, this APS is with a pixel digitlization of image.The resolution of the quantity decision captured images of the pixel in APS 100 arrays.General A PS 100 pixels comprise three transistors 120,121 and 122, and are arranged on the photodiode 125 on the silicon area, are provided with a plurality of metal levels on described silicon area.Generally need a plurality of metal levels to be because APS 100 needs five terminal traces (trace) to be used for operation.This is because the width on the traditional cmos array between each APS 100 generally only allows enough spaces to be used for two terminal traces of each metal level.Described five terminal traces comprise RESET (resetting) 110, PRESET (presetting) 111, V _Dd112, COLUMN (row) 113 and ROW (OK) 114.Each APS 100 also comprises GROUND (ground connection) 115 terminals.By using the controller (not shown) in each control terminal of APS 100 and the every other contact point control signal that is associated with other APS 100 (not shown) in the CMOS array, just can detect the luminous intensity that also digitlization shines the CMOS array, i.e. image.

Fig. 2 is the sequential chart of the traditional operation of APS 100 among Fig. 1.The operation of APS 100 comprises reseting stage 200, accumulation stage 220 and reads the stage 240.With reference to sequential chart in these stages 200,220 and 240 each is described below.

Before obtaining image, each APS 100 must be at first at reseting stage 200 quilts " zero clearing ".This is to begin to accumulate the light time when photodiode 125 in order to guarantee, all pixels in the CMOS array (not shown) all have identical starting voltage.During the time period 201, APS 100 is in previous reading the stage 240, therefore (as following explanation) about the stage of reading 240, RESET 110 traces are set to predetermined low voltage level (being generally 0 volt), and ROW 113 and PRESET 111 traces are set to predetermined high-voltage level (being generally 2.5 to 5.0 volts).At t2, RESET 110 traces are enhanced high-voltage level, make transistor 121 serve as Closing Switch.Like this, the voltage at node 130 places just equals the voltage at PRESET 111 trace places.The voltage at node 130 places may turn-on transistor 122, but any electric current of the transistor 122 of may flowing through all is unessential, because any signal that obtains on COLUMN 113 traces is describedly read the stage 240 and just understood sensed up to following.Next, PRESET 111 traces are reduced to the predetermined low voltage level, and RESET 110 traces still are in high-voltage level.Like this, the voltage step-down at node 130 places, this parasitic capacitance (not shown) that causes being associated with photodiode 125 discharges.At last, PRESET 111 traces are resumed to high-voltage level is charged to the predetermined start voltage level with the parasitic capacitance with photodiode 125, thereby finish reseting stage 200.

Next, in the accumulation stage 220, after photodiode 125 was reset, RESET 110 traces were set to low-voltage at t3, made transistor 121 turn-off.At this moment, photodiode 125 light that just is ready to be exposed to from the image that will catch has suffered.During the section 204, photodiode 125 is exposed in the light at the fixed time.As everyone knows, photodiode 125 causes and its proportional reverse current of luminous intensity of irradiation, thereby parasitic capacitance is partially or even wholly discharged.

After predetermined integration time section 204, begin the stage of reading 240.ROW 114 traces are become high-voltage level at t5, make transistor 120 become Closing Switch, and transistor 122 serve as source follower (source follower).This causes the voltage (this voltage representative is in detected luminous intensity during the accumulation stage 220) at node 130 places that the voltage bias on COLUMN 113 traces is deducted the V that is caused by transistor 122 to this voltage level _GS Pressure drop.COLUMN 113 traces are coupled to the constant-current source (not shown), make the voltage at node 130 places will change corresponding voltage on COLUMN 113 traces into via transistor 122.Because for for all crystals pipe 122 among other APS 100, the voltage threshold of transistor 122 all is equal or approximately equalised, so V _GSThe influence of pressure drop offsets, and makes the treatment circuit (not shown) determine the luminous intensity at the pixel place that caught by APS 100 based on the voltage on COLUMN 113 traces.

During the image acquisition procedure, each the row APS 100 (being pixel) in the CMOS array is repeated each above-mentioned stage.The circulation independently of each row, and generally carry out above-mentioned circulation in the mode of rolling.That is, when first the row be converted to accumulation during the stage from reseting stage, next line just begins reseting stage.Therefore, when one-row pixels was read, other pixel columns can not be read.

The problem of the APS 100 of Fig. 1 is that each APS 100 needs five terminal traces, as mentioned above.As a result, for the CMOS array, generally needing three metal levels at least, is trace (two every layer here) fixed line of each pixel in metal level.These metal levels generally be disposed in active silicon area above, on this active silicon area, form integrated photodiode 125 and transistor 120,121 and 122.In addition, these metal levels generally by the thicker relatively dielectric layer that is used to insulate separately.Therefore, traditional CMOS array generally comprises at least three metal levels that separated by dielectric.

Fig. 3 is the figure in the zone that occupied by APS 100 in traditional cmos array 300.Three metal levels 310,311 and 312 by oxide-insulator 315 separates all produce cavity (cavitity) 320 above each photodiode 125.These cavitys 320 can cause two problems.At first, metal and oxide skin(coating) are thick more, quantity is many more, will stop that many more light arrives the photodiode 125 in the CMOS array 300.Therefore, along with the increase of metal and oxide skin(coating) thickness and quantity, the sensitivity of CMOS array 300 descends.

Secondly, cavity 320 is high more, and the incidence angle 330 of incident light just must be the closer to the normal of CMOS array 300, to arrive the pixel shown in shadow region 325.Therefore, if incidence angle 330 is too big, photodiode 125 just can not correctly be caught image so.In addition, because the restriction in space, the calibrating optical chain (optical train) that is used to reduce incidence angle may be infeasible.

Therefore, hope can reduce the thickness and/or the quantity of metal and oxide skin(coating) in the cmos pixel array.

Summary of the invention

According to embodiments of the invention, a kind of image element circuit comprises silicon substrate, and it has photodiode, is used for luminous intensity is converted to voltage signal.Image element circuit also comprises row traces and the trace that resets.Row traces during the stage of reading trigger switch photodiode being coupled to the row trace, and in the voltage zero clearing of reseting stage with photodiode.Image element circuit also comprises voltage supply trace.The image element circuit needs metal level still less that only has four traces.

(for example, be used for row traces and the first metal layer of trace that resets, and be used for row trace and V by the metal level that has still less _DdSecond metal level), when catching image, light is with easier arrival photodiode.That is, the cavity of each pixel of being discussed is more shallow, because only have two metal levels rather than three.Therefore, for the control circuit that is associated with each pixel, the metal level that has still less is favourable.

Another advantage with metal level still less is the light that can catch bigger incidence angle.Because the space is limited in the application of for example digital camera mobile phone, so the optical correction chain between light source and cmos pixel array is infeasible.Therefore, compare with the traditional cmos pixel array with the more metal levels that are used for control circuit, in having the cmos pixel array of metal level still less, incidence angle can be bigger.

Description of drawings

By with reference to detailed description below in conjunction with accompanying drawing, will be more readily understood above-mentioned aspect of the present invention and subsidiary many advantages, wherein:

Fig. 1 is the schematic diagram of traditional three transistor pixels capture circuits;

Fig. 2 is the sequential chart that illustrates the three transistor pixels capture circuits operation of Fig. 1;

Fig. 3 is the profile in a zone of traditional cmos pel array, and this traditional cmos pel array comprises the three transistor pixels capture circuits of Fig. 1;

Fig. 4 is the schematic diagram according to three transistor pixels capture circuits of the embodiment of the invention;

Fig. 5 is the sequential chart according to three transistor pixels capture circuits operation among Fig. 4 of the embodiment of the invention; And

Fig. 6 according to the embodiment of the invention, comprise the block diagram of the CMOS array of the pixel capture circuit among Fig. 4.

Embodiment

Fig. 4 is the schematic diagram according to three transistor APS 400 of the embodiment of the invention.APS 400 is similar to the APS 100 of Fig. 1, and just APS 400 includes only four terminal traces rather than five.This minimizing of terminal trace allows the minimizing of metal and oxide skin(coating) in corresponding pel array (Fig. 6), thereby has improved the sensitivity of array.

APS 400 comprises three transistors 420,421 and 422 and be arranged in integrated photodiode 425 on the active silicon area (not shown).But different with the APS 100 of Fig. 1 is only to need four terminal traces be used for operation.These four traces comprise RESET 410, V _Dd412, COLUMN 413 and ROW 414.Each APS 400 also comprises GROUND 415 terminals.Because 400 of each APS have four traces, so these traces need metal level still less.Among the embodiment that goes out shown here, APS 400 has removed PRESET 111 traces, exists among this trace traditional APS 100 shown in Figure 1.By the Protection Counter Functions of PRESET 111 traces and the function of ROW 414 traces are combined, only used four traces to be used for operation.

Fig. 5 is the sequential chart that illustrates the operation of APS 400 among Fig. 4.The operation of APS 400 comprises reseting stage 500, accumulation stage 520 and reads the stage 540.In these stages 500,520 and 540 each will be described below.

Before obtaining image, APS 400 is cleared at reseting stage 500.During the time period 501, APS 400 is in previous reading the stage 540, and therefore, RESET 410 traces are set to the predetermined low voltage level, and ROW 414 traces are set to predetermined high-voltage level.At t2, RESET 410 traces are enhanced high-voltage level, make transistor 421 serve as Closing Switch, and like this, the voltage at node 430 places just equals the voltage at ROW 414 trace places.The voltage at node 430 places may turn-on transistor 422, and some electric currents transistor 422 of may flowing through, and ROW 414 traces of the grid of transistor 420 are in high-voltage level and transistor 420 is conductings because also be coupled to.But, because COLUMN 413 traces can be not accessed, promptly be not the stage of reading 540 now, so the voltage on COLUMN 413 traces does not generally produce bad influence to the operation of CMOS array.

Next, ROW 414 traces are reduced to the predetermined low voltage level, and RESET 410 traces still are in high-voltage level.Like this, the voltage step-down at node 430 places makes photodiode 425 discharges.Then, ROW 414 traces are resumed and are high voltage, are charged to the predetermined start voltage level with the parasitic capacitance that will be associated with photodiode, thereby finish reseting stage 500.

Next, in the accumulation stage 520, after the parasitic capacitance that is associated with photodiode 425 was discharged, RESET 410 traces were set to low-voltage at t3, made transistor 421 turn-off.At this moment, photodiode 425 was exposed in the light during predetermined accumulation period 504.

After predetermined accumulation period 504, begin the stage of reading 540.ROW 414 traces are become high-voltage level at t5, make transistor 420 conductings and become Closing Switch, and transistor 422 serves as source follower.The predetermined high voltage of reading during the stage 540 can be identical with the voltage of reseting stage, but also may depend on turn-on transistor 422 required electric currents and different.This voltage (this voltage representative in detected luminous intensity during the accumulation stage 520) that causes node 430 places deducts the V that is caused by transistor 422 with the voltage bias on COLUMN 413 terminals to the voltage at node 430 places _GSPressure drop.Equally, because for for all crystals pipe 422 among other APS 400, the voltage threshold of transistor 422 all is equal or approximately equalised, so V _GSThe influence of pressure drop offsets, and makes the treatment circuit (not shown) determine the luminous intensity at pixel place based on the voltage on COLUMN 413 traces.

During the image acquisition procedure, each row pixel (APS 400) is all repeated each above-mentioned stage.The circulation independently of each row, and each row generally carries out above-mentioned circulation one by one.That is, after first each of passing through in three above-mentioned stages, next adjacent row begins to experience this three phases from reseting stage.Therefore, when one-row pixels was read, other pixel columns can not be read.This illustrates in greater detail in Fig. 6, and is as described below.

Fig. 6 shows the block diagram of system 600, and this system comprises cmos pixel array 610, and this arranged in arrays has the APS 400 of several Fig. 4.System 600 can be digital camera, digital camera mobile phone, or uses other electronic equipments of digital image capture device.This system comprises the CPU (CPU) 615 with bus 620 couplings.With the memory 625 in addition of bus 620 couplings, it is used to store the digital picture of being caught by CMOS array 610.CPU 615 is more prone to catching of image by following means: in a single day it controls CMOS arrays 610 by bus 620, and captures image, just image is stored in the memory 625 with number format.

CMOS array 610 comprises several parts, is used to make catching with digitlization of image to be more prone to.Each APS 400 in the CMOS array 610 is coupled to ROW control circuit 650 and COLUMN control circuit 660, and ROW control circuit 650 and COLUMN control circuit 660 facilitate for the control signal that reference Fig. 4 and Fig. 5 describe.More specifically, the APS of each in single row of pixels 400 passes through to connect (connection) 651 and is coupled to special-purpose ROW (Fig. 4 414) control line and special-purpose RESET (Fig. 4 410) control line.In addition, each APS 400 in row is coupled to special-purpose COLUMN (Fig. 4 413) control line by connecting 661.And each APS 400 in the CMOS array 610 is coupled to V _Dd611 with GROUND 612 (do not illustrate each be connected).

Described with reference to Fig. 5 as the front, each provisional capital of CMOS array 610 is separated to read.For example, each pixel in first row 652 begins the image acquisition procedure, promptly resets 500, accumulation 520 and read 540, the then identical image acquisition procedure of next line 653 beginnings.Voltage on COLUMN 413 traces of each APS 400 in the stages of reading 540, the first row is read by COLUMN control circuit 660, and is sent to multiplexer 670.Multiplexer is combined as a multiplex signal with the voltage signal of each COLUMN 413 trace, the voltage signal that catch in each photodiode 425 places of each pixel in the particular row that this signal representative just is being read, i.e. pixel.After amplification stage 680, this signal is converted into digital signal by analog to digital converter 690, is transmitted to bus 620 then.Then, CPU 615 helps this digital signal is stored in the memory 625, and to the next digital signal of representing next line too, the rest may be inferred.This process is repeated in each provisional capital in the CMOS array 610, be read up to each provisional capital and complete digital picture has been stored in the memory 625.

Here provided above-mentioned discussion, so that those skilled in the art can realize and use the present invention.Under the situation that does not break away from the spirit and scope of the present invention, universal principle as described herein can be applied to embodiment and the application outside described in detail here.The invention is not restricted to shown embodiment, but should give and principle and the corresponding to scope the most widely of feature disclosed here or that propose.

Claims (18)

1. A pixel capture circuit comprising: a pixel capture device having a node and operable to convert light intensity at the node into a pixel signal representative of the captured pixel; and A row node carrying a row signal operable to couple the node to a column trace during reading of a captured pixel and operable to set the node to a predetermined signal level during a reset phase. 2. The circuit of claim 1, further comprising a reset trace carrying a reset signal operable to decouple the node from the row trace during reading of a captured pixel. 3. The circuit of claim 2, wherein the pixel capture device is arranged on a silicon substrate. 4. The circuit of claim 3, wherein the row traces, column traces and reset traces are arranged on no more than two conductive layers arranged on the silicon substrate . 5. The circuit of claim 1, wherein the pixel capture device comprises a photodiode. 6. The circuit of claim 1, wherein the pixel signal comprises a voltage. 7. The pixel capture circuit of claim 1, further comprising: Substrate; two conductive layers disposed on the substrate; and One or more conductive paths, individually operable to carry the row signals, each disposed in a separate one of the two conductive layers. 8. The pixel capture circuit of claim 7, wherein the circuit has no other conductive layers arranged on the substrate other than the two conductive layers. 9. A pixel capture circuit comprising: a pixel capture device having first and second nodes, the first node being coupled to a first supply node; a first transistor having a control node coupled to a second node of the pixel capture device, a first drive node, and a second drive node, and the first drive node coupled to a second supply node; a second transistor having a control node, a first drive node, and a second drive node, the control node of the second transistor being coupled to a row node, the first drive node of the second transistor being coupled to the first transistor's a second drive node, the second drive node of the second transistor coupled to the column node; and a third transistor having a control node, a first drive node, and a second drive node, the control node of the third transistor being coupled to the reset node, the first drive node of the third transistor being coupled to the row node, the The second drive node of the third transistor is coupled to the second node of the pixel capture device. 10. The circuit of claim 9, wherein the first, second and third transistors comprise MOSFET transistors. 11. A CMOS array comprising: A plurality of pixel capture circuits are arranged in rows and columns, and the pixel capture circuits include: a pixel capture device having a node and operable to convert light intensity at the node into a pixel signal representative of the captured pixel; and A row node carrying a row signal operable to couple the node to a column trace during reading of a captured pixel and operable to set the node to a predetermined signal level during a reset phase. 12. The CMOS array of claim 11, further comprising a reset trace carrying a reset signal operable to decouple the nodes from the row trace during reading of captured pixels. 13. The CMOS array as claimed in claim 12, further comprising a first conductive layer and a second conductive layer, in which the row traces and the reset traces are arranged, in the second The column traces are arranged in the conductive layer. 14. A system comprising: CMOS array with: A plurality of pixel capture circuits are arranged in rows and columns, and the pixel capture circuits include: a pixel capture device having a node and operable to convert light intensity at the node into a pixel signal representative of the captured pixel; and a row node carrying a row signal operable to couple said node to a column trace during reading of a captured pixel and operable to set said node to a predetermined signal level during a reset phase; and a processor coupled to the CMOS array operable to detect a voltage signal at each column trace in each pixel of the CMOS array. 15. The system of claim 14, further comprising a memory coupled to the processor, the memory operable to store the pixel signal. 16. A method comprising: Accumulate a certain amount of light; generating a signal on a pixel node, the signal having a level related to the amount of accumulated light; reading the signal in response to a first control signal on the first control node; and The signal level at the pixel node is reset in response to a second control signal on the first control node. 17. The method of claim 16, said reading said signal further comprising detecting a level at a second control node. 18. The method of claim 16, wherein said resetting comprises: setting the level at the third control node to a predetermined high level; and making the level at the first control node jump from a predetermined high level to a predetermined low level.

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