CN1673954A - Method for holding data consistency when register document inbedding operation under multi process - Google Patents

Abstract

The invention discloses a method for maintaining data consistency during register file insertion operation under multi-process, comprising the following steps: pre-setting the scoreboard flag position of the entry of the register file, and setting the scoreboard flag position as occupied when the insertion instruction is executed value, put in the instruction and set the scoreboard flag as an idle value; judge whether the value of the scoreboard flag of the register file entry that the instruction needs to access is an occupied value, if so, suspend the process of executing the current instruction and execute the next process, otherwise execute the instruction. The method provided by the present invention ensures the continuous operation of the pipeline while strictly ensuring the data consistency when the register file is placed into the operation, without causing interruption in the execution of the pipeline, thereby greatly improving the performance of the CPU. command efficiency.

Description

A method to maintain data consistency during register file placement operations under multi-process

technical field

The invention belongs to data channel technology, in particular to a method for maintaining data consistency during register file insertion operations under multi-process.

Background technique

At present, most computers are developed based on the programmable computer model proposed by von Neumann. According to the theory of the programmable computer model proposed by von Neumann, the central processing unit (CPU) is mainly composed of a controller and a data channel, where the data channel represents the logic circuit necessary to implement each instruction, such as addition or logic operation etc., and the controller is responsible for sending a control signal to the data channel according to the obtained instruction to activate the corresponding processing circuit in the data channel.

The data channel part mainly includes a register file, an arithmetic logic unit (ALU) and a local memory. The register file is a set of general-purpose storage registers used to store data words to be used in the current calculation chain. The ALU unit provides all arithmetic operations and A group of circuits with logical operation functions, and the local memory is also called cache memory. The local memory communicates with both the CPU and the main system memory. It is mainly used to increase the speed of the CPU's access to the main system memory.

The operation of the register file includes three modes, which are register file to register file operation mode, store operation mode and put operation mode. In the register file to register file operation mode, the data source is the register file, and the processed data result is written back to the register file. The storage operation mode is to transfer the data in the register file to the local memory, and set The input operation mode is to transfer the data in the local memory to the register file.

Figure 1 shows a schematic diagram of data flow in the insert operation mode. As shown in Figure 1, the data source is a local memory, and the register file receives data from the local memory. When the put instruction is executed, the ALU unit provides a data address signal, and the put and store unit (LSU) fetches the data in the local memory according to the data address signal provided by the ALU unit, and sends the fetched data to the register file. The LSU unit is mainly used to process put instructions and store instructions in the CPU system. The put instruction is an instruction for the CPU system to read back data from the local memory to the register file, and the store instruction is an instruction for completing the writing of the data in the register file to the local memory. Due to the long execution time of the insert and store instructions, in order not to affect the normal operation of the CPU main pipeline, the insert and store instructions stored in the LSU unit are not the actual contents of the insert and store instructions, but the translated set Enter and store commands. These two commands mainly include the source address, destination address, data length and other information of the command.

The LSU unit generally includes a command first-in-first-out buffer (FIFO), a result FIFO, a read command control module, an output control module, a command decoding and MEM bus arbitration module. Since multiple insert and store instructions may need to be executed on the pipeline, the insert and store instructions are cached with the command FIFO, and the result data read back is cached with the result FIFO. When the pipeline executes the put instruction, the put instruction will be placed into the command FIFO, the data read from the local memory will be placed into the result FIFO, and the read command control module in the LSU unit continues to read the content in the command FIFO, and Write specific instructions into the command decoding and MEM bus arbitration module. The command decoding and MEM bus arbitration module generates the operation signal to the local memory according to the content of the command. The command decoding and MEM bus arbitration module first takes out the source address, and then writes the source address signal combined with the read chip select signal to the interface pin between it and the local memory. When the data is successfully read back from the local memory, it combines this setting The destination address in the command word of the incoming instruction composes a new result data and writes it into the result FIFO at the same time. When the command decoding and the MEM bus arbitration module read in the command is a storage command, it first takes out the destination address and data in the command, and then writes these destination addresses and data signals to it and the local memory in combination with the write chip select signal. interface pins.

In order to be able to correctly implement the operation of the register file in a computer system, the data must have been transferred from the memory to the register file before the ALU unit can be accessed, so the problem of data consistency must be considered, that is, every time the ALU unit operates The specific values of the registers in the register file used must be the values that the ALU unit should use. In order to ensure the consistency of register file data during CPU processing, it must be ensured that the data has been transferred from memory to registers before the ALU unit can access the data. For example, assuming that the current instruction is a put operation, this put operation instruction is to write the data of a certain address in the local memory into a register in a certain register file, and the next instruction will use The value of this register is calculated and processed, so when this instruction that needs to use the value of the register for calculation and processing can use the data of the register as the operator during calculation and processing, the previous put operation instruction must have been completed and stored in the memory The data is transferred to this register in the register file, otherwise the obtained result does not match the expected result.

In the prior art, when the instruction pipeline is executed, if it is found that the instruction is a built-in instruction in the decoding stage, several waiting cycles are inserted in the pipeline execution process to ensure that the inserted instruction can be executed correctly, and then the next instruction is executed. down instruction. For example, assuming that a process executes a register file insertion instruction and the CPU can execute 4 hardware processes at the same time by means of time-division multiplexing, and the LSU unit needs 4 cycles to complete reading the data from the external storage space, then according to According to the design method of the prior art, the process of executing the inserted instruction needs to wait for 4 cycles before executing the next instruction. Since the hardware process is scheduled every 4 cycles, there is no difference between the execution of the instruction at this time and the normal situation. Suppose The LSU unit needs to execute 8 cycles to finish reading the data in the external memory space, and the process of executing the embedded instruction needs to wait 8 cycles before executing the next instruction. Then when this process is scheduled for the next time, the process is in a no-operation state, and only when this task is scheduled again, that is, when exactly 8 cycles have passed, the process can execute the next instruction. The longer the interval between successful readbacks of memory data, the more wait cycles need to be inserted.

Fig. 2 is a flow chart of executing instructions in the prior art. As shown in Figure 2, it includes the following steps:

Step 201: Fetching instructions and decoding the instructions;

Step 202: Determine whether the instruction is an insert instruction, if yes, execute step 203, if not, execute step 204;

Step 203: inserting a wait cycle behind the put instruction;

Step 204: Execute the instruction and end.

FIG. 2 shows that the operation process of executing the embedded instruction and executing other instructions in the prior art is different. When the placed instruction is not executed, the instruction will be executed directly, and when the placed instruction is executed, other instructions behind the placed instruction can only proceed normally after waiting for the placed instruction to end, so the execution process of the entire pipeline is affected.

Fig. 3 is the time sequence schematic diagram when instruction pipeline is executed in the prior art, as shown in Fig. 3: the pipeline of CPU includes instruction fetch (Fetch), instruction decoding (Decode), read operand (Read), instruction execution (Execute) And write back registers (Write back) these stages. The load instruction shown in FIG. 3 is a kind of put instruction. In the instruction Fetch stage, the load instruction is executed first, and then several instructions such as sub, addic, multi, and addi are executed. In the instruction decoding Decode stage, if it is found that it is a load instruction and the entire insertion operation needs 2 cycles to end, then insert 2 wait-cycles (wait-cycle) after the load instruction, only after these 2 wait-cycles. Start executing the sub command.

The existing technology is to ensure the data consistency during the insert operation by inserting a wait cycle after the insert instruction. If the execution of the CPU instruction is carried out in a single-process manner, this method of inserting the wait cycle is necessary. means, but if under the multi-process mechanism, this method of inserting the waiting period cannot reflect the advantages of multi-process execution at all, because in the prior art, there is a waiting period when the pipeline is executed, and the pipeline cannot execute the setting in the waiting period. Therefore, the efficiency of CPU executing instructions will be greatly affected, thus greatly reducing the efficiency of CPU executing instructions.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method for ensuring data consistency during register file insertion operations under multi-process, so as to improve the efficiency of CPU executing instructions.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

A method for maintaining data consistency during register file placement operations under multi-process, comprising the following steps:

A1. Set the scoreboard flag for the entry of the register file in advance. When inserting the operation, set the value of the scoreboard flag of the destination entry as the occupied value. When the insert operation is completed, set the value of the scoreboard flag of the destination entry. is the idle value;

A2. Determine whether the value of the scoreboard flag of the entry of the register file that the instruction needs to access is an occupied value. If it is an occupied value, set the state of the process executing the instruction to suspend and execute the next process. If it is not an occupied value, execute instruction.

The method for the scoreboard flag bit of the entry of setting register file described in step A1 is: the scoreboard flag bit of D register is set as the entry of register file, or one or more bits of random access memory RAM is set as register file The entry's scoreboard flag.

The method of setting the value of the scoreboard flag position as an occupied value or an idle value described in step A1 is: during the insertion operation, the ALU unit sets the value of the scoreboard flag position as an occupied value, and when the insertion operation is completed, , the LSU unit sets the value of the scoreboard flag to an idle value.

Step A2 is: the ALU unit judges whether the value of the scoreboard flag of the entry of the register file that the instruction needs to access is an occupied value, if it is an occupied value, the LSU unit sends the scoreboard flag occupied signal to the process selection switching module,

The process selection switching module sets the state of the process executing the instruction as suspended and executes the next process according to the occupancy signal of the scoreboard flag position; if it is not an occupancy value, the instruction is executed.

After the processes described in step A2 are suspended, the process switching selection module further judges whether all the processes are suspended, and if so, inserts a null instruction into the instruction execution pipeline, otherwise executes the next process.

The method further includes: after the process hangs, if the insertion instruction is completed, the LSU unit updates the value of the scoreboard flag to an idle value, sends the scoreboard flag idle signal to the process switching selection module, and the process switching selection module judges whether There are other reasons that cause the process to hang, if not, the process switching selection module sets the state of the process as ready; if there is, the process continues to wait until receiving other signals that set the process state as ready.

It can be seen from the above technical solutions that the present invention adopts the method of combining the scoreboard technology and the process suspending mechanism to ensure the data consistency during the multi-process register file insertion operation. First, set the scoreboard flag bit for the entry of the register file. When the instruction is placed into operation, set the value of the scoreboard flag bit of the target entry of the register file of the instruction into the occupied value. After the entry is successfully written back, score The card flag bit is set to an idle value, and when the CPU instruction tries to access the register file entry whose scoreboard flag bit is an occupied value, the process is in a suspended state, and at the same time, in the next cycle, another process is selected for execution instead of the current one. In the prior art, a wait cycle is inserted behind the insert instruction to cause an interruption of the execution of the pipeline instruction. Therefore, after the application of the present invention, the data consistency during the register file insert operation is strictly guaranteed, and the continuous operation of the pipeline is guaranteed. It will cause interruptions in the execution of the pipeline, and will not be affected by the fact that some processes need to enter the waiting state because the corresponding register file entries are not updated in time when the register file is placed into the instruction, thus greatly improving CPU execution. command efficiency.

Description of drawings

FIG. 1 is a schematic diagram of data flow in a register file insertion operation mode.

Fig. 2 is a flow chart of instruction execution in the prior art.

FIG. 3 is a schematic diagram of execution sequence of an instruction pipeline in the prior art.

FIG. 4 is a schematic diagram of CPU multi-process execution.

FIG. 5 is a flowchart of instruction execution according to an embodiment of the present invention.

FIG. 6 is a flow chart of a state change of a process suspended due to needing to access an entry of a register file that has not been updated in accordance with an embodiment of the present invention.

FIG. 7 is a schematic diagram of an execution sequence of an instruction pipeline according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The main idea of the present invention is to strictly guarantee the data consistency of the register file inserting operation by combining the scoreboard flag bit and the process suspension mechanism. First set the scoreboard flag bit for the entry of the register file. When the instruction is placed and executed, the ALU unit will set the scoreboard flag bit of the destination entry of the instruction as the occupied value. After the data is successfully written back to the register file entry, the LSU The unit then sets the scoreboard flag to an idle value. When a CPU instruction tries to access a register file entry whose scoreboard flag is an occupied value, the process executing the instruction is in a suspended state, and in the next cycle it will select another process to execute, only when all other processes When both are suspended, a null instruction is inserted into the pipeline. If not all processes are suspended, the pipeline can execute normally without being affected by the need for the previous process to enter the wait state because the corresponding register file entry content is not updated in time when performing a register file put operation.

The CPU can simultaneously execute multiple hardware processes in a time-division multiplexing manner, and each hardware process can contain multiple software processes. During time division multiplexing, the number of hardware processes can be adjusted accordingly, and the number of software processes can also be adjusted accordingly, and the execution order of the hardware processes is fixed. Assuming that there are 4 hardware processes, FIG. 4 is a schematic diagram of CPU multi-process execution when there are 4 hardware processes. As shown in Figure 4, the CPU can simultaneously execute four hardware processes in one cycle in a time-division multiplexing manner, and the order in which these four hardware processes are executed is fixed. For example, in one cycle, the hardware process process0 is executed first, and then the hardware process process1, the hardware process2 and the hardware process3 are executed sequentially, and one hardware process is executed in each clock (CLK), so each hardware process occupies 25% of the CPU bandwidth. Each hardware process can contain multiple software processes. Assuming that there are 4 hardware processes and the number of software processes included in each hardware process is n, then the entire system includes 4n software processes, and process switching is performed between these 4n software processes. Process switching means that the software process that is not allowed by the condition is given to the software process that is allowed to execute first, that is, the software process that is not allowed by the condition is suspended first, and other software processes are executed first, and then restarted with other software processes when the condition is allowed. Software processes compete for execution together. The switching between processes is switched every other clock cycle by a special process switching selection module according to the resource usage of the CPU.

A software process is always in one of the three states of activation (Active), suspend (Suspend), and preparation (Ready) during execution. After power-on reset, the n software processes corresponding to a hardware process are all in the ready state at the beginning, and then select one software process from the n software processes according to certain principles and migrate its state to the active state, while the software process The suspended state of the process is switched over due to resource conflicts during the execution of the active software process. For example, when the CPU accesses a register that should be updated but has not yet been updated, it is a kind of transition from the active state to the suspended state. When a software process is suspended due to some reason, if the execution condition corresponding to the process is satisfied at a certain moment in the next moment, the state of the software process will immediately change from the suspended state to the ready state. Each clock cycle will select a hardware process from the hardware process, and at the same time select an active software process among the selected hardware processes, and put the selected software process into the next stage of the pipeline so that the next stage can process the software process. On the next clock cycle, a software process is selected from the next hardware process and placed on the next stage of the pipeline.

The present invention strictly guarantees the data consistency when the register file is inserted into the operation mainly through the combination of the scoreboard flag and the process suspending mechanism. When an instruction attempts to access a register file entry whose content has not been updated, the process executing the instruction is suspended, and a scoreboard flag is used to indicate the update status of the contents of the register file target entry placed in the instruction.

The content in the register file can be logically composed of multiple entries, and the scoreboard flag bits of the entries in the register file are preset. The scoreboard flag can be a D register of a register file, or one or more bits of a random access memory (RAM). It is set that when the value of the scoreboard flag bit is 1, it means that the content of the entry of the register file has not been updated, and when the value of the scoreboard flag bit is 0, it means that the content of the entry of the register file has been updated.

Based on the schematic diagram of CPU multi-process execution shown in FIG. 4 , FIG. 5 is a flow chart of instruction execution according to an embodiment of the present invention. As shown in Figure 5, it includes the following steps:

Step 501: Fetch instructions and decode the instructions;

Step 502: judging whether the instruction is an insert instruction, if yes, execute step 503 and its subsequent steps, if not, execute step 504 and its subsequent steps;

Step 503: judging whether the value of the scoreboard flag of the target entry of the instruction is 1, if yes, execute step 508, if not, execute step 505 and its subsequent steps;

Step 504: judging whether the value of the scoreboard flag of the entry of the register file that needs to be accessed is 1, if yes, execute step 508, if not, execute step 509;

Step 505: ALU unit sets the value of the scoreboard flag to 1;

Step 506: Execute the insertion operation;

Step 507: the LSU unit sets the value of the scoreboard flag to 0 and sends the scoreboard flag idle signal to the process switching selection module and ends;

Step 508: The LSU unit sends the scoreboard flag occupation signal to the process switching selection module, and the process switching selection module sets the process status as suspended and terminated;

Step 509: the process executes the instruction and ends.

In the above process, it can also be preset that when the value of the scoreboard flag is 0, it means that the scoreboard flag is occupied, and when the value of the scoreboard flag is 1, it means that the scoreboard flag is free.

In the above process, when the process is suspended, each clock cycle will select a hardware process from the hardware process, and at the same time select an active software process from the selected hardware process, and put the selected software process into the pipeline The next level of , so that the next level can handle this software process.

In the above process, an entry in the register file may also correspond to more than one scoreboard flag. When an entry corresponds to multiple scoreboard flags, when the insert instruction writes the entry, all the scoreboard flags corresponding to this entry are set to the preset occupancy value, and when the insert instruction finishes writing When entering this entry, set all the scoreboard flags corresponding to this entry to the preset free values.

In the above process, after step 508, the process switch selection module can further judge whether all processes have been suspended, if so, insert a null instruction in the pipeline, otherwise execute the next selected software process.

When a process tries to access an entry in the register file, the ALU unit judges whether the value of the scoreboard flag of the entry in the register file that the instruction needs to access is an occupied value. If it is an occupied value, the LSU unit sends the scoreboard flag to the process selection switching module bit occupation signal, the process is suspended, and the process switching selection module records the reason for the process suspension. When the LSU unit finishes updating the entries of the register file, the LSU unit updates the scoreboard flag and sends the scoreboard flag idle signal to the process switching selection module, and the process switching selection module will determine that the process is suspended when it receives this signal This reason no longer exists, and will judge simultaneously whether there are other reasons that cause the process to hang, if there are no other reasons that cause the process to hang, the process switching selection module is set to the state of the process from being suspended to preparing.

Based on what is shown in FIG. 4 and FIG. 5 , FIG. 6 is a flow chart of a process state change that is suspended due to the need to access an entry of a register file that has not been updated, according to an embodiment of the present invention. As shown in Figure 6, the following steps are included:

Step 601: when the process is suspended because the value of the scoreboard flag of the entry of the register file to be accessed is an occupied value, the process switching selection module records the reason for the process suspension;

Step 602: After the entry of the register file is updated, the LSU unit updates the value of the scoreboard flag to be an idle value and sends a scoreboard flag idle signal to the process switching selection module;

Step 603: The process switching selection module judges whether there are other reasons for process suspension, if so, execute step 604, otherwise execute step 605;

Step 604: The process continues to save the suspended state, waits for other signals to change the process state and ends;

Step 605: The process switching selection module sets the process state as ready and finished according to the scoreboard flag idle signal sent by the LSU unit.

When the state of the process is ready, the process switching selection module can execute the process according to a certain selection principle.

FIG. 7 is a schematic diagram of an execution sequence of an instruction pipeline according to an embodiment of the present invention. As shown in Figure 7, the sub instruction is executed immediately after the load instruction is executed in the Decode stage of instruction decoding, without inserting any waiting cycle. In this case, the entire pipeline of the CPU executes the load instruction the same as executing other instructions, and has no effect on the entire pipeline, and the efficiency will not be reduced due to the insertion of waiting cycles.

In the above process, 4 hardware processes are taken as an example to illustrate the switching between CPU multi-process processes. In fact, the number of hardware processes can be adjusted accordingly, and the number of software processes can also be adjusted accordingly.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. Keep the method for data consistency when 1, register file is inserted operation under a kind of multi-process, it is characterized in that, may further comprise the steps:

   A1, in advance for item in register file is provided with the scoreboard zone bit, the value of inserting the scoreboard zone bit of when operation purpose clauses and subclauses is set to the value of taking, and inserts operation when finishing, the value of the scoreboard zone bit of purpose clauses and subclauses is set to free value;

   Whether the value of the scoreboard zone bit of the item in register file that A2, decision instruction need be visited is the value of taking, if the value of taking then is provided with the process status of this instruction of execution for hanging up and carrying out next process, then executes instruction if not the value of taking.
2. 2, method according to claim 1, it is characterized in that the steps A 1 described method that the scoreboard zone bit of item in register file is set is: the D register is set to the scoreboard zone bit of item in register file or with the one or more scoreboard zone bits that are set to item in register file of random access memory ram.
3. 3, according to right 1 described method, it is characterized in that, the method that the value of steps A 1 described scoreboard zone bit is set to the value of taking or free value is: when inserting operation, the value of the described scoreboard zone bit in ALU unit is set to the value of taking, insert and operate when finishing, the value of the described scoreboard zone bit in LSU unit is set to free value.
4. 4, according to right 1 described method, it is characterized in that steps A 2 is: whether the value of the scoreboard zone bit of the item in register file that the instruction of ALU unit judges need be visited is the value of taking, if the value of taking, the LSU unit sends scoreboard zone bit Seize ACK message to the process selection handover module

   It is to hang up and carry out next process that the process selection handover module is provided with the process status of carrying out this instruction according to described scoreboard zone bit Seize ACK message; Then execute instruction if not the value of taking.
5. 5, according to right 1 described method, it is characterized in that after the described processes of steps A 2 were hung up, process switching selected module to judge whether that further all processes all hang up, if then insert dummy instruction, otherwise carry out next process at the instruction execution pipeline.
6. 6, according to right 3 described methods, it is characterized in that, this method further comprises: after process is hung up, if inserting instruction finishes, then the LSU unit is updated to free value with the value of scoreboard zone bit, selects module to send scoreboard zone bit idle signal to process switching, and process switching selects module to judge whether to also have other to cause the reason that process is hung up, if no, process switching selects module state of a process to be set for preparing; If have, process continue to wait for, process status is set is preparative until receiving other.

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