CN1581699B - Phase phagocytosis device and signal generating device using the phase phagocytosis device - Google Patents

Abstract

A phase swallowing device capable of reducing the jitter of an output clock and a signal generating device using the phase swallowing device. The signal generating device comprises a multi-phase clock generator, which receives a reference clock and generates a plurality of multi-phase reference clocks with the same frequency but different phases; a multiplexer, which receives a plurality of multi-phase reference clocks and selects a reference clock output from the plurality of multi-phase reference clocks according to a phase selection signal; a phase swallowing control unit, which has a comparison unit and receives a phase swallowing amount and generates a phase control signal; and a clock selection unit, which receives the phase control signal and generates the phase selection signal. The comparison unit generates the phase control signal according to the phase swallowing amount and a reference signal, and the reference signal is compared with the phase swallowing amount in a non-bit order, so the phase control signal is not continuous and can be regarded as evenly distributed, thereby reducing the periodic jitter of the output signal of the signal generating device.

Description

Phase phagocytosis device and signal generating device using the phase phagocytosis device

technical field

The present invention relates to a phase devouring device and a signal generating device, in particular to a phase devouring device capable of reducing the jitter of an output clock and a signal generating device using the phase devouring device.

Background of the invention

FIG. 1 is a structural diagram of a conventional signal generating device. The signal generating device 10 is used to generate a frequency synthesis clock, and the frequency of the clock can be adjusted according to requirements. The signal generating device 10 includes a multi-phase clock generator (multi-phase clock generator) 11, a multiplexer (multiplexer) 12, a phase-swallow control unit (phase-swallow control unit) 14, and a clock selection unit (clock selector) 15. The multi-phase clock generation unit 11 generates a plurality of multi-phase reference clocks CKn-1, CKn-2, . . . , CK0 with the same frequency but different phases according to a reference clock. FIG. 2 shows waveforms of 8 multi-phase reference clocks CK7 , CK6 , . . . CK0 with different phases. The multiplexer 12 receives a plurality of multi-phase reference clocks CKn-1, CKn-2..., CK0, and selects a clock output of the multi-phase reference clocks according to a phase selection signal, so as to generate an output clock signal of. The phase swallow control unit 14 generates a phase control signal (swallow control signal, SCS) according to the amount of phase swallow. The clock selection unit 15 then outputs a phase selection signal according to the phase control signal SCS. The clock selection unit 15 can be a counter and uses the phase control signal as a trigger signal. When the phase control signal is enabled, the counter is incremented by 1, so the phase selection signal is also incremented by 1, so that the multiplexer 12 selects the reference clock of the next phase as the output clock signal. In this way, according to the enabling times of the phase control signal, the frequency of the output clock signal of the signal generating device 10 can be fine-tuned.

Generally, a traditional phase engulfing control unit can use a sigma-delta modulator (sigma-delta modulator) to achieve precise control of the output frequency and a small cycle jitter. If the first-order sigma-delta modulator is taken as an example, its embodiment It can be an accumulator (Accumulator), and its circuit area is still larger than general logic elements (AND gate, OR gate, flip-flop).

For circuit design requirements that require a small circuit size, a conventional phase engulfment control unit is implemented using a counter (which can be regarded as a plurality of flip-flops), please refer to FIG. 3 . FIG. 3 is a block diagram of the phase engulfment control unit in FIG. 1 . As shown in the figure, the phase swallowing control unit 14 includes a counter 31 , a comparator 32 , and a register 33 . The counter 31 counts the number of clock pulses of the clock signal, and outputs a reference signal to the comparator 32 . And the temporary register 33 is to temporarily store the phase engulfing amount. The comparator 32 compares the reference signal output by the counter 31 with the phase swallowing value of the register 33 . That is, when the reference signal is smaller than the phase swallowing amount, the phase control signal SCS is enabled; otherwise, when the reference signal is greater than or equal to the phase swallowing amount, the phase control signal SCS is disabled. Therefore, as shown in FIG. 3, the low bit of the reference signal is compared with the low bit of the phase swallow, and the high bit of the reference signal is compared with the high bit of the phase swallow.

In the architecture of Figure 3, the engulfment is continuous due to its phase. For example, if the phase difference is 3 phases, then the conventional phase swallowing method is to swallow one phase in each of 3 consecutive clock cycles. Therefore, the cycle-cycle jitter of the output clock of the signal generating device 10 is relatively large. Designed according to system requirements, the output clock signal can be divided by an appropriate value to achieve the required frequency. That is, a frequency divider (not shown in the figure) is used to receive the clock signal output by the multiplexer 12 and perform frequency division. When 8 clock cycles continuously swallow 3 phases, and the frequency divider is divided by 3, the maximum period jitter is 3ΔT, where ΔT is the difference between two adjacent multi-phase reference clocks Phase difference. Moreover, the more phases are swallowed, the greater the amount of maximum period jitter.

Therefore, it is an important subject to meet the requirement of a small circuit size and to effectively reduce the amount of period jitter.

Contents of the invention

An object of the present invention is to provide a phase devouring device capable of reducing the amount of period jitter and a signal generating device using the phase devouring device.

A phase devouring device provided by the present invention is to receive a plurality of multi-phase reference clocks and generate an output clock, and these multi-phase reference clocks have the same frequency and different phases. The phase devouring device includes:

A multiplexer is used to receive the multi-phase reference clocks, and select a reference clock output of the multi-phase reference clocks according to a phase selection signal as the output clock; and

A phase engulfing control unit outputs the phase selection signal after comparing the phase engulfing amount with the reference signal in a non-bit sequential manner according to a phase engulfing amount and a reference signal.

The phase devouring device further includes a counter for outputting the reference signal.

The phase engulfment control unit compares the bits of the reference signal with the corresponding bits of the phase engulfment in a bit reverse order.

A signal generating device comprising:

A multi-phase clock generator, which receives a reference clock and generates a plurality of multi-phase reference clocks with the same frequency but different phases;

A multiplexer, receiving the multi-phase reference clocks, and selecting a reference clock output of the multi-phase reference clocks according to a phase selection signal as the output clock;

A phase engulfment control unit has a comparison unit and receives a phase engulfment amount, and generates a phase control signal; and

a clock selection unit, receiving the phase control signal and generating the phase selection signal;

Wherein, the comparison unit compares the phase engulfment amount with a reference signal in different bit order, and outputs the phase control signal.

Both the phase engulfment amount and the reference signal are signals with a plurality of bits, and the phase engulfment control unit includes a plurality of bit comparison units for comparing the mth bit of the phase engulfment amount and the reference signal to output the phase control signal, where m and n are both positive integers, and m is not equal to n.

In the signal generating device, the different bit order is bit reverse order.

The signal generating device further includes a counter for outputting the reference signal.

The phase engulfment control unit further includes a register for storing and outputting the phase engulfment amount.

In the phase engulfment control unit, the comparator compares the reference signal and the phase engulfment amount in different bit order, so the phase control signal generated by the phase engulfment control unit is not continuous, and can be regarded as evenly distributed, so as to reduce the signal generation The amount of period jitter in the output signal of the device.

Description of drawings

FIG. 1 is a structural diagram of a conventional signal generating device;

FIG. 2 is a schematic diagram of waveforms of a plurality of multi-phase clocks;

Fig. 3 is a block diagram of a conventional phase engulfment control unit;

Fig. 4 shows the structural diagram of the signal generating device of the present invention;

Fig. 5 shows the schematic diagram of the phase phagocytosis control unit of Fig. 4;

Fig. 6 shows the value of the counter received by the comparator of Fig. 5;

FIG. 7 shows a schematic diagram of phase phagocytosis corresponding to different phase phagocytosis amounts, wherein the oblique area is the area where the phase control signal SCS is enabled, and N is the phase phagocytosis amount.

Detailed ways

The phase devouring device of the present invention and the signal generating device using the phase devouring device will be described in detail below with reference to the accompanying drawings.

Since the phase swallowing in the conventional architecture is continuous, the period jitter is relatively large. Therefore, in order to reduce the period jitter, the present invention proposes a structure to disperse the phase phagocytosis.

FIG. 4 shows the structure diagram of the signal generating device of the present invention. The signal generating device 40 of the present invention includes a multi-phase clock generating unit 41 , a phase swallowing device 42 , and a frequency divider 43 . The phase devouring device 42 includes a multiplexer 421 , a phase devouring control unit 422 , and a clock selection unit 423 . The multi-phase clock generation unit 41 generates a plurality of multi-phase reference clocks CKn-1, CKn-2, . . . , CK0 with the same frequency but different phases according to a reference clock. The multiplexer 421 receives a plurality of multi-phase reference clocks, and selects a reference clock output of the multi-phase reference clocks according to a phase selection signal. The phase swallowing control unit 422 generates a phase control signal SCS according to the amount of phase swallowing. The clock selection unit 423 then outputs a phase selection signal according to the phase control signal SCS. The difference between the signal generation device 40 of the present invention and the conventional signal generation device is that the phase control signal generated by the phase engulfment control unit 422 is scattered and not continuous. Since the structures and functions of the multi-phase clock generating unit 41 , the multiplexer 421 , the frequency divider 43 , and the clock selecting unit 423 of the signal generating device 40 are the same as those of the conventional signal generating device, the description will not be repeated here.

FIG. 5 shows a schematic diagram of the phase engulfment control unit of FIG. 4 . As shown in the figure, the phase swallowing control unit 422 includes a counter 51 , a comparator 52 , and a register 53 . The counter 51 counts the number of clock pulses of the clock signal, and outputs the count value (reference signal) to the comparator 52 . And the temporary register 53 is to temporarily store the phase engulfing amount. The difference between the phase engulfment control unit 422 and the phase engulfment control unit in FIG. 3 is that the order of the high and low bits of the counter 51 connected to the comparator 52 is reversed. That is, the lowest bit C0 of the counter 51 is connected to A2 of the comparator 52, the second lowest bit C1 of the counter 51 is connected to A1 of the comparator 52, and the highest bit C2 of the counter 51 is connected to A0 of the comparator 52; The lowest bit D0 of the register 53 is connected to B0 of the comparator 52 , the second lowest bit D1 of the register 53 is connected to B1 of the comparator 52 , and the highest bit D2 of the register 53 is connected to B2 of the comparator 52 . Figure 6 shows the value of the counter received by the comparator. As shown in FIG. 6 , the clock signal is input into the comparator 52 in bit reverse order to be compared with the phase engulfing amount, so the count value will be scattered. According to this characteristic, after the comparator compares the count value and the phase swallowing amount, the output signal of the comparator is not continuous, and it can be regarded as distributed distribution. Of course, the implementation method of the circuit is not limited to the above-mentioned description, and the phase engulfment and the reference clock are not in the bit sequence, and logical operations such as AND gate or inverse OR gate are used, and it does not depart from the present invention. The spirit of the proposed use of non-bit ordering to achieve scatter effects.

FIG. 7 shows phase inhibition situations corresponding to different phase phagocytosis amounts, where the oblique area is the area where the inhibition control signal SCS is enabled, and N is the phase phagocytosis amount. The situation shown in FIG. 7 assumes that there are 8 multi-phase reference clocks. As shown in Figure 7, the time points of phase engulfment are spread out. In the conventional architecture, the maximum amount of period jitter is proportional to the number N of phases swallowed. And the maximum period jitter of the present invention has two situations, when the divisor of the frequency divider is an even number, its maximum period jitter is 0 or a ΔT, wherein ΔT is the phase difference of two adjacent multi-phase reference clock pulses . And when the divisor of the frequency divider is an odd number, its maximum period jitter is 2ΔT.

Therefore, the output clock generated by the signal generating device of the present invention can effectively reduce the amount of jitter. Although the present invention has been described above with examples, the scope of the present invention is not limited thereto. Those in the industry can make various modifications or changes as long as they do not depart from the gist of the present invention.

Claims (13)

1. a phase place is engulfed device, receives a plurality of leggies with reference to clock pulse, and produces an output clock pulse, and leggy is identical with reference to the frequency of clock pulse, phase place is different, it is characterized in that this phase place engulfs device and comprise:

One multiplexer receives leggy with reference to clock pulse, and selects leggy to export with reference to clock pulse with reference to one in the clock pulse according to a Selecting phasing signal, as described output clock pulse; And

One phase place is engulfed control unit, according to a phase place amount of engulfing and a reference signal, and by non-bit mode sequentially, relatively after this phase place amount of engulfing and this reference signal, produces phase control signal; And

Timing selection unit is exported this Selecting phasing signal according to this phase control signal.

2. phase place as claimed in claim 1 is engulfed device, it is characterized in that this phase place amount of engulfing and this reference signal are all the signal with a plurality of bits, and this phase place is engulfed control unit and is comprised a plurality of bit comparing units, in order to relatively the m bit of this phase place amount of engulfing and the n bit of this reference signal, to export this Selecting phasing signal, wherein, m, n is all positive integer, and m is not equal to n.

3. phase place as claimed in claim 2 is engulfed device, it is characterized in that this phase place engulfs control unit and also comprise a buffer, in order to store and to export this phase place amount of engulfing.

4. phase place as claimed in claim 2 is engulfed device, it is characterized in that this phase place engulfs control unit and also comprise a counter, in order to export this reference signal.

5. phase place as claimed in claim 1 is engulfed device, it is characterized in that it is that the order that a plurality of bits of this reference signal are put upside down with the height bit is made comparisons with corresponding a plurality of bits of this phase place amount of engulfing that this phase place is engulfed control unit.

6. signal generation device is characterized in that comprising:

One leggy clock pulse generator receives one with reference to clock pulse, and produces identical but the leggy that phase place is different of a plurality of frequencies with reference to clock pulse;

One multiplexer receives these a plurality of leggies with reference to clock pulse, and according to a Selecting phasing signal select these a plurality of leggies with reference to clock pulse one with reference to clock pulse output, as the output clock pulse;

One phase place is engulfed control unit, has a comparing unit and receives a phase place amount of engulfing, and produce a phase control signal; And

Timing selection unit receives this phase control signal, and produces this Selecting phasing signal;

Wherein, this phase place is engulfed control unit the phase place amount of engulfing that receives is offered described comparing unit, and described comparing unit is with non-bit order relatively this phase place amount of engulfing and a reference signal, and exports this phase control signal.

7. signal generation device as claimed in claim 6, it is characterized in that this phase place amount of engulfing and this reference signal are all the signal with a plurality of bits, and this comparing unit is the comparing unit with a plurality of bits, in order to relatively the m bit of this phase place amount of engulfing and the n bit of this reference signal, to export this phase control signal, wherein, m, n is all positive integer, and m is not equal to n.

8. signal generation device as claimed in claim 6 is characterized in that this non-bit sequentially is the bit reverse sequence.

9. signal generation device as claimed in claim 6 is characterized in that this phase place engulfs control unit and also comprise a counter, in order to export this reference signal.

10. signal generation device as claimed in claim 6 is characterized in that this phase place engulfs control unit and also comprise a buffer, in order to store and to export this phase place amount of engulfing.

11. a signal generating method is characterized in that comprising:

According to one with reference to clock pulse to produce identical but the leggy that phase place is different of a plurality of frequencies with reference to clock pulse;

Foundation one Selecting phasing signal is to select these a plurality of leggies to export clock pulse with reference to clock pulse as one with reference to one in the clock pulse;

After coming the comparison one phase place amount of engulfing and a reference signal by the mode of non-bit order, export this Selecting phasing signal.

12. signal generating method as claimed in claim 11, it is characterized in that this phase place amount of engulfing and this reference signal are all the signal with a plurality of bits, relatively the m bit of this phase place amount of engulfing and the n bit of this reference signal, to export this phase control signal, wherein, m, n is all positive integer, and m is not equal to n.

13. such as claim the 11 described signal generating methods, it is characterized in that the order that non-bit is sequentially put upside down for the height bit.

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