CN1553575A - Surge-free circuit capable of reducing electromagnetic interference - Google Patents

Abstract

The invention discloses a surge-free circuit capable of reducing electromagnetic interference, which comprises a first trigger stage, a time sequence delay device, a logic group and a second trigger stage. The first flip-flop stage is triggered by a first edge of a pulse signal. The timing delay device is electrically connected to the first flip-flop stage and is triggered by a second edge of the pulse signal relative to the first edge. The timing delay device shifts the input signal switching the logic level between the first edge and the second edge of the pulse signal by half a period. The logic group is electrically connected to the timing delay circuit. The second flip-flop stage is electrically connected to the logic group and is triggered by a first edge of the pulse signal.

Description

Glitch-free circuitry to reduce EMI

technical field

The present invention relates to a synchronous circuit, in particular to a logic circuit which maintains low electromagnetic interference by eliminating surges in the internal circuit.

Background technique

其中T代表突波的宽度。Synchronous circuits have been widely used in VLSI and ULSI designs due to their fast, easy design and ease of handling by CAD tools. However, synchronous circuits have some inherent problems, such as clock skew and racing problems, large switching currents, high power consumption, and surges between internal logic gates. The glitch of the internal logic gate is usually caused by two input signals switching to different logic levels within a short period of time. In most cases, glitches in the internal logic gates cause electromagnetic interference. This EMI is proportional to

Where T represents the width of the burst.

Please refer to FIG. 1 , which shows a logic circuit including a first flip-flop stage 11 , a logic group 12 and a second flip-flop stage 13 . For the synchronous function, the flip-flops 111 , 112 and 113 in the first flip-flop stage 11 and the flip-flop 131 in the second flip-flop stage 13 are all designed to be rising edge triggered. An input terminal of a NAND gate (NAND gate) 121 is connected to outputs A and -B of flip-flops 111 and 112 . An input terminal of a NAND gate 122 is connected to the output D of the NAND gate 121 and the output B of the flip-flop 112 . An input terminal of a NOR gate (NORgate) 123 is connected to the output E of the NAND gate 122 and the output C of the flip-flop 113 . Finally, the output F of the NOR gate 123 is used as the input of the flip-flop 131 .

FIG. 2 shows a timing diagram of the logic circuit of FIG. 1 . Wherein the voltage of the signal C drops from high level to low level at the rising edge of the pulse signal (marked as CK), but the voltage of the other input terminal E of the NOR gate 123 is at the rising edge of the pulse signal after a time difference. Rise from low level to high level. This time difference causes a spike in the signal F, which further causes electromagnetic interference.

In other words, if the input terminals of the existing circuit switch their voltages to opposite logic levels at different time points, it will inevitably cause surges in the internal circuit. In order to solve the above problems, the present invention proposes a novel surge-free circuit to reduce electromagnetic interference.

Contents of the invention

The main purpose of the present invention is to provide a surge-free circuit for meeting the market demand for low electromagnetic interference.

A second object of the present invention is to provide a glitch-free circuit, which can avoid unknown states during circuit simulation.

In order to achieve the above purpose, the surge-free circuit capable of reducing electromagnetic interference disclosed by the present invention includes a first flip-flop stage, a timing delay device, a logic group and a second flip-flop stage. The first flip-flop stage is triggered by a first edge of a pulse signal. The timing delay device is electrically connected to the first flip-flop stage, and is triggered by a second edge of the pulse signal relative to the first edge. The timing delay device shifts the switching logic level of the input signal by half a period between the first edge and the second edge of the pulse signal. The logic group is electrically connected to the timing delay circuit. The second flip-flop stage is electrically connected to the logic group and is triggered by the first edge of the pulse signal.

The first edge of the pulse signal can be selected from a rising edge or a falling edge of the pulse signal, and the second edge of the pulse signal is an unselected part thereof.

Description of drawings

The invention will be described with reference to the accompanying drawings, in which:

Fig. 1 is an existing circuit diagram;

Fig. 2 shows the timing diagram of the logic circuit of Fig. 1;

Fig. 3 shows the surge-free circuit of the first embodiment of the present invention;

Fig. 4 shows the timing diagram of the logic circuit of Fig. 3;

5(a) and 5(b) show the circuit diagram of the timing delay device of the second embodiment of the present invention; and

6(a) and 6(b) are circuit diagrams of a timing delay device according to a third embodiment of the present invention.

Detailed ways

FIG. 3 shows the glitch-free circuit of the first embodiment of the present invention. The difference from the conventional circuit in FIG. 1 is that the present invention adds a timing delay device 31 between the first flip-flop stage 11 and the logic group 12 . The first data latches 311 and 313 (a flip-flop can also be used) and the second data latch 312 (a flip-flop can also be used) in the timing delay device 31 are triggered by the falling edge of the pulse signal. The input terminal of the first data latch 311 is further connected to a preset terminal point (marked as the S point of the data latch), which represents that when the pulse signal is at a high level, if the input A is currently at a logic high level , or input A was logic high level in the previous cycle but is logic low level in this cycle, then output A1 is also logic high level. The input end of this second data latch 312 is connected to a reset terminal (marked as the RN of this data latch) in addition, and it represents when the pulse signal is low level, if this moment input B is low level, or Input B was low in the previous cycle but high in this cycle, then output BO is logic low.

The input terminal of the data latch 313 is connected to its preset terminal in addition, and it shows that when the pulse signal is high level, if the input C is high level at this time, or the input C was high level in the previous cycle but this time When it is low level, the output C1 is high level. The consideration in choosing to connect the input to the preset or reset terminal is what type of logic gate the data latch is connected to. If the logic gate outputs to an AND gate or a NAND gate, the input terminal is connected to the reset terminal. If the data latch outputs to an OR gate or a NOR gate, the input terminal is connected to the preset terminal.

FIG. 4 shows a timing diagram of the logic circuit of FIG. 3 . It is obvious that the spike in signal F in FIG. 2 disappears, and this result eliminates the aforementioned electromagnetic interference. In other words, the first data latch 313 of the timing delay device 31 shifts the falling edge of the signal C1 by half a cycle, so as to avoid the logic level transition of the signal C1 when the pulse signal is at a high level. Therefore, even if the signal E starts to change from a logic low level to a high level after a period of time relative to the signal C, the surge will not occur.

FIG. 5(a) and FIG. 5(b) show the surge-free circuit of the second embodiment of the present invention. FIG. 5( a ) shows a possible implementation of the data latches 311 and 313 , which includes a pulse-controlled latch 51 . When the pulse signal is low, the pulse-controlled latch 51 exhibits a buffer behavior. However, when the pulse signal is at a high level, if the input A is at a logic high level at this time, or if the input A was at a logic high level in the previous cycle but is at a logic low level in this cycle, the output A1 will display a logic high level. flat. FIG. 5( b ) shows another possible implementation of the second data latch 312 , which includes another pulse-controlled latch 52 . When the pulse signal is low, the pulse-controlled latch 52 exhibits a buffer behavior. However, when the pulse signal is high, if input B is logic low at this time, or input B was logic low in the previous cycle but this cycle is logic high, then output B0 shows a logic low flat.

FIG. 6( a ) and FIG. 6( b ) are circuit diagrams of a timing delay device according to a third embodiment of the present invention. FIG. 6( a ) shows a possible implementation of the first data latches 311 and 313 comprising a pulse-controlled complementary metal-oxide-semiconductor (also known as C ² MOS) 61 . When the pulse signal is at low level, the pulse controls the CMOS 61 to behave as a buffer. However, when the pulse signal is high, if input A is logic high at this time, or input A was logic high in the previous cycle but is currently logic low due to charge storage in stray capacitance, then Output A1 exhibits a logic high level. FIG. 6( b ) shows a possible implementation of the second data latch 312 comprising a pulsed metal oxide semiconductor (also called C ² MOS) 62 . When the pulse signal is at low level, the pulse controls the MOS 62 to function as a buffer. However, when the pulse signal is at a high level, if the input B is at a logic low level at this time, or the input B was at a logic low level in the previous cycle but the current cycle is at a logic high level due to the charge storage effect of the stray capacitance, Then the output BO shows a logic low level.

Another advantage of the invention is that the simulation screen will be easier to read. In most cases, if the simulation screen has an unknown state due to a surge, the unknown state will propagate to the logic gates connected to it, making the simulation waveform difficult to read, and making it impossible for the designer to find out where the original surge occurred Location. The present invention can avoid the generation of surge, and provide a designer with a clearer simulation environment, so that the designer can conveniently detect the error of his circuit.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various replacements and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the content disclosed in the embodiments, but should include various replacements and modifications that do not depart from the present invention, and are covered by the claims of this patent application.

Claims (11)

1. A surge-free circuit capable of reducing electromagnetic interference, comprising: a first flip-flop stage, triggered by the first edge of a pulse signal; a logic group; and a second flip-flop stage, electrically connected to the Logic group, and triggered by the first edge of the pulse signal, characterized in that: Also includes a timing delay device, electrically connected between the first flip-flop stage and the logic group, and triggered by a second edge of the pulse signal relative to the first edge, the timing delay device is at the pulse The input signal switching logic level is shifted by half period between the first edge and the second edge of the signal. 2. The glitch-free circuit according to claim 1, wherein the timing delay device comprises a first flip-flop, if the input signal of the timing delay device is logic high before the first edge of the pulse signal level, the first flip-flop outputs a logic high level between the first edge and the second edge of the pulse signal. 3. The glitch-free circuit according to claim 1, wherein the timing delay device comprises a first data latch, if the input signal of the timing delay device is logic before the first edge of the pulse signal high level, the first data latch outputs a logic high level between the first edge and the second edge of the pulse signal. 4. The glitch-free circuit according to claim 1, wherein the timing delay device comprises a second flip-flop, if the input signal of the timing delay device is logic low before the first edge of the pulse signal level, the second flip-flop outputs a logic low level between the first edge and the second edge of the pulse signal. 5. The glitch-free circuit according to claim 1, wherein the timing delay device comprises a second data latch, if the input signal of the timing delay device is logic before the first edge of the pulse signal low level, the second data latch outputs a logic low level between the first edge and the second edge of the pulse signal. 6. The glitch-free circuit according to claim 3, wherein the first data latch is electrically connected to an OR gate or a NOR gate of the logic group. 7. The glitch-free circuit of claim 5, wherein the second data latch is electrically connected to an AND gate or a NAND gate of the logic group. 8. The glitch-free circuit according to claim 3, wherein the first data latch is electrically connected to its input terminal to its preset terminal. 9. The glitch-free circuit according to claim 5, wherein the second data latch is electrically connected from its input terminal to its reset terminal. 10. The glitch-free circuit of claim 1, wherein the timing delay device comprises a pulse-controlled latch. 11. The glitch-free circuit of claim 1, wherein the timing delay means comprises a pulse-controlled CMOS.

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