CN1327353C

CN1327353C - Microprocessor device with optional recall of prefetch

Info

Publication number: CN1327353C
Application number: CNB2003101014821A
Authority: CN
Inventors: 罗德尼·E·胡克; G·葛兰·亨利
Original assignee: IP First LLC
Current assignee: IP First LLC
Priority date: 2003-04-21
Filing date: 2003-10-17
Publication date: 2007-07-18
Anticipated expiration: 2023-10-17
Also published as: CN101063956A; CN1514369A; CN100489813C

Abstract

A microprocessor capable of selectively retiring a prefetched cache line is disclosed. In a first embodiment, a first count and a second count are maintained, wherein the first count counts accesses to the prefetched cache line and the N second counts accesses to N cache lines in an alternate reserve set of the cache, the N cache lines in the reserve set being selected by an address of the prefetched cache line, and the reserve prefetched cache line is retired back into the cache if the first count is greater than a minimum of the N second counts when another prefetch is requested; otherwise, the prefetched cache line is discarded. In a second embodiment, a count of the number of alternative reserved cache lines is maintained, and when another prefetch is requested, the reserved prefetch cache line is evicted back to the cache if the count is greater than a programmable threshold value; otherwise, the prefetched cache line is discarded.

Description

The micro processor, apparatus of selective prefetch retire

Technical field

The present invention relates to the field of high-speed cache (cache), refer to the computing of looking ahead (prefetching) of fast line taking (cache line) especially, promptly relate to the micro processor, apparatus of selective prefetch retire.

Background technology

Included a microprocessor and an Installed System Memory in the computer system of today, this Installed System Memory is in order to store microprocessor instruction and to be the handled data of this microprocessor instruction.In general, from required time of Installed System Memory reading of data can more than microprocessor carry out the required time of one or more instruction want many-in some cases, be even more than ten times or 20 times, therefore, when from the Installed System Memory loading data, microprocessor often is to be in idle state, and this kind situation is very inefficent, and can reduce the performance of system.

For relaxing the influence of the problems referred to above to system, can in microprocessor, make up a high-speed cache usually, this high-speed cache is built in the microprocessor in being, and its memory capacity is less than Installed System Memory, in order to a subclass of stocking system internal memory institute deposit data.When processor must be taken data carrying out an instruction, this processor at first can check whether this desired data is present in this high-speed cache from a previous data load, was referred to as " cache hit " (cache hit) as this step 1.If in this previous data load, desired data " hits " this high-speed cache, in other words, be that desired data has been deposited in this high-speed cache, this instruction this moment can be performed immediately, if but in this previous data load, desired data " in getting not soon " is this high-speed cache (miss), then delay the execution of this instruction again, obtain desired data in processor from Installed System Memory to wait for.

The designer of microprocessor knows that software program often is successional to the access of data and instruction; therefore; if during a data load is miss this high-speed cache; then and then the data on the memory address of the miss address of this data load (load miss address) probably soon can be required by this program; so a microprocessor is anticipated following demand to next data; therefore even in program still before next data of failed call; regular meeting in advance and then the data block subsequently of this miss address date be loaded in its high-speed cache, this action generally is referred to as look ahead (prefetch).

The size of the data block that this is prefetched normally is equal to the size of a fast line taking, and high-speed cache is with in the fast line taking of data storing, and the size of general fast line taking often is 32 bytes or 64 bytes.Fast line taking is the least unit of the data that can transmit between this high-speed cache and this Installed System Memory, in other words, when the be cached data of desiring to read when a microprocessor are not present in its high-speed cache, this microprocessor promptly can read from Installed System Memory and comprise the whole fast line taking that this can be cached data, and should fast line taking be stored in its high-speed cache, similarly, in the time a new fast line taking need being written to its high-speed cache, promptly can cause being substituted of a fast line taking that was modified, this moment, microprocessor also was written to Installed System Memory with whole this substituted fast line taking.

Traditionally, this fast line taking of looking ahead all is regarded as being equal to a common fast line taking and fills (line fill).One common fast line taking is filled to a fast line taking of extracting from Installed System Memory, because an instruction is from this fast line taking access data, so utilize a common fast line taking to fill, this fast line taking that is extracted can unconditionally be written into or be retracted into its high-speed cache.Unconditionally recall the fast line taking of looking ahead in advance and have a shortcoming to its high-speed cache, this shortcoming may replace a fast line taking that just is being used or is being about to be used for this fast line taking that is withdrawn, thereby may adverse influence be arranged to the efficient of high-speed cache.Therefore, desire is improved the efficient of high-speed cache, must solve this shortcoming.

Summary of the invention

In one first specific embodiment of the present invention, the present invention can distinguish look ahead fast line taking and a common fast line taking and fill, and access (contemporaneous access) when this is looked ahead fast line taking, the present invention fast line taking of optionally this being looked ahead is withdrawn into its high-speed cache.In one second specific embodiment of the present invention, access based on to the fast line taking of one in this high-speed cache the time, and this fast line taking will be by being replaced by this fast line taking of looking ahead, and this fast line taking of looking ahead is optionally to recall.Therefore, for reaching above-mentioned purpose, the invention provides a microprocessor, this microprocessor comprises that a high-speed cache and is coupled to the prefetch buffer of this high-speed cache, and this prefetch buffer is in order to receive from one of an Installed System Memory fast line taking of looking ahead.This microprocessor also comprises the steering logic device that is coupled to this prefetch buffer, this steering logic device be according in fact simultaneously access this look ahead fast line taking with look ahead this fast line taking of looking ahead to this prefetch buffer, be retracted into its high-speed cache with fast line taking that this is looked ahead.

On the other hand, the invention provides a kind of device in a microprocessor, this device is according to an access of looking ahead fast line taking, optionally a plurality of fast line takings of looking ahead are withdrawn into a high-speed cache of this microprocessor.This device comprises a prefetch buffer, and this prefetch buffer is in order to store the fast line taking of looking ahead.This device comprises that also one is coupled to a buffer of this prefetch buffer, and this buffer is in order to store a prefetch address of this fast line taking of looking ahead.This device also comprises the steering logic device that is coupled to this buffer, and this steering logic device receives the access address of a memory access computing, and this access address and this prefetch address are done one relatively.This device also comprises a counter that is coupled to this steering logic device, and this counter is in order to store the counting of this fast line taking of looking ahead of an access.If this access address is identical with this prefetch address, then this steering logic device increases the counting of this counter.This steering logic device and be withdrawn into this high-speed cache with the fast line taking of optionally this being looked ahead according to this counting.

Again on the other hand, the invention provides a kind of device in a microprocessor, this device can be optionally be withdrawn into a high-speed cache of this microprocessor with the fast line taking of looking ahead.This device comprises that in order to store a prefetch buffer of this fast line taking of looking ahead with a counter that is coupled to this prefetch buffer, this counter is accessed in the counting that one in the high-speed cache laid in fast line taking in order to store one.This device also comprises a steering logic device that is coupled to this counter, and this steering logic device is withdrawn into this high-speed cache according to this counting with the fast line taking of optionally this being looked ahead.

Again on the other hand, the invention provides a kind of method, this method is in a microprocessor, optionally from a prefetch buffer the one fast line taking of looking ahead is withdrawn into a high-speed cache.The step of this method comprises first counting of preserving this fast line taking of looking ahead of an access, and receives one and requires with the new fast line taking of looking ahead to this prefetch buffer.The step of this method comprises that also whether one second counting that be accessed in high-speed cache in a deposit fast line taking of judgement before receiving this requirement be less than this first counting, with response as this requirement of reception, if and this second counting then rewrites (overwrite) to this fast line taking of looking ahead of this prefetch buffer with this new fast line taking less than this first counting.

Again on the other hand, the invention provides a kind of method, this method optionally is withdrawn into a high-speed cache from a prefetch buffer with the fast line taking of looking ahead in a microprocessor.The step of this method comprises this fast line taking of looking ahead of looking ahead to this prefetch buffer, with in getting not soon as one of this high-speed cache with receive the response of a new fast line taking that require to look ahead to this prefetch buffer.The step of this method comprises also whether a deposit fast line taking of judgement in this high-speed cache is invalid, if the fast line taking of this deposit is invalid, then is substituted in this high-speed cache this with this fast line taking of looking ahead and lays in fast line taking.

Again on the other hand, the invention provides a computer data signal that is included in a transmission assembly, but this computer data signal comprises that computing machine identification program code is used for a microprocessor.This program code comprises that first program code is used for a high-speed cache.This program code comprises that also second program code is used for a prefetch buffer, and this prefetch buffer is coupled to this high-speed cache, with the fast line taking of looking ahead from Installed System Memory reception one.It is used that this program code comprises that also the 3rd program code is coupled to the steering logic device of this prefetch buffer for one, this steering logic device according in fact simultaneously access this look ahead fast line taking with look ahead this fast line taking of looking ahead to this prefetch buffer, be retracted into its high-speed cache with fast line taking that this is looked ahead.

The invention has the advantages that as long as increase some extra hardware, the present invention can lower the fast line taking of looking ahead replaced also may be promptly will be by the unfavorable possibility of the fast line taking of access, thereby the efficient of promoting high-speed cache.

Other purpose of the present invention and advantage can be clearer by subsequently the detailed description and the chart of enclosing.

Description of drawings

Fig. 1 is a calcspar of the present invention, and it is described in the device in the microprocessor, and this device is in order to optionally to recall most fast line takings of looking ahead.

Fig. 2 is a process flow diagram of the present invention, and it illustrates in microprocessor shown in Figure 1, optionally recalls the operation of fast line taking to its high-speed cache of looking ahead from this prefetch buffer.

Fig. 3 is a calcspar of another specific embodiment of the present invention, and it is described in the device in the microprocessor, and this device is in order to optionally to recall most fast line takings of looking ahead.

Fig. 4 is a process flow diagram of the present invention, and it illustrates in microprocessor shown in Figure 3, optionally recalls the operation of fast line taking to its high-speed cache of looking ahead from this prefetch buffer.

Wherein, description of reference numerals is as follows:

100 microprocessors, 102 steering logic devices

104 high-speed caches, 106 prefetched lines impact dampers

108 prefetch address buffers (PAR)

112A deposit path 0 access count buffer (CWAC0)

112B deposit path 1 access count buffer (CWAC1)

112C deposit path 2 access count buffers (CWAC2)

112D deposit path 3 access count buffers (CWAC3)

114 minimums are chosen logic device 116 access counts (PBAC) buffer

118 comparer 122min_AC

124 comparative result 126min_way signals

128 look ahead cushions access count (PBAC) 132 loading/storage addresses

The fast line taking of looking ahead of 134 status informations 136

138 prefetch address, 300 microprocessors

The fast line taking access count of 302 steering logic devices, 314 deposits

316 access fixed limit buffers, 318 deposit path buffers

Embodiment

See also Fig. 1, it is a calcspar, and it is described in the device in the microprocessor 100, and this device is in order to optionally to recall most fast line takings of looking ahead.This microprocessor 100 comprises that one is coupled to each other to constitute a plurality of stages of a pipeline (pipeline).One or more this pipeline stage comprises an address generator, and this address generator is in order to produce a memory access arithmetic address, loading as shown in Figure 1/storage address 132.These 132 concrete addresses of specifying a loading or storing computing, loading/storage address.One load operation is written to internal memory with data from microprocessor 100 and store computing from the internal memory reading of data to microprocessor 100.In one embodiment, this loading/storage address 132 is a physical memory addresses.

Microprocessor 100 also comprises a high-speed cache 104, and this high-speed cache comprises the high-speed cache of a N set of paths associated form.In one embodiment, this high-speed cache 104 comprises the 64KB high-speed cache of one 4 set of paths associated forms (4-way set associative).In one embodiment, this high-speed cache 104 is a ground floor data cache (level-1 data cache); But the present invention is not limited to be applied in a data cache, but can be applicable to an instruction cache, an or associating data/commands high-speed cache, and the present invention also is not limited to and only uses the ground floor data cache, but can use at the high-speed cache of getting arbitrary level in the strata system soon.

High-speed cache 104 stores the address label and is stored in the state of each the fast line taking in it.This label comprises the upper strata part that is stored in the memory address of a plurality of fast line takings in the high-speed cache 104.In one embodiment, this state comprises MESI (revising, exclusive, shared, invalid) (modified, exclusive, shared, invalid) protocol information.High-speed cache 104 receives loading/storage address 132.One lower floor of this loading/storage address 132 partly be in order in high-speed cache 104 as choosing a set (set), or row (row), or the index of path (ways).High-speed cache 104 will load/store the upper strata of address 132 and partly do one relatively with this address label that is selected each path in the set, whether " hit " this high-speed cache to judge this loading/storage address 132, in other words, whether i.e. this loading/storage address 132 conforms to arbitrary label that is present in this high-speed cache 104, and be effective status.High-speed cache 104 is with status information 134 outputs, and this status information 134 comprises the MESI state that is selected each path in the set, and shows that this is selected the indication whether arbitrary label in the set conforms to loading/storage address 132.If loading/storage address 132 is derived from a load operation, and " hitting " high-speed cache 104, then these fast line taking data of hitting will be provided for the pipeline stage of this microprocessor 100 that requires these fast line taking data.

Microprocessor 100 also comprises the steering logic device 102 that is coupled to high-speed cache 104.These steering logic device 102 reception sources are from the status information 134 and the loading/storage address 132 of high-speed cache 104.The a plurality of control signals of generation of steering logic device 102 responses are with the running of control high-speed cache 104.The running of this steering logic device will be described in detail hereinafter.

Microprocessor 100 also comprises a prefetched lines impact damper 106 that is coupled to high-speed cache 104.Prefetched lines impact damper 106 is to receive the fast line taking 136 of looking ahead from a Bus Interface Unit, and this Bus Interface Unit is via a processor bus, to extract data to this microprocessor 100 from an Installed System Memory.As described below, this high-speed cache 104 during if loading/storage address 132 is got not soon, then this steering logic device 102 will impel a fast line taking followed by this loading/storage address 132 fast line taking pointed, and in other words, the fast line taking 136 of looking ahead is taken to this prefetched lines impact damper 106 in advance from Installed System Memory.Therefore, as described below, the access when basis that this steering logic device 102 can be favourable is looked ahead fast line taking 136 to this is withdrawn into this high-speed cache 104 with the fast line taking 136 of optionally this being looked ahead.

Prefetched lines impact damper 106 offers this high-speed cache 104 with this fast line taking 136 of looking ahead, and in addition, this prefetched lines impact damper 106 and the fast line taking 136 of will looking ahead offer one or more pipeline stage that requires this microprocessor 100 of data from this fast line taking 136 of looking ahead.In this regard, can be considered as be an extension of this high-speed cache 104 to this prefetched lines impact damper 106.Promptly be, this high-speed cache 104 during if a loading/storage address 132 of the concrete appointment of these steering logic device 102 judgement one load operations is got not soon, but but hit this prefetched lines impact damper 106, then this can the be looked ahead data of fast line taking 136 of this steering logic device 102 offer the pipeline stage of this microprocessor 100.

Microprocessor 100 also comprises a prefetch address buffer (prefetch address register, PAR) 108 that are coupled to steering logic device 102.This prefetch address buffer 108 is the addresses that are stored in the fast line taking 136 of looking ahead in this prefetched lines impact damper 106, and this address is referred to as prefetch address 138.When steering logic device 102 impels this fast line taking 136 of looking ahead prefetched to this prefetched lines impact damper 106, this steering logic device 102 is about to prefetch address buffer 108 and is updated to this fast line taking address 138 of looking ahead.In addition, this steering logic device 102 does one relatively with this prefetch address buffer 108 and this loading/storage address 132, with the detecting access to this fast line taking 136 of looking ahead subsequently.

Microprocessor 100 also comprise be coupled to one of steering logic device 102 look ahead the buffering access count (prefetch buffer access count, PBAC) buffer 116.The buffering of looking ahead access count buffer 116 is the access times that store this fast line taking 136 of looking ahead this prefetched lines impact damper 106 in, and these access times are referred to as to look ahead and cushion access count (PBAC) 128.When this steering logic device 102 detects a access to this fast line taking 136 of looking ahead, then this steering logic device 102 promptly increases this PBAC buffer 116.In one embodiment, an access comprises reads this one of fast line taking 136 of looking ahead, and still, in other specific embodiment, the access of a pair of this fast line taking 136 of looking ahead also comprises and writes and/or spy on (snoop) computing.When a new fast line taking 136 of looking ahead was pre-fetched into this prefetched lines impact damper 106, this steering logic device 102 was promptly removed this PBAC buffer 116.

Microprocessor 100 also comprises a plurality of deposits path access count that is coupled to steering logic device 102, and (candidate way access count, CWAC) buffer 112.N second counter can be coupled to this steering logic device, specific embodiment at Fig. 1 comprises four deposit path access count buffers, annotation is CWAC0 112A respectively, CWAC1 112B, CWAC2 112C, reach CWAC3 112D, also correspond respectively to each path of 4 set of paths associated form high-speed caches 104.Each CWAC buffer 112 stores in these reserve convergences the access times in pairing path separately.This reserve convergence is in this high-speed cache 104, by the set in the selected path of this prefetch address 138.When this steering logic device 102 detects when in this high-speed cache 104 this chosen the access in a path of set, then this steering logic device 102 promptly increases by corresponding one this CWAC buffer 112.When a new fast line taking 136 of looking ahead was pre-fetched into this prefetched lines impact damper 106, this steering logic device 102 was promptly removed this CWAC buffer 112.

Microprocessor 100 comprises that also the minimum that is coupled to CWAC buffer 112 chooses logic device (minimum selection logic) 114.This minimum is chosen the CWAC that logic device 114 receives from each CWAC buffer 112, and exports the minimum value of its CWAC that receives, and this minimum value can be designated as min_AC 122.In addition, this minimum is chosen logic device 114 and output min_way signal 126 to this steering logic device 102, and this min_way signal 126 is concrete specifies this to have the path number of the minimum value that receives from this CWAC buffer 112.

Microprocessor 100 also comprises a comparer 118, and this comparer 118 is to choose logic device 114 with this minimum to couple mutually with this PBAC buffer 116.This comparer 118 does one relatively with this min_AC 122 and this PBAC 128, if this PBAC 128 is greater than this min_AC 122, then produce a logic device true value (true value) with result's 124 outputs as a comparison, otherwise export a logic device falsity (falsevalue).In another specific embodiment, this comparer 118 does one relatively with this min_AC 122 and this PBAC 128, if this PBAC 128 is more than or equal to this min_AC 122, then produce a logic device true value (true value) with result's 124 outputs as a comparison, otherwise export a logic device falsity (false value).This comparative result 124 is provided for this steering logic device 102 then.

See also Fig. 2, it is a process flow diagram of the present invention, illustrates in microprocessor shown in Figure 1 100, optionally recalls the operation of fast line taking to its high-speed cache 104 of looking ahead from this prefetch buffer 106.Flow process starts from decision block 202.

In decision block 202, this steering logic device 102 will check the status signal 134 of Fig. 1, in order to judge this loading/storage address 132 whether get not soon in this high-speed cache 104.If answer is for being that then flow process proceeds to square 204; If answer is that then flow process is not got back to decision block 202.

In square 204, begin to extract from internal memory this get not soon fast line taking to this high-speed cache 104, these steering logic device 102 its bus interface assemblies of instruction are looked ahead its next line taking soon to the prefetched lines impact damper 106 of Fig. 1, the fast line taking of looking ahead that the fast line taking of this next one is pointed to for loading/storage address 132 during and then this gets soon.Prefetched to this prefetched lines impact damper 106 in the fast line taking of the next one, this steering logic device 102 is verified the fast line taking of this next one and also is this high-speed cache 104 in getting not soon.Prefetched to this prefetched lines impact damper 106 when this fast line taking 136 of looking ahead, this steering logic device 102 is about to the prefetch address 138 that this prefetch address buffer 108 is updated to Fig. 1, in other words, and the address that is updated to the fast line taking of this next one that is about to.Flow process then proceeds to decision block 206.

In decision block 206, steering logic device 102 is inquired about (query) prefetch address 138 to high-speed cache 104, and the status information 134 of Fig. 1 is carried out an inspection in order to judge that whether any paths is arranged is to be in invalid (invalid) state in its reserve convergence.If answer is for being that then flow process proceeds to square 208; If answer is that then flow process does not proceed to square 212.

In square 208, steering logic device 102 is retracted into the path that this is in disarmed state with this fast line taking 136 of looking ahead, in the reserve convergence of this path in high-speed cache 104.Flow process is then got back to square 202.

In square 212, steering logic device 102 is removed the PBAC buffer 116 and CWAC buffer 112 of Fig. 1, and its value is set at 0.Flow process then proceeds to decision block 214.

In decision block 214, when loading/storage computing was carried out access to high-speed cache 104, steering logic device 102 will carry out an inspection made the arbitrary path in its reserve convergence become disarmed state in order to judge whether arbitrary computing.For example the path in reserve convergence can invalidly be spied on access (invalidating snoop access) and becomes disarmed state through one.If there is the arbitrary path in its reserve convergence to be become disarmed state, then flow process is got back to square 208 from decision block 214; If answer is that then flow process does not proceed to decision block 216.

In decision block 216, this steering logic device 102 will carry out an inspection in order to judge whether the new requirement of looking ahead, in other words, this steering logic device 102 will carry out an inspection in order to judge a new loading/storage address 132 whether get not soon in this high-speed cache 104, thereby needing to cause the new fast line taking of looking ahead of this prefetched lines impact damper 106.If answer is for being that then flow process proceeds to decision block 218; If answer is that then flow process does not proceed to decision block 224.

In decision block 218, this steering logic device 102 will carry out an inspection to the compare result signal 124 of Fig. 1 in order to judge that whether PBAC 128 is greater than min_AC 122.If answer is for being that then flow process proceeds to square 222; If answer is for denying, then flow process is got back to square 204, and this fast line taking 136 of looking ahead that consequently is stored in prefetched lines impact damper 106 can not be retracted into this high-speed cache 104, but is dropped, in other words, this fast line taking 136 of looking ahead is by subsequently the new rewriting that fast line taking covers of looking ahead.

In square 222, this steering logic device 102 is retracted into path by 126 concrete appointments of min_way signal with this fast line taking 136 of looking ahead, in the reserve convergence of this path in high-speed cache 104.Flow process is then got back to square 204 from square 222.

In decision block 224, this steering logic device 102 carries out an inspection in order to judge that whether a path in reserve convergence is by access with status information 134.In one embodiment, why one path is because of this loading/storage address 132 cache hits this high-speed cache 104, in other words by access, be because this path is an effective status, and the label in this path partly conform to the label of this loading/storage address 132.If this reserve convergence is by access, then flow process proceeds to decision block 226; If answer is that then flow process does not proceed to decision block 228.

In decision block 226, the access path that this steering logic device 102 is determined in response to decision block 224 is to increase CWAC buffer 112.For example, by access, then this steering logic device 102 increases CWAC 112C as if path 2.Flow process then proceeds to decision block 228 from square 226.

In decision block 228, this steering logic device 102 will be relatively this prefetch address 138 and this loading/storage address 132, to carry out an inspection in order to judge that whether this fast line taking 136 of looking ahead is by access.If answer is for being that then flow process proceeds to square 232; If answer is that then flow process is not got back to decision block 214.

In square 232, this steering logic device 102 increases PBAC buffer 116.Flow process is then got back to decision block 214 from square 232.

False code (pseudocode) shown in the following form 1 is also in order to the computing of the microprocessor 100 of describing Fig. 2.

If(anyWayInCandidateSetInvalid){

RetirePrefetchedLineToCache()；

}else{

PBAC＝CWAC[0]＝CWAC[1]＝CWAC[2]＝＝CWAC[3]＝0；

while(noNewPrefetchRequested&&noWayInCandidateSetInvalided){

if(candidateSetAccessed)

CWAC[accessedWay]++；

if(PrefetchedLineAccessed)

PBAC++；

}

if(newPrefetchRequested){

if(PBAC＞min_AC)

RetirePrefetchLineToCache()；

else/*throw?away?prefetched?cache?line*/

OverwritePrefetchBufferWithNewPrefetchData()；

}else{/*way?in?candidate?set?was?invalidated*/

RetirePrefetchedLineToCache()；

}

Form 1.

As shown in Figures 1 and 2, the invention has the advantages that according to the path of gathering corresponding to this storages by this fast line taking 136 of looking ahead of access times by access times, the fast line taking 136 of can optionally this being looked ahead is withdrawn into its high-speed cache 104, rather than indiscriminate this fast line taking 136 of looking ahead is withdrawn into its high-speed cache 104.

See also Fig. 3, it is a calcspar of another specific embodiment of the present invention, and it is described in the device in the microprocessor 300, and this device is in order to optionally to recall most fast line takings of looking ahead.

As the assembly of Fig. 1 same numeral, this microprocessor 300 comprises a high-speed cache 104, prefetched lines impact damper 106, prefetch address buffer (PAR) 108, loading/storage address 132, status information 134, the fast line taking 136 of looking ahead, and prefetch address 138.

Microprocessor 300 also comprises the steering logic device 302 that is coupled to this high-speed cache 104, as the steering logic device 102 of Fig. 1, with prefetched lines impact damper 106; But the steering logic device 302 of Fig. 3 is to be withdrawn into this high-speed cache 104 according to a plurality of numerical value with the fast line taking 136 of optionally this being looked ahead, these a plurality of numerical value are to be stored in the fast line taking access count of a deposit (candidate line access counter, CLAC) buffer 314, one access fixed limit buffer (access threshold register, ATR) 316, reach deposit path buffer (candidate way register, CWR) 318.Above-mentioned CLAC buffer 314, ATR316 and CWR 318 all are coupled to this steering logic device 302.

CWR 318 stores a numerical value, and this numerical value is concrete specifies a deposit path, and this path is in this reserve convergence, with the path of prefetched fast line taking 136 selected property replacements.In one embodiment, just with a nearest used path garrison CWR 318 in this reserve convergence, this path is determined by status information 134 302 beginnings of this steering logic device.If aforesaid deposit path before new looking ahead is required, promptly is substituted, then this steering logic device 302 is updated to the new nearest used path of one with CWR 318.

CLAC 314 stores a numerical value, and this numerical value is prefetched to prefetched lines impact damper 106 for calculating from the fast line taking 136 of looking ahead, this by the fast line taking of deposit of 318 concrete appointments of CWR or deposit path by the number of times of access.

ATR 316 stores a fixed limit numerical value, and this fixed limit numerical value Be Controlled logic device 302 is in order to compare with the numerical value that is stored in CLAC 314, and optionally to recall this fast line taking 136 of looking ahead, details are as follows.In one embodiment, this numerical value that is stored in ATR 316 is predetermined value.In one embodiment, this numerical value that is stored in ATR 316 is program-controlled.

See also Fig. 4, it is a process flow diagram of the present invention, and it illustrates in microprocessor shown in Figure 3 300, optionally recalls the operation of fast line taking to its high-speed cache 104 of looking ahead from this prefetch buffer 106.Flow process starts from decision block 402.

In decision block 402, this steering logic device 302 will check the status signal 134 of Fig. 3, in order to judge this loading/storage address 132 whether get not soon in this high-speed cache 104.If answer is for being that then flow process proceeds to square 404; If answer is that then flow process is not got back to decision block 402.

In square 404, begin to extract from internal memory this get not soon fast line taking to this high-speed cache 104, this steering logic device 302 is about to concrete this nearest numerical value in path (LRU) that used of laying in fast line taking of specifying and moves into to CWR 318.And these steering logic device 302 its bus interface assemblies of instruction are looked ahead its next line taking soon to the prefetched lines impact damper 106 of figure three, the fast line taking of looking ahead that the fast line taking of this next one is pointed to for loading/storage address 132 during and then this gets soon.Prefetched to this prefetched lines impact damper 106 in the fast line taking of the next one, this steering logic device 102 is checked the fast line taking of this next one and also is this high-speed cache 104 in getting not soon.In addition, this steering logic device 302 be about to this get not soon in the address of next fast line taking of fast line taking move into to prefetch address buffer 108.Flow process then proceeds to decision block 406.

In decision block 406, steering logic device 302 is inquired about (query) prefetch address 138 to high-speed cache 104, and the status information 134 of Fig. 3 is carried out an inspection in order to judge that whether any paths is arranged is to be in invalid (invalid) state in its reserve convergence.If answer is for being that then flow process proceeds to square 408; If answer is that then flow process does not proceed to square 412.

In square 408, steering logic device 302 is retracted into this fast line taking 136 of looking ahead by the deposit path at high-speed cache 104 of 318 concrete appointments of CWR.Flow process is then got back to decision block 402.

In square 412, steering logic device 102 is removed the CLAC 314 of Fig. 3, and its value is set at 0.Flow process then proceeds to decision block 414.

In decision block 414, when loading/storage computing is carried out access to high-speed cache 104, steering logic device 302 will carry out an inspection and become disarmed state in order to have judged whether that arbitrary computing makes in its deposit path.If answer is for being that then flow process is got back to square 408 from decision block 414; If answer is that then flow process does not proceed to decision block 416.

In decision block 416, this steering logic device 302 will carry out an inspection in order to judge whether the new requirement of looking ahead.If answer is for being that then flow process proceeds to decision block 418; If answer is that then flow process does not proceed to decision block 424.

In decision block 418, this steering logic device 302 will carry out an inspection in order to judge that whether CLAC314 is greater than the numerical value in the ATR 316 that is stored in Fig. 3.If answer is for being that then flow process proceeds to square 422; If answer is for denying, then flow process is got back to square 404, and this fast line taking 136 of looking ahead that consequently is stored in prefetched lines impact damper 106 can not be retracted into this high-speed cache 104, but is dropped, in other words, this fast line taking 136 of looking ahead is by subsequently the new rewriting that fast line taking covers of looking ahead.

In square 422, this steering logic device 302 with this fast line taking 136 of looking ahead be retracted into by CWR318 the deposit path at high-speed cache 104 of concrete appointment.Flow process is then got back to square 404 from square 422.

In decision block 424, this steering logic device 302 carries out an inspection in order to judge that whether this deposit path is by access with status information 134.In one embodiment, why this deposit path be because this path be effective status, and the label in this path with the label of this loading/storage address 132 partly conforms to by access.If this reserve convergence is by access, then flow process proceeds to decision block 426; If answer is that then flow process does not proceed to decision block 428.

In decision block 426, this steering logic device 302 increases CLAC 314.Flow process then proceeds to decision block 428 from square 426.

In decision block 428, this steering logic device 302 will carry out an inspection in order to judge whether the deposit path is stored computing by one and replace.If answer is for being that then flow process proceeds to square 432; If answer is that then flow process is not got back to judgement side 414.

In square 432, this steering logic device 302 is updated to a new nearest used path in its reserve convergence with CWR 318, and removes CLAC 314, and its value is set at 0.Flow process is then got back to decision block 414 from square 432.

False code (pseudocode) shown in the following form 2 is also in order to the computing of the microprocessor 300 of describing Fig. 4.

If(Cache[PrefetchIndex][CandidateWay].Valid＝＝0){

RetirePrefetchedToCache()；

}else{

CandidateLineAccessCount＝0；

while(！NewPrefetchRequest&&！CandidateLineInvalidated){

if(CandidateLineAccessed){

CandidateLineAccessCount++；

}else?if(CandidateLineInvalidated){/*e.g.，by?external?snoop*/

RetirePrefetchToCache()；

}else?if(CandidateLineReplaced){/*i.e.，with?valid?miss?data*/

UpdateCandidateWayRegister()；

CandidateLineAccessCount＝0；

}

if((CandidateLineAccessCount＜AccessThreshold)&&

(！CandidateLineInvalidate))

{

RetirePrefetchToCache()；

}else{

OverWritePrefetchBufferWithNewPrefetchData()；

/*i.e.，flush?old?prefetch?data*/

}

Form 2.

Though specific embodiments of the invention narrated as before, the present invention is not subject to this.For example, the present invention is applicable to a data cache, an instruction cache, or an instruction/data high-speed cache.In addition, though be described in detail in one embodiment the fast line taking of looking ahead prefetched to its prefetch buffer after, how to follow the trail of the access of (track) this fast line taking of looking ahead and the replacement of the fast line taking of deposit, but other the time access also can be tracked, and the basis of recalling this fast line taking of looking ahead of property alternatively, for example be confirmed as and this fast line taking of looking ahead arrived between the time of this prefetch buffer, to this fast line taking and/or lay in the access of fast line taking of looking ahead in this demand of looking ahead.In addition, read, write, spy on and the combination of other access also can be tracked, and use optionally to recall this fast line taking of looking ahead.In other words, various examinations are arranged, and rule can be by specific implementation to judge this fast line taking of looking ahead in high-speed cache by mistake, or the fast line taking of a deposit have in future bigger by the access possibility, so the present invention to be withdrawn into its high-speed cache than traditional fast line taking of unconditionally this being looked ahead more favourable.At last, though the invention relates to by looking ahead of being produced in getting not soon, the present invention is also applicable to the looking ahead of any pattern, for example by looking ahead that the prefetch program instruction is produced.

The present invention not only can hardware realizes, also can by can use at a computing machine (for example, but identification) but the computing machine identification code of assembly specific implementation (for example, but computing machine identification program code, data or the like) realize.The function of the present invention that this computer program code facilitates this place to disclose, or make, or both realizations of all having.For instance, the present invention can realize it by following computer program code: general program language (for example, C, C++, JAVA or the like); The GDSII database; (hardwaredescription languages HDL), comprising hardware description language: Verilog HDL, VHDL, Altera HDL (AHDL) or the like; Or other programming and/or circuit (promptly being, icon) trap tool in the art.This computer program code (for example can use applicable to any known computing machine, but identification) assembly, this computing machine can use assembly to comprise: semiconductor memory, and disk sheet, discs is (for example, CD-ROM, DVD-ROM or the like), and as can use (for example, but identification) transmission assembly (for example, carrier wave at a computing machine, or comprise numeral, optics, or analog assembly) computer data signal of specific implementation.With regard to itself, this computer program code can transmit on telecommunication network, and this telecommunication network comprises world-wide web and enterprise network.Be understandable that the present invention can (for example realize by computer program code, one intellecture property (Intellectual property, IP) part of core, as a microcontroller core, or as the design of a systemic hierarchial, for example (System-on-Chip SoC), and is transferred to hardware to become the part of integrated circuit with it to a system single chip.The present invention also can a hardware and the combination of computer program code realize.

Specific embodiments of the invention narrated as before, but the present invention is not subject to this.Above-mentioned only is preferred embodiment of the present invention, can not limit the scope of the invention with it.All equalizations of making according to claim of the present invention change and revise, and still belong to protection scope of the present invention, and it does not break away from design of the present invention and scope, so all should be considered as further enforcement situation of the present invention.

Claims

1. A microprocessor comprising:

cache;

a prefetch buffer coupled to the cache for receiving a prefetch cache line from a system memory; and

a control logic coupled to the prefetch buffer, the control logic is based on simultaneously accessing the prefetch cache line and prefetching the prefetch cache line to the prefetch buffer to selectively Prefetch cache lines are recalled to this cache.

2. The microprocessor of claim 1 , wherein the control logic selectively withdraws the prefetch cache line to the cache in response to a subsequent prefetch of another prefetch cache line to the prefetch buffer requirements.

3. The microprocessor of claim 1, further comprising:

A first counter, coupled to the control logic, to count the number of times the prefetch cache line in the prefetch buffer is accessed.

4. The microprocessor of claim 3, wherein the control logic selectively selects the prefetch cache line according to the value stored in the counter representing the number of accesses to the prefetch cache line Fetches are recalled to this cache.

5. The microprocessor of claim 4, wherein the cache comprises an N-way set associative cache.

6. The microprocessor of claim 5, further comprising:

an address, the address is input into the N-path-set associative mode cache for selecting an N-path-set in the cache.

7. The microprocessor of claim 6, further comprising:

N second counters, the N second counters are coupled to the control logic, and each of the N second counters, after the prefetch cache line is prefetched, respectively calculates It corresponds to the number of times the path of the selected set is accessed.

8. The microprocessor of claim 7, wherein the control logic selectively selects the preset Fetch lines are recalled to the cache.

9. The microprocessor of claim 8, further comprising:

The selection logic is coupled to the N second counters, and is used for selecting a minimum value of access times among the N second counters.

10. The microprocessor of claim 5, wherein the control logic recalls the prefetch cache line to the cache in response to invalidating one of the N paths in the selected set.

11. The microprocessor of claim 10, wherein the control logic recalls the prefetch cache line to an invalidated one of the N paths in the selected set in the cache.

12. The microprocessor of claim 1, further comprising:

The register is coupled to the control logic to store an address of the prefetch cache line.

13. The microprocessor of claim 1, wherein the prefetch cache line is prefetched from the system memory in response to a cache miss of an address of the cache.

14. The microprocessor of claim 1 , wherein the prefetch cache line is simultaneously accessed at least as frequently as at least one reserve replacement cache line in the cache is simultaneously accessed, the The control logic is to recall the prefetch cache line to the cache.

15. The microprocessor of claim 1 , wherein the prefetch cache line is accessed prior to a new prefetch request to prefetch another cache line to the prefetch buffer, the control logic The device is about to recall the prefetch cache line to the cache.

16. A means in a microprocessor for selectively recalling a plurality of prefetch cache lines to a cache memory of the microprocessor based on an access to a prefetch cache line , the device consists of:

a prefetch buffer for storing a prefetch cache line;

a register coupled to the prefetch buffer to store a prefetch address of the prefetch cache line;

a control logic, which is coupled to the register to receive an access address for a memory access operation, and compare the access address with the prefetch address;

a counter, the counter is coupled to the control logic to store a count for accessing the prefetch line, wherein when the access address is the same as the prefetch address, the control logic is about to count the counter Increase.

Wherein, the control logic also selectively recalls the prefetch cache line to the cache according to the count.

17. The apparatus of claim 16, wherein the memory access operation comprises a load operation, a store operation, or a peek operation, and a combination of at least two operations among the load operation, the store operation, and the peek operation.

18. The device of claim 16, further comprising:

A second counter coupled to the control logic for storing a second count of a reserve cache line in the cache to be replaced by the prefetch cache line.

19. The apparatus of claim 18, wherein the control logic is to recall the prefetch cache line to the cache when the count is greater than the second count.

20. The apparatus of claim 19, wherein when the count is not greater than the second count, the control logic uses a new prefetch cache line to replace the prefetch cache line in the prefetch buffer override override.

21. The apparatus of claim 20, wherein the reserve cache line comprises one of a plurality of cache lines in a set selected by the prefetch address within the cache.

22. An apparatus in a microprocessor for selectively recalling a prefetch cache line to a cache memory of the microprocessor, the apparatus comprising:

a prefetch buffer for storing the prefetch cache line;

a counter coupled to the prefetch buffer for storing a count of accesses to a reserved cache line in the cache; and

A control logic coupled to the counter, and the control logic selectively recalls the prefetch cache line to the cache according to the count in the counter.

23. The device of claim 22, further comprising:

A limited register is coupled to the control logic to store a limited value.

24. The device of claim 22, further comprising:

A register, coupled to the control logic, stores a value specifying a reserve path within the cache, and the reserve path stores the alternate reserve cache line.