CN1300676C

CN1300676C - Stack area expanding method

Info

Publication number: CN1300676C
Application number: CNB2004100675395A
Authority: CN
Inventors: 胡越黎; 冉峰; 郭腊梅; 朱良辰
Original assignee: University of Shanghai for Science and Technology
Current assignee: University of Shanghai for Science and Technology
Priority date: 2004-10-27
Filing date: 2004-10-27
Publication date: 2007-02-14
Anticipated expiration: 2024-10-27
Also published as: CN1609785A

Abstract

The invention relates to a stack area expansion method. This method is based on the 8051 system, and uses external RAM instead of internal RAM as a spare part of the stack to extend the stack area. When the on-chip stack overflows, it automatically switches to the off-chip stack (using off-chip RAM resources to extend the stack area) to achieve stack capacity. expansion and stack trace. The method for expanding the stack area can be applied to single-chip microcontrollers based on the 8051 instruction system, and can also be applied to other fields such as microcontrollers and microprocessors.

Description

Stack area expanding method

Technical field

The present invention relates to a kind of stack area expanding method, can be applicable to single chip microcontroller, also can be applicable to fields such as other microcontroller, microprocessor based on 8051 instruction systems based on 8051 instruction systems.

Background technology

The special area that storehouse (Stack) normally marks off in storer is used for depositing some special datas, is actually the working storage of data.The storage area of this temporal data is determined by the content among the stack pointer SP.

During the microprocessor operation, can run into interruption, call submodule (subroutine) etc., at this moment often with current PC pointer pop down (preservation), or the incident handled complicated when systematic comparison more for a long time, multiple nesting allocation or interruption can occur, at this moment just have many corresponding PC pointer values to need pop down (preservation).And in the standard 8051, stack pointer SP is 8 special registers, and it indicates the position of storehouse top in the internal RAM zone.The operable zone of SP is 07H-7FH, and stack top is fixed as 7FH, and the stack base then can be located at any position in this zone.Usually the user can be the initial value of SP that the stack base is provided with than higher in order to use limited internal RAM space more, and as 60H, the regional space really used of SP has only 1FH like this.For the project of large-scale frequent call subroutine, and when using the program of recursive algorithm, storehouse just may overflow and cause loss of data.When exceeding the capacity of storehouse, storehouse will take place to be overflowed, at this moment the PC pointer value just can not be protected, and program just can not be recovered to carry out from breakpoint, often makes program fleet, system crash.A kind of simple solution is to strengthen the capacity of storehouse, but object standard 8051 these class single chip microcontrollers, RAM resource-constrained on its sheet (standard 8051 has only 128 bytes), and can not all use RAM on the sheet in actual the use as storehouse, metadata cache, data processing all will be used RAM on the sheet, embedded in addition high capacity RAM can make chip area increase, cause chip cost to raise, therefore it is non-remunerative that the capacity that increases internal RAM simply comes the dilatation stack region, in fact also is infeasible.

Summary of the invention

The object of the present invention is to provide a kind of stack area expanding method, it is based on the stack trace function of standard 8051 systems, can replace internal RAM to extend stack region with the external RAM of cheapness as the reserve piece of storehouse, when storehouse overflows on the sheet, automatically switch to the outer storehouse of sheet (using the outer RAM resource of sheet), realize the expansion of storehouse capacity and the tracking of storehouse.

For achieving the above object, design of the present invention is as follows:

Because the available stack area of standard 8051 is at the 07H-7FH of inner (on the sheet) RAM, the present invention is extended for the stack area in two zones of 80H-FFH of 07H-7FH and outside (sheet the is outer) RAM of inside (on the sheet) RAM, the stack trace function that possesses can allow SP freely switch between two zones of 80-FFH of the 07H-7FH of internal RAM and external RAM, promptly when stack top jumps out the internal RAM space, the automatic directed outwards RAM of SP; When otherwise the storehouse of external RAM was empty, SP pointed to internal RAM automatically, and handoff procedure does not need any participation of user.128 grades of stack spaces of expansion can allow user indiscriminately ad. as one wishes nested subroutine and interruption, and can easily parameter be passed to subroutine and local variable, and need not be narrow and small stack space worry again.The user will do is provided with the SPTCON register when only being beginning and opens the stack trace function, and this function is closed under the default situations.Because regardless of being unlatching or closing this function that SP might overflow, and therefore is provided with the sightless internal system storehouse of user overflow indicator.The value of this sign dynamic tracking SP, microcontroller can be put this zone bit automatically when storehouse overflowed, so that WDT (need not count time-delay) can the immediate replacement system.

According to above-mentioned design, the present invention adopts following technical proposals:

A kind of stack area expanding method, it is characterized in that based on 8051 systems, replace internal RAM to extend stack region with external RAM as the reserve piece of storehouse, when storehouse overflows on the sheet, automatically switch to the outer storehouse of sheet, extend stack region with the outer RAM resource of sheet, realize the expansion of storehouse capacity and the tracking of storehouse;

Concrete steps are:

A., storehouse extended function register SPTCON is set, opens the storehouse extended function, this function is closed under the default situations;

B. divide stack region, the storehouse that is about to MCU is divided into internal stack and external stack, and wherein the external stack zone is to carry out the zone that storehouse expands, and sets relevant letter for to represent the external stack pointer with ESP, represents built-in stack pointer with ISP;

C. according to the inside of being divided, outside two stack regions, following three kinds of situations are considered in extended operation to storehouse, and set coherent signal:

(a) the current stack operation is purely in inside or external RAM;

(b) relate to the instruction that twice is read and write RAM in trans-regional operation: RET/RETI or the LCALL/ACALL implementation, and the ram region difference of twice pop down;

Carry out the POP instruction during (c) execution PUSH when the 7FH of pointed internal RAM, or the 80H of directed outwards RAM;

The concrete steps of setting the coherent signal under above-mentioned three kinds of situations of storehouse expansion are:

(a). two show and relate to significant register SPINC and the SPDEC that strides stack operation:

SPINC: show that current SP will carry out being turned to by built-in stack pointer the operation of external stack pointer;

SPDEC: show that current SP will carry out being turned to by the external stack pointer operation of built-in stack pointer;

(b). two intermediate total device CNT and COUNT:

CNT: SP is added 1/ subtract 1 number of operations and count;

COUNT: the write operation number of times to internal RAM is counted;

(c). the two kinds of decoded signal relevant: XSRTOBE_CON and XMEMORY_CON with stack instruction.XSRTOBE_CON: the read-write control signal of control external RAM.XMEMORY_CON: control is to the addressing operation and the data transmission of external RAM.

Above-mentioned storehouse extended function register SPTCON method is set is:

The address of determining storehouse extended function register SPTCON is C8H, and the control of all functions is to realize by read-write storehouse extended function register SPTCON;

Open the stack pointer extended function, SP freely switches between two zones of 80-FFH of the 07-7FH of internal RAM and external RAM, when stack pointer SP overflows the internal RAM space, and the 80-FFH of the automatic directed outwards RAM of SP; The sightless internal system storehouse of user overflow indicator SPTF is set, the value of this sign dynamic tracking SP, no matter whether stack trace is activated, microcontroller all can put ' 1 ' automatically when storehouse overflowed, system's immediate replacement.

The concrete steps of setting the coherent signal of above-mentioned MCU stack region division are:

A. the stack pointer of system is then still represented with SP, and the content of current stack movable pointer ISP or ESP clock period of can delaying time is reflected to SP;

B.ISP_INUSE signal indication current stack movable pointer attribute, effectively representing the current stack movable pointer when the ISP_INUSE signal is ISP, otherwise represents that then the current stack movable pointer is ESP, or execution is to stride stack operation;

C.ISP_INUSE is the output signal of storehouse enlargement module, also is the status signal of the stack pointer of MCU, and when not opening the storehouse expansion, system default is that the ISP_INUSE signal is effective.CPU judges that by continuous detection ISP_INUSE signal the current stack position is on sheet or outside the sheet, thereby controls each functional module.

The concrete steps of setting above-mentioned ISP_INUSE signal are:

A. the most significant digit according to SP stack pointer value is SP[7 at the end of each machine cycle] judge which district current stack pointer SP is operated in, as be operated in RAM07-7FH on the sheet, SP[7]=0, ISP_INUSE=0 then; As be operated in the outer RAM80-FFH of sheet, SP[7]=1, ISP_INUSE=1 then;

B. each machine cycle other constantly, at the bottom of not opening stack trace or external stack pointer and pointing to stack all the time, show to relate to the significant signal SPINC that strides stack operation and SPDEC when all invalid that ISP_INUSE=1 shows that promptly what carry out this moment is pop down on the sheet.

The concrete steps of setting above-mentioned SPINC signal are:

With PC _7～0And PC _15～8Represent the low eight digit number value and the high eight-bit numerical value of program pointer respectively, the instruction that SPINC relates to has the ACALL/LCALL/PUSH instruction, when SPINC is effective, be that it is to show that stack pointer SP will carry out at 1 o'clock to stride stack operation that promptly stack pointer SP will turn to external stack pointer ESP by built-in stack pointer ISP; The effective status of flag register SPINC is that 1 condition is that following three conditions have an establishment:

When a. the value of current I SP is 7FH, execution be ACALL/LCALL instruction, carry out PC _7～0And PC _15～8Push operation (CNT=0);

When b. the value of current I SP is 7FH, execution be ACALL/LCALL instruction, carry out PC _15～8Push operation, to PC _7～0Push operation finish COUNT=1;

When c. the value of current I SP is 7FH, execution be PUSH DIR instruction, carry out push operation.The concrete steps of setting above-mentioned SPDEC signal are:

The instruction that SPDEC relates to has RET/RETI/POP instruction, and when SPDEC was effective, promptly it was to show that stack pointer SP will carry out at 1 o'clock to stride stack operation that promptly stack pointer SP will turn to built-in stack pointer ISP by external stack pointer ESP; The effective status of flag register SPDEC is that 1 condition is that following three conditions have an establishment:

A. present instruction is RET/RETI, ESP=7FH, and ISP=7FH has only carried out and has once gone out stack operation, CNT=1;

B. present instruction is RET/RETI, ESP=7FH, and ISP=7FH has carried out twice and has gone out stack operation, CNT=2;

C. present instruction is POP instruction, ESP=7FH, and ISP=7FH has carried out and has once gone out stack operation, CNT=1.

The concrete steps of setting relevant control signal XSRTOBE_CON of above-mentioned external stack and XMEMORY_CON signal are:

XSRTOBE_CON, XMEMORY_CON are controlled by the state of ISP_INUSE, ISP_INUSE be effective status then XSRTOBE_CON, XMEMORY_CON be disarmed state 0, otherwise then be effective status 1;

A. if internal stack, ISP_INUSE=1 then, XSRTOBE_CON, XMEMORY_CON decoded signal are invalid; Stack pointer points to built-in stack pointer ISP; External RAM is not carried out read-write operation and data transmission;

B. if external stack is operated, then SPINC, SPDEC, ISP_INUSE are disarmed state.And XSRTOBE_CON, XMEMORY_CON are effective status, carry out to the read-write of external RAM control and to the addressing and the Data Transmission Controlling of external RAM; Stack pointer directed outwards stack pointer ESP;

C. if stride stack operation:

A) SPINC is become effectively by invalid, and then ISP_INUSE is invalid by effectively becoming, and XSRTOBE_CON, XMEMORY_CON decoded signal are also become effectively by invalid; Carry out to the read-write of external RAM control and to the addressing and the Data Transmission Controlling of external RAM; Become the operation of execution external stack by carrying out the internal stack operation; Stack pointer SP turns to external stack pointer ESP by built-in stack pointer;

B) SPDEC is become effectively by invalid, then ISP_INUSE XSRTOBE_CON, XMEMORY_CON decoded signal still are invalid, stack manipulation becomes the operation of execution internal stack by carrying out the external stack operation, external RAM is not carried out read-write operation and data transmission, stack pointer SP turns to built-in stack pointer ISP by external stack pointer ESP.

The present invention compared with prior art, have following conspicuous outstanding substantive distinguishing features and remarkable advantage: the present invention is based on 8051 systems, replace internal RAM to extend stack region with the external RAM of cheapness as the reserve piece of storehouse, storehouse extended register SPTCON of definition in 8051 special function registers (SFR) that keep of standard, open the storehouse extended function, this function is closed under the default situations, then when storehouse overflows on the sheet, can automatically switch to the outer storehouse of sheet, extend stack region with the outer RAM resource of sheet, realize the expansion of storehouse capacity and the tracking of storehouse.The present invention can be applicable to the single chip microcontroller based on 8051 instruction systems, also can be applicable to fields such as other microcontroller, microprocessor.

Description of drawings:

Fig. 1 is the stack architecture synoptic diagram of one embodiment of the invention.

Fig. 2 is the sequential chart of LCALL/ACALL under Fig. 1 example normal condition.

Fig. 3 is that the outer RAM district SP of the sheet of Fig. 1 example follows the tracks of timing waveform.

Fig. 4 be Fig. 1 example stride RAM district SP oscillogram when following the tracks of.

Fig. 5 is that the outer RAM district SP of the sheet of Fig. 1 example follows the tracks of timing waveform.

Fig. 6 is that the ram in slice district SP of Fig. 1 example follows the tracks of oscillogram.

Oscillogram when Fig. 7 is the outer RAM district SP tracking of the sheet of Fig. 1 example.

Oscillogram when Fig. 8 is the outer RAM district SP tracking of the sheet of Fig. 1 example.

Embodiment

Details are as follows for a preferred embodiment of the present invention:

This stack area expanding method adopts following stack architecture (seeing accompanying drawing 1):

● stack pointer (stack pointer): the address at stack top place.If one is added to storehouse or by storehouse deletion, then this pointer points to stack top all the time accordingly by increment or decrement.

● storehouse plot (stack base): the address that holds the bottom position of this reserved block.When storehouse was sky, initial stack pointer was exactly the storehouse plot.Note, carry out the POP operation this moment report is made mistakes.

● storehouse boundary (stack limit): the upper limit of storehouse capacity, promptly when stack full, the address at its stack top place.Note, carry out this moment the PUSH operation then report make mistakes.When SP exceeds the storehouse boundary, will " missing ", the breakpoint of program can not be preserved, and program just can not normally be carried out, system crash.

Can find out that from stack architecture figure enlarging the storehouse capacity is to guarantee the not missing necessary condition of stack pointer.But resource is very precious on the sheet of microcontroller, and Limited resources can't all be used for storehouse, expands in addition that RAM will make chip area increase on the sheet, and cost improves.Therefore the present invention adopts the outer RAM of sheet as the stack area of expanding, in case storehouse is with full (overflowing) in the sheet, system changes storehouse outside the sheet automatically over to, thereby has enlarged the storehouse capacity and don't taken resource on the sheet of microcontroller.Based on thought of the present invention, for 16 microprocessor, the stack area can reach 64KB in theory, and the outer data storage area of sheet cheaply can be used in the stack area of expansion.

Specific implementation method is:

Storehouse extended function register SPTCON of definition in the special function register (SFR) that standard 8051 keeps, the address is C8H.The control of all functions is to realize by read-write storehouse extended function register SPTCON.

Storehouse extended function register SPTCON is defined as follows:

SPTCON address: C8H

-

?SPTOE

SPTE

SPTF

SPTCON.3-7: all be to keep position, zero setting always.

SPTOE: this position is 0 under the default situations.

SPTE: this position is 0 under the default situations, and SP stack region extended function is closed.

Open SP stack region extended function, must follow following process:

1) writes SPTE to ' 1 ' and open this function MOV 0C8H, #02H.

2) can open SP stack region extended function with writing ' 1 ' to SPTOE and SPTE simultaneously in write operation; MOV 0C8H, #06H.

The state flag bit of SPTF:SP, system is provided with automatically, and the user can only read and can not write.When opening the stack region extended function, SPTCON is done whole write operation, can not influence this content.

Open the stack pointer function, SP freely switches between two zones of 80-FFH of the 07-7FH of internal RAM and external RAM.When stack pointer SP overflows the internal RAM space, the 80-FFH of the automatic directed outwards RAM of SP, this process does not need any participation of user.The user will do is provided with the SPTCON register when only being beginning and opens this function, and this function is closed under the default situations.SP also might overflow when considering unlatching simultaneously or closing this function, therefore is provided with the sightless internal system storehouse of user overflow indicator SPTF.Whether the value of this sign dynamic tracking SP is activated no matter storehouse expands, and microcontroller all can put ' 1 ' automatically when storehouse overflowed, system's immediate replacement.

(1) scheme of stack area expanding method

The storehouse of MCU is divided into internal stack (RAM on the sheet, 07-7FH) and external stack (the outer RAM of sheet, 80H-FFH), represent the external stack pointer with ESP, represent built-in stack pointer with ISP, ISP_INUSE signal indication current stack movable pointer attribute, effectively representing the current stack movable pointer when the ISP_INUSE signal is ISP, otherwise represent that then the current stack movable pointer is ESP, or execution is to stride stack operation.ISP_INUSE is the output signal of storehouse enlargement module, also is the status signal of the stack pointer of MCU, and when not opening the storehouse expansion, system default is that the ISP_INUSE signal is effective.Thereby CPU judges current stack position (still sheet is outer on the sheet) by continuous detection ISP_INUSE signal controls each functional module.The stack pointer of system then still represents with SP, and the content of current stack movable pointer (ISP or ESP) clock period of can delaying time is reflected to SP.

(2) setting and the instruction sequencing figure of concrete associated control signal and status signal

Because during stack pointer directed outwards RAM, not only the instruction cycle is elongated, also want similar MOVX equally to read and write external RAM (because the stack area of expansion externally RAM on), therefore all control unit module of comprising of many places (except order register and interrupt system), the input selection and the I/O port processing module of ALU operand will increase the steering logic to ISP_INUSE.The storehouse expansion relates to LCALL, ACALL, RET, RETI, PUSH and six instructions of POP, storehouse expands when taking place, the read-write operation sequential of these six instructions can change (see attached list 1 provided when stack pointer directed outwards RAM the timing variations situation of these six instructions).

The design of ISP_INUSE signal need be considered three kinds of situations,

(1) the current stack operation is purely in inside or external RAM;

(2) relate to trans-regional operation, as the instruction of twice read-write RAM in RET/RETI or the LCALL/ACALL implementation, and the ram region difference of twice pop down;

Carry out the POP instruction during (3) execution PUSH when the 7FH of pointed internal RAM, or the 80H of directed outwards RAM.

The value that only needs to judge current I SP or ESP for (1) gets final product; For (2) and (3) owing to relate to trans-regional operation, then comparatively complicated, the current operation that must be perfectly clear is in which in a stage, when pointer transfers the external stack pointer to by built-in stack pointer or transfers built-in stack pointer to by the external stack pointer, show that the effective status of the register ISP_INUSE of current stack movable pointer attribute will change.Show and relate to significant register SPINC and the SPDEC that strides stack operation so increased by two again, show respectively that by the effective status of these two registers current SP will carry out turning to the operation of external stack pointer still to be turned to the operation of built-in stack pointer by the external stack pointer by built-in stack pointer.And increase by two intermediate total device CNT and COUNT, respectively SP is added 1/ and subtract 1 number of operations and count with the write operation number of times of internal RAM and count.Be directed to the external stack operation, increased the read-write control signal of two kinds of decoded signals relevant: XSRTOBE_CON-control external RAM again with stack instruction.XMEMORY_CON-control is to the addressing operation and the data transmission of external RAM.

The effective status of flag register SPINC is that 1 condition is that following three conditions have an establishment to get final product:

When 1. the value of current I SP is 7FH, execution be ACALL/LCALL instruction, carry out PC _7～0And PC _15～8Push operation (CNT=0).

When 2. the value of current I SP is 7FH, execution be ACALL/LCALL instruction, carry out PC _15～8Push operation, to PC _7～0Push operation finish (COUNT=1).

When 3. the value of current I SP is 7FH, execution be PUSHDIR instruction, carry out push operation.

The instruction that SPINC relates to has the ACALL/LCALL/PUSH instruction, and the operation of SP is: SP adds 1 earlier and also writes SP again, the content that will preserve is write in the address of SP appointment again.

For 1., because the value of current I SP is 7FH, SP carries out and adds 1 operation, and turns to external stack pointer ESP, so the address of twice push operation all is an external RAM.

Finish in internal RAM for 2. push operation for the first time, SP adopts built-in stack pointer ISP.Externally finish among the RAM for the second time, SP adopts external stack pointer ESP.

For 3. only carrying out a push operation, the SP pointer turns to external stack pointer ESP by built-in stack pointer ISP, and pop down is externally finished among the RAM.

The effective status of flag register SPDEC is that 1 condition is that following three conditions have an establishment to get final product:

1. present instruction is RET/RETI, ESP=7FH, and ISP=7FH has only carried out and has once gone out stack operation (CNT=1).

2. present instruction is RET/RETI, ESP=7FH, and ISP=7FH has carried out and has gone out stack operation (CNT=2) for twice.

3. present instruction is POP instruction, ESP=7FH, and ISP=7FH has carried out and has once gone out stack operation (CNT=1).

The instruction that SPDEC relates to has the RET/RETI/POP instruction, and the operation of SP is: earlier the content in the SP assigned address is ejected, SP carries out and subtracts 1 operation and write SP again.

Carry out for 1. SP and to subtract the value that equals 7FH after 1 and write SP again and delay a clock period than ESP=7FH, thus when ESP=7FH SP=80H.The PORT mouth is sent out stack address 0080H, and the content that ejects under the effective situation of NXRAMR in this address arrives the appointment register.So it should be 7FH that the next one goes out stack address, SP subtracts 1 automatically, ISP=7EH, and next clock period SP stack pointer turns to built-in stack pointer ISP to equal 7EH automatically.

For 2. for the first time, to go out stack address for the second time all be the external RAM address, goes out the 0080H that stack address is an external RAM for the second time, and ejects after second byte SP and subtract 1 and write the back again and be 7FH, points to built-in stack pointer ISP automatically.

For 3. POP instruction only the carrying out ejection operation of next byte, ejecting the address is the 0080H of external RAM.Automatically subtract 1 after the SP ejection content and equal 7FH, and write and point to built-in stack pointer ISP again.

More than two significant register SPINC and SPDEC show that stack pointer SP will carry out when effective and stride stack operation that promptly stack pointer SP will turn to external stack pointer ESP by built-in stack pointer ISP, or turns to built-in stack pointer ISP by external stack pointer ESP.So represent that at this moment the ISP_INUSE signal of current stack movable pointer attribute should be invalid.

The ISP_INUSE signal of expression current stack movable pointer attribute is effective, represents that promptly the current stack movable pointer is that the condition of ISP is that following three conditions have an establishment to get final product:

1. the scope of activities of SP is 07H～7FH.

2. do not open stack trace.

3. ESP=7FH and SPINC and SPDEC are disarmed state.

So show that when the ISP_INUSE signal is effective what carry out is internal stack operation; ISP_INUSE invalidating signal, SPINC, SPDEC signal show that effectively what carry out is to stride stack operation; ISP_INUSE invalidating signal, SPINC, SPDEC invalidating signal show that what carry out is external stack operation.

The overall operation flow process of storehouse is as follows:

(1) for the instruction that relates to stack manipulation, the rising edge in first clock period of the machine cycle that present instruction begins begins to locate the most significant digit of ISP_INUSE negate in SP.As SP=07H～7FH, then ISP_INUSE=1 is effective status.As SP=80H～FFH, then ISP_INUSE=0 is disarmed state.And the rising edge place begins decoding, translates relevant control signal.The control signal relevant with storehouse has: MEM_CON, XSRTOBE_CON, XMEMORY_CON.Wherein XSRTOBE_CON, XMEMORY_CON are controlled by the state of ISP_INUSE, as ISP_INUSE be effective status then XSRTOBE_CON, XMEMORY_CON be disarmed state 0, otherwise then be effective status 1.Be that XSRTOBE_CON, XMEMORY_CON are the control signals relevant with external stack.

(2) afterwards the state of the ISP_INUSE of rising edge place of each clock period all can be judged its state according to above-mentioned condition after first clock period, and then controls each module relevant with storehouse according to the state of ISP_INUSE again.

1. if internal stack, ISP_INUSE=1 then, XSRTOBE_CON, XMEMORY_CON decoded signal are invalid.Stack pointer points to built-in stack pointer ISP.

2. if external stack is operated, then SPINC, SPDEC, ISP_INUSE are disarmed state.And XSRTOBE_CON, XMEMORY_CON are effective status, carry out to the read-write of external RAM control and to the addressing and the Data Transmission Controlling of external RAM.Stack pointer directed outwards stack pointer ESP.

3. if stride stack operation, 1) SPINC becomes effectively by invalid, and then ISP_INUSE is invalid by effectively becoming, and XSRTOBE_CON, XMEMORY_CON decoded signal are also become effectively by invalid.Become the operation of execution external stack by carrying out the internal stack operation.Stack pointer SP turns to external stack pointer ESP by built-in stack pointer.2) SPDEC is become effectively by invalid, and then ISP_INUSE XSRTOBE_CON, XMEMORY_CON decoded signal still are invalid, and stack manipulation becomes the operation of execution internal stack by carrying out the external stack operation.Stack pointer SP turns to built-in stack pointer ISP by external stack pointer ESP.

Below be the implementation status of concrete instruction:

①LCALL/ACALL

1) (timing waveform is seen accompanying drawing 2) under the normal condition:

The push operation of LCALL/ACALL is finished in internal RAM, and the ISP_INUSE signal is effective.Stack pointer SP points under the situation of built-in stack pointer ISP, and the time sequential routine is only used two machine cycles.

2) the outer RAM district SP of sheet follows the tracks of (timing waveform is seen accompanying drawing 3):

The push operation of LCALL/ACALL is externally finished among the RAM, the ISP_INUSE invalidating signal, and SPINC, SPDEC are invalid.Under the situation of stack pointer SP directed outwards stack pointer ESP, the time sequential routine is wanted four machine cycles.

3) stride RAM district SP and follow the tracks of (timing waveform is seen accompanying drawing 4):

If carry out the CALLS instruction during current SP=7EH (ISP).

A. ISP=ISP+1=7FH for the first time, PC _7-0Write in the unit that the internal RAM address is 7FH CNT=1

B. ISP=ISP+1=80H for the second time, PC _15-8Leave in the unit that the external RAM address is 80H CNT=2 in.This wherein just relates to the problem of trans-regional operation.How to allow instruction after having write data to internal RAM, can seamlessly deliver to address date in the external RAM and go by PORT0, how does how the operation of control address increment control the write signal of external RAM? the key that solves these a series of problems is must elongate in the instruction cycle.Be equivalent to do a MOVX operation because write external RAM, what device the transmission of address and data will cross over comprises the PAD mouth, still quite objective through its size of delay of stack.

Sum up: a. sends the internal RAM write signal during operation, COUNT=1, and SPINC=1 afterwards, ISP_INUSE=1, presentation directives's cycle need be elongated.Disturb for reducing data, CALLS_WR_CTRL=1 is set makes the XRAM write signal keep high level.Will write XRAM when b. operating, NXRAMW is effective for the XRAM write signal.Instruction cycle length was 4 machine cycles.

②RET/RETI

The outer RAM district SP of sheet follows the tracks of (timing waveform is seen accompanying drawing 5):

(1) current SP=81H (ESP) carries out the RET/RETI instruction.

A. take out the content assignment in for the first time being the unit of 81H and give PC from the XRAM address _15-8, ESP=ESP-1=80H, CNT=1.

B. take out the content assignment in for the second time being the unit of 81H and give PC from the XRAM address _7-0, ESP=ESP-1=7FH, CNT=2, ISP=7FH at this moment.

The content that the SP of a, twice operation of b points to is all from external RAM, thus the instruction cycle elongation to 3 machine cycles, twice of the read signal of XRAM is effective.After twice reducing of stack pointer, the cycle that SPDEC=1 indicates this instruction is set keep elongation up to end!

Judge (ESP==8 ' h7FH﹠amp; ﹠amp; (ISP=8 ' h7FH) ﹠amp; ﹠amp; CNT=2 ' b10﹠amp; ﹠amp; MEM_CON[9] whether set up!

(2) current SP=80H (ESP) carries out the RET/RETI instruction.

A. take out the content assignment in for the first time being the unit of 80H and give PC from the XRAM address _15-8, ESP=ESP-1=7FH, CNT=1.

B. for the second time internally address ram be to take out the content assignment in the unit of 7FH to give PC _7-0, ISP=ISP-1=7EH, CNT=2, ESP=7FH at this moment.

The content that SP points among a is from XRAM, and the content that SP points among the b is from internal RAM, and the instruction cycle is still elongated, but the read signal of XRAM is effective when having only a operation, b will be provided with ISP_READY=RETS_RD_CTRL=1 during operation, makes the NXRAMR signal keep high level.

Judge in the execution process instruction (ESP==8 ' h7FH) ﹠amp; ﹠amp; (ISP==8 ' h7FH) ﹠amp; ﹠amp; CNT[0] (ISP=8 ' h7EH﹠amp; ﹠amp; CNT[1]) ﹠amp; ﹠amp; MEM_CON[9] whether set up! Setting up then, the XRAM write signal keeps high level.

Attention: only need judge the value of ISP during CNT=2 and need not to judge ESP, to have only the RET/RETI instruction to carry out, may make that just two of ISP==8 ' h7EH and CNT=2 are satisfied simultaneously from SP=80H because this possibility is a uniqueness.

③PUSH?dir

Current SP=7FH (ESP) carries out the PUSH instruction.ESP=ESP+1=80H if dir points to special function register SP, need pay special attention to.Must pin the value of OPERAND_B in this under the situation at the C1P3 end, because ESP the variation just assignment SP of beat that will delay time, the SFR value that reads when also being C1P3 is the correct value before storehouse changes, and the value of storehouse has equaled 80H during C1P4, so latch the value of SFR at the C1P3 end and import the ALU processing by OPERAND_B, the output of ALU writes XRAM in three subsequent beats.

Ram in slice district SP follows the tracks of waveform and sees accompanying drawing 6:

Waveform was seen accompanying drawing 7 when the outer RAM district SP of sheet followed the tracks of:

④POP?dir

The outer RAM district SP of sheet follows the tracks of (timing waveform is seen accompanying drawing 8):

Current SP=80H (ESP) carries out the POP instruction.

ESP＝ESP-1＝7FH，CNT＝1。The content of SP is from XRAM, so the XRAM read signal is effective.The data that from XRAM, read, to handle through the ALU that pure combinational logic is formed, give the specified SFR of dir in instruction end assignment then, the perhaps unit in the internal RAM of dir appointment, latter two beat that instructs in Z8051 takes off the bar instruction in advance by the PO mouth, so the content (XRAMDI) on the latch data bus during CLP2 end.Judge in the execution process instruction (ESP==8 ' h7FH) ﹠amp; ﹠amp; (ISP==8 ' h7FH) ﹠amp; ﹠amp; CNT[0] ﹠amp; ﹠amp; MEM_CON[11] whether set up! Set up and then put SPDEC, effective three beats of expression XRAM read signal.

Under when expressing stack region and expand taking place before and after the instruction cycles contrast:

Instruction	Former instruction cycles	Elongate the back instruction cycles
Instruction	Former instruction cycles	Elongate the back instruction cycles	LCALL/ACALL	2	4
RET/RETI	2	3	LCALL/ACALL	2	4
RET/RETI	2	3	PUSH	2	2
POP	2	2	PUSH	2	2

Claims

1. stack area expanding method, it is characterized in that based on 8051 systems, replace internal RAM to extend stack region with external RAM as the reserve piece of storehouse, when storehouse overflows on the sheet, automatically switch to the outer storehouse of sheet, extend stack region with the outer RAM resource of sheet, realize the expansion of storehouse capacity and the tracking of storehouse;

Concrete steps are:

B. divide stack region, the storehouse that is about to MCU is divided into internal stack and external stack, and wherein the external stack zone is to carry out the zone that storehouse expands, and sets coherent signal for to represent the external stack pointer with ESP, represents built-in stack pointer with ISP;

C. according to the inside of being divided, outside two stack regions, following three kinds of situations are considered in extended operation to storehouse:

(a) the current stack operation is purely in inside or external RAM;

The concrete steps of setting the coherent signal under three kinds of situations of storehouse expansion are:

(a) two show and relate to significant signal SPINC and the SPDEC that strides stack operation:

(b) two intermediate total device CNT and COUNT:

CNT: SP is added 1/ subtract 1 number of operations and count;

COUNT: the write operation number of times to internal RAM is counted;

(c) the two kinds of decoded signal relevant: XSRTOBE_CON and XMEMORY_CON:XSRTOBE_CON: the read-write control signal of control external RAM with stack instruction;

XMEMORY_CON: control is to the addressing operation and the data transmission of external RAM.

2. stack area expanding method according to claim 1 is characterized in that the method that storehouse extended function register SPTCON is set is:

3. stack area expanding method according to claim 1, the concrete steps that it is characterized in that setting the coherent signal that the MCU stack region divides are:

4. stack area expanding method according to claim 3 is characterized in that the concrete steps of setting the ISP_INUSE signal are:

5. stack area expanding method according to claim 1 is characterized in that the concrete steps of setting the SPINC signal are:

Represent the low eight digit number value and the high eight-bit numerical value of program pointer respectively with PC7～0 and PC15～8, the instruction that SPINC relates to has the ACALL/LCALL/PUSH instruction, when SPINC is effective, be that it is to show that stack pointer SP will carry out at 1 o'clock to stride stack operation, be that stack pointer SP will turn to external stack pointer ESP by built-in stack pointer ISP, the effective status of flag register SPINC is that 1 condition is that following three conditions have an establishment:

When a. the value of current I SP is 7FH, execution be ACALL/LCALL instruction, carry out push operation (CNT=0) to PC7-0 and PC15～8;

When b. the value of current I SP is 7FH, execution be ACALL/LCALL instruction, carry out push operation to PC15～8, the push operation of PC7～0 is finished COUNT=1;

When c. the value of current I SP is 7FH, execution be PUSH DIR instruction, carry out push operation.

6. stack area expanding method according to claim 1 is characterized in that the concrete steps of setting the SPDEC signal are:

7. stack area expanding method according to claim 1 is characterized in that the concrete steps of setting relevant control signal XSRTOBE_CON of external stack and XMEMORY_CON signal are:

B. if external stack is operated, then SPINC, SPDEC, ISP_INUSE are disarmed state; And XSRTOBE_CON, XMEMORY_CON are effective status, carry out to the read-write of external RAM control and to the addressing and the Data Transmission Controlling of external RAM; Stack pointer directed outwards stack pointer ESP;

C. if stride stack operation:

A) SPINC is become effectively by invalid, and then ISP_INUSE is invalid by effectively becoming, and XSRTOBE_CON, XMEMORY_CON decoded signal are also become effectively by invalid; Carry out to the read-write of external RAM control and to the addressing and the Data Transmission Controlling of external RAM;

Become the operation of execution external stack by carrying out the internal stack operation; Stack pointer SP turns to external stack pointer ESP by built-in stack pointer;