CN1391672A - Raid controller system and method with ATA emulation host interface - Google Patents

Abstract

The RAID storage device controller (70) provides a host interface (56) for connecting the controller to the host system bus. The host interface is isolated from the connected storage devices, such as IDE disk drives, so that the number of drives actually connected is not limited by the interface protocol. Various device ports can be implemented, and various RAID strategies, such as RAID3 and RAID5, can be used. In various cases, the host interface provides a standard, uniform interface to the host, namely the ATA interface (82, 84, and 86), and preferably a dual-channel ATA interface. The host interface emulates a single-channel or dual-channel ATA interface and emulates one or two connected IDE devices per channel, regardless of the actual number of devices physically connected to the controller. For example, this allows configuring five or seven IDE devices in a RAID5 protocol without changing the standard BIOS in the PCI host. Thus, the RAID controller is transparent to standard dual-channel ATA controller boards.

Description

Inexpensive Disk Redundant Array Controller System and Method with Advanced Technology Embedded Interface Emulation Host Interface

related application

This application is a continuation of and claims the benefit of US Provisional Application No. 60/156001, filed September 22, 1999.

technical field

The invention relates to a computer data storage device controller, in particular to a RAID controller with a host interface simulating an ATA standard controller and connected IDE devices.

Background of the invention

The first IBM PCs and compatibles had only floppy disk drives for mass storage. Subsequent XT and AT models included adapters for attaching 5.25-inch fixed (non-removable) drives for mass data storage. These initial adapters provided most of the low-level control signals for the drive, including data separation circuitry for read signals and precompensated write signals. Including these functions in the adapter avoids duplicating a pair of drives where only one drive is accessed at a time. Unfortunately, the 5MB read/write channel in the adapter doesn't allow faster drives to be connected as technology improves.

This problem was solved by bringing the "real-time" approach of the controller to the drive. The integrated drive circuit, or IDE drive, combines all the control and data channels required to read or write the drive, transferring data between the local buffer and the media. Manufacturers can choose the data rate. For the connection of data storage devices to host systems, a new interface is defined, ATA (AT Embedded Interface with Packet Interface Extension (ATA/ATAP14)) (IBM AT Embedded Interface). The first IDE interface simply included address decoding and buffering between the ISA bus and the ATA cable connector. The interface protocol uses program-controlled input and output commands to access the registers of the IDE device. Data transmission uses the input string and output string commands of the main processor to adjust the transmission rate of the connected drive. In more recent versions of the specification, these transfer rates reach 16MBPS. This is the transfer rate between the buffer of the storage device and the memory of the ISA bus. The transfer rate between the media and the buffer is much lower.

With the emergence of the PCI bus, Intel Corporation released the PCI IDE document (PCI IDE controller technical specification, revision 1.0, 3/4/94), which provides a mapping from the previous host interface based on the ISA bus to the PCI bus. This standard describes a dual IDE channel controller. A pair of devices, a master and a slave, can be connected to each channel. For data transfers, the device can also be accessed as a PCI bus target.

Intel Corporation has also released the Bus Master IDE Documentation (Programming Interface for Bus Master IDE Controllers, Revision 1.0, 5/16/94). This document defines a standard for incorporating DMA devices in IDE channels. The bus master interface allows the IDE channel to transfer data to or from the system memory through the PCI bus, acting as a bus master (PCI bus initiator). The maximum transfer rate to a 32-bit/33MHz PCI bus is 133MBPS.

A revision of the ATA specification defines a new transfer mode, Ultra DMA. Improves on previous transfer rates by tightening setup and hold time requirements for data transfers in cables. At 16MBPS, the read transfer rate is greatly limited by the round trip of sending the read strobe, accessing the data, and sending that data back. The Ultra DMA protocol originally maintained the electrical characteristics of all signals and cables, but redefined the functions of three of the signals to provide a new protocol. In this protocol, the strobe signal that provides the timing of the data is transmitted as data from the same end, that is, by the controller for writes and by the device for reads. In this configuration, the transfer rate is limited only by the cable skew of the cable's single transition. The first UDMA device doubles the programmable IO transfer rate to 33MBPS. Subsequent revisions doubled the original UDMA transfer rate to 66MBPS, but required the use of 80 ribbon cables with alternating signal and ground connections. The current version supports a transfer rate of 100MBPS. There is a trend to replace the ATA parallel interface with a high-speed serial link, but more parallel interfaces that increase parallel speed may be released first.

question

A common personal computer includes a motherboard designed around a chipset, including a processor, DRAM interface, various input/output adapters, and BIOS ROM. IO adapters usually include IDE interfaces. The current version of the IDE controller features a pair of IDE ports, each capable of connecting to a pair of IDE storage devices. These devices usually include one or more IDE hard disks and CD ROM, DVD ROM or CD WORM drives. The Basic Input Output System, or BIOS, is a program that boots a PC and provides low-level IO routines for adapters on the motherboard. Basically all of these PCs can use the motherboard BIOS to boot and run from an IDE hard drive.

An increasing number of personal computers are deployed in server or workstation applications in the small office/home office (SOHO) market. Historically, hard drives with Small Computer System Interface (SCSI) provided some performance gains for more demanding applications. But today, with more than 85% of drives made as IDE drives, SCSI drives also tend to be built with the same media and read/write heads, with little or no performance gain and a huge increase in cost. Another popular option is to use Redundant Arrays of Inexpensive Disks (RAID), which was originally suggested by Patterson (D. Patterson et al. "The Case for Redundant Arrays of Inexpensive Disks (RAID)" (Univ. Cal. Report No.UCB/CSD87/391, Dec.1987). RAID systems are committed to these two aspects of reliability and performance. First, data is stored in a redundant manner through two or more drives so that no single drive fails Data is lost, thereby achieving reliability. Second, relative to a single drive, due to the collective performance of the array, performance increases are achieved. Different parts of data stored in a redundant manner can be read from two drives at the same time. In addition , data can be written in the form of data strips, wherein, data strips run through all available drives, and when data is read back, an aggregate transfer rate can be achieved. In US Patent No.6018778 of the present invention, the RAID array controller has been implemented Further explanation.

Unfortunately, several existing RAID solutions have some drawbacks. The local intelligence and use of SCSI disk drives characterizes a class of RAID solutions. Such solutions exhibit high performance despite the high cost of drivers and controllers. Another popular class of RAID solutions is characterized by the use of IDE drives but lacks local intelligence or buffering. This is mostly a software solution. All the software required to control multiple drives for redundancy or to stripe data must run on the host system, greatly increasing disk drive overhead on the processor and system bus. Thus, RAID benefits are realized at the expense of system performance degradation due to the increased system overhead. Both solutions have an additional problem. These RAID controllers are not directly supported by the motherboard's BIOS. Additional software drivers are required. These drivers may vary with the functions of the operating system, such as Windows, Windows NT, UNIX, LINUX, etc., thereby bringing additional burdens to controller manufacturers, OEMs, marketing groups, and system integrators.

Therefore, there remains a need for a RAID storage device controller that does not require specialized software to execute in the host processor, and that does not require additional software drivers or changes to the BIOS. RAID controllers that do not require changes to the BIOS generally have the advantage of "plug and play" compatibility with virtually all off-the-shelf computers that implement the ATA-compliant interface standard. The RAID controller is transparent to the host, and can configure multiple storage devices (not limited to four) with any combination of device interfaces, and can implement RAID mirroring, stripes, etc., without adding overhead to the host. This RAID controller brings RAID functionality to all PC users with low cost and extremely easy installation.

Summary of the invention

The present invention implements a RAID controller that is compatible with all operating systems that can be booted and run on a given PC motherboard using standard IDE controllers and IDE drivers. This compatibility is achieved by simulating standard controllers and connected drives. For example, for reliability, a given system may require a pair of drives in a RAID1 or "mirrored" configuration. When connected to the controller of the present invention, the BIOS will see a single, extremely reliable drive. The system can also require an array of three drives, configured in a RAID3 or RAID5 configuration. This will provide twice the transfer rate of any of the three drives with high reliability. Likewise, in the present invention, to the BIOS, this three-drive array appears to be a single drive, advertises twice the capacity of any of the three drives, and exhibits twice the transfer rate, With high reliability. In any case, RAID is transparent to the existing drivers in the BIOS.

The controller of the present invention emulates a standard two-channel IDE controller. Like a standard controller, it is logically connected to the PCI bus. It can physically exist on the motherboard, possibly integrated in the motherboard chipset, or in a plug-in card in a PCI slot. It can emulate all four devices that can be connected to a standard controller. Each of these logical devices provides a possible interface to the array of physical devices connected to the controller. Although this embodiment provides an ATA port for the connection of a physical drive, other types or combinations of interfaces may be used.

Other objects and advantages of the present invention will become apparent through the following detailed description of the preferred embodiment with reference to the accompanying drawings.

Figure overview

Figure 1 is a simplified block diagram of a prior art ATA dual channel controller application illustrating the physical and software/register views.

Figure 2 is a simplified block diagram of a RAID controller with ATA port emulation in accordance with the present invention.

Figure 3 is a high level simplified block diagram of a currently preferred commercial embodiment of a RAID controller with ATA port emulation.

FIG. 4 illustrates an implementation of the ATA register file of the controller of FIG. 3 in more detail.

DETAILED DESCRIPTION OF THE BEST EMBODIMENTS

The upper part of FIG. 1 illustrates a typical prior art application of an ATA controller 10 providing an interface between a system bus 12 and a storage device 14 in a personal computer. The system bus 12 is a PCI bus. When logically connected to the PCI bus, the ATA controller is usually integrated in the motherboard chipset. For a given application, other or additional controllers may plug into one of the PCI bus slots (not shown) on the motherboard. The PCI bus provides a configuration mechanism by which each controller can be assigned a unique address. A typical controller 10 provides two channels terminated in a pair of connectors 16 and 18, identified as primary and secondary IDE connectors, respectively. Each secondary channel will support a pair of storage devices that share a connector and cable. For example, in FIG. 1 , secondary channel cable 19 connects to master storage device 20 and to slave storage device 22 . Another pair of drivers is similarly connected to the fundamental channel cable 24 . Thus, the two channel controllers 10 support a total of four devices, as shown in FIG. 1 .

The lower part of Fig. 1 illustrates the programming interface and driver of the IDE controller seen from the perspective of the PCI bus. The physical address of each block is assigned through the controller's PCI bus configuration space, as is known in the art and described in the previously referenced Intel PCI IDE Controller Specification document. Another Intel document cited earlier, "Programming Interface for Bus-Master IE Controllers," describes the programming interface for bus-master IDE controllers. Before this mechanism was standardized, storage device data was typically transferred via programmed I/O, where the loads and stores required for data transfers were performed by the system processor. Although the programmable I/O mechanism is still supported, the bus master interface allows the ATA controller to transfer data through direct access to system memory, ie through DMA. The bus master IDE controller documentation defines a sixteen-byte block of registers that supports a pair of bus masters, one for the primary ATA channel and one for the secondary ATA channel. This register block is physically an integral part of the controller. As shown, it is split into two sections 30 and 32, one section being associated with each channel.

The ATA specification defines the programming interface for storage devices. The interface consists of two register blocks: a command block and a control block. A command block is an eight-byte block of byte-wide registers. A control block is a four-byte block of byte-wide registers. All implementation details of these registers are published in the ATA specification.

The right side of Figure 1 shows four sets of command and control register blocks, one set corresponding to one of the four attached memory devices. For example, a set of register blocks 36 includes a command block 38 and a corresponding control block 40 . These registers are physically an integral part of the corresponding memory devices shown in the upper part of Figure 1. Thus, register set 36 (fundamental channel) is located in main storage device 25 . If a given memory device is not connected, its command and control register block will not appear in the programming interface.

The ATA specification also defines the protocols supported by storage devices. In general, access commands and all associated parameters are loaded into registers of the command block. The storage device will execute the command. For device writes, it will first request data to be written. For programmed I/O operations, the host processor will read data from system memory and write the data to a buffer (not shown) in the device using a portion of the command block as a sixteen bit window. For bus master DMA operations, the ATA controller will directly access data from system memory according to the configuration of the channel's bus master controller register block. Storage devices access storage media and transfer data between the media and its local buffers. For media reads, the data in the local buffer is transferred to system memory using the above-mentioned programmed I/O or bus master DMA. Finally, the storage device will indicate to the host system that the operation is complete through the ATA controller, either by polling the status register, or using an interrupt.

When powered on, a PC executes code that is physically stored in non-volatile memory on the motherboard. The Basic Input Output System, or BIOS code, loads the PC operating system from ATA storage devices connected to the ATA controller and provides low-level I/O system drivers for such storage devices.

The present invention emulates the ATA controller shown in Figure 1 and described above, and is fully compatible with it at the programming level. Referring now to FIG. 2, the upper part of FIG. 2 is a block diagram of a controller according to the present invention, which can be configured as a RAID controller, for example. The left side of the controller block 50 connects to the PCI bus in place of a standard dual-channel ATA controller and emulates one to four connected ATA storage devices. The emulation of the ATA storage device, described in detail below, separates the controller's host interface from the physical device interface, allowing considerable freedom in the type and number of device interfaces to be provided. For example, an application of the present invention may implement X SCSI ports and/or Y ATA ports, where X and Y are by no means limited to the four logical drives present in the host system. FIG. 2 is an example of implementing N+1 ATA ports numbered from 0 to N−1.

The lower part of Figure 2 illustrates the programming interface of the present invention. The host interface 56 implements all the register blocks seen from the point of view of the standard ATA controller's PCI bus: the dual channel bus master controller blocks 58, 60 and four sets of command and control register blocks numbered 62, 64, 66 and 68 respectively. The host interface block 56 emulates the registers of the ATA controller and ATA storage device, down to the layers required to support the ATA specification protocol.

Block 70 in the lower portion of FIG. 2 illustrates the main components of controller block 50 . In addition to the host interface block 56, the controller 70 includes a RAM buffer cache 72, a DMA channel 74, and a processor 80, as further described below. Controller block 70 also includes a number of ATA port interfaces, such as interfaces 82 , 84 and 86 . Each ATA port interface provides a standard interface to IDE type storage devices such as disk drives. As previously mentioned, each memory device includes a block of command and control registers on the motherboard. For example, they are illustrated as a command register block 90 and a controller block 92 , both associated with a single device, ie a host drive, connected to the ATA port interface 82 , standard connector cable 96 . The controller block 70 can be configured to include any desired number of ATA ports while still providing a standard dual channel controller interface 56 to the host PCI bus 12 .

Figure 3 shows a detailed block diagram of the presently preferred embodiment of the invention. The system is implemented as an Application Specific Integrated Circuit (ASIC) in a 0.18 micron CMOS process. The device is logically divided into four modules, each module having an associated port to the outside of the device.

The host interface 100 is based on the PCI core 104 fabricated in indium silicon. CS6464AF is a soft core (Verilog source synthesized for specific applications), which supports 32-bit and 64-bit PCI buses, and the PCI bus clock rate is 33MHZ or 66MHZ. The core supports master and destination operations. Target feature 106 provides access to the previously described ATA compatible register file. The master capability 108 is used to emulate the bus master DMA feature of the ATA controller. The PCI core includes a configuration space that emulates the configuration space 110 of a dual-port ATA controller.

The DRAM interface block 120 supports externally connected SDRAM 122. The 64-bit wide, 100MHZ single data rate port 124 supports a maximum transfer rate of 800MBPS. Locally, the DRAM interface may be shared and accessed by the local processor in processor block 150 by transferring to or from the PCI bus via host interface 100 and to or from the disk drive via drive interface 130 .

Drive interface block 130 provides five ATA ports, such as 134, each capable of supporting master and slave drives. Each port supports programmable input and output (PIO) up to 16MBPS transfer rate and Ultra DMA up to 100MBPS transfer rate.

The processor block is built around the EZ4102 TinyRISC core 160 by LSI Logic. This processor is a variant of the MIPS processor. On power up, the processor loads code from external flash memory 162 accessed through expansion bus port 166 . This code is transferred to the SRAM block 170 in the processor block. The processor 160 configures each of the other modules and through these modules it can access the PCI bus, SDRAM or ATA drives. In general, system transfer rates are enhanced by not requiring a processor to process data. The processor coordinates data transfers between the driver and DSRAM by configuring the DMA engines 136, 146 in these blocks to load and unload the FIFO 148 in between. Likewise, it coordinates transfers between SDRAM and PCI bus targets by configuring the DMA engines 172, 102 in the DRAM interface and the host interface to load and unload the FIFO 174 between these blocks.

Figure 4 illustrates the ATA register file implementation details. The registers are all dual ported and can be accessed by the host system or by the local processor 160 from the PCI bus. From the perspective of the PCI bus, each ATA channel has two register blocks associated with it. Command block 208 is an eight byte range of byte wide registers. Control block 210 is a four-byte range where only a single location of storage is used. As mentioned earlier, a single ATA port can be used to access a pair of drives connected to a common cable. Each device has its own block of command and control registers. The devices are physically configured with jumpers so that one is designated as master and the other as slave. A specific device is selected for access by writing a byte of data into the device header register of the command block with an address offset of six. If bit four is asserted, the slave is selected and the master is deselected for subsequent operations. A write to the same register with bit four cleared selects the master and deselects the slave. To simulate this behavior in the present invention, master and slave register sets are implemented. Additionally, a single bit slave register 230 is provided which records the bit four most recently written to the device header register. The slave registers control read multiplexing and write address decoding from the PCI bus so that the appropriate pair of register blocks will be accessed based on the most recent device selection.

On power-up or after reset, the ATA device is initially busy. The busy condition can be detected by reading the status register at address offset seven in the command block, or by reading the alternate status register block in the control block. While the device is busy, no other registers can be accessed. To simulate this behavior in the present invention, a single bit busy register 232 is provided. This register is set by a reset from the PCI bus, by a write to the soft reset bit in the device control register of the control block, or when the address offset seven of the command register block is written to the command register. The local processor can clear the busy register.

Each ATA device is capable of asserting an interrupt request to the host system if interrupts have been enabled in the device. To emulate this behavior, single bit interrupt request 234 and interrupt enable 236 registers are provided for master and slave devices. Interrupt enable is controlled by the device control register of each device. Each device can assert an interrupt request to the host system in order to transfer data or return a completion status. In the present invention, the interrupt request can be set or cleared by the local processor. Interrupt requests are also cleared by reading the device's status register (but not the alternate status register), as described in the protocol of the ATA specification. The interrupt request and interrupt enable states of master and slave devices can be maintained independently, allowing proper behavior when the master changes device selection.

For secondary channels, the command and control register files of the master and slave devices and the slave, busy, interrupt "edge effects" are duplicated. The command and control register file blocks for all four devices are all linearly mapped into the address space of the local processor.

The shared dual channel bus master controller block 250 can be accessed from the PCI bus or by a local processor.

According to the ATA protocol, selecting the device, all parameters required for a given command are loaded into the command register file, and then the command itself is also loaded into said registers at offset seven. As above, this will set the channel to busy. A busy rising edge causes an interrupt to the local processor, which will respond by interpreting the command and its parameters. Most commands will be remapped as accesses to arrays of attached physical devices. These accesses can be used to implement any common RAID protocol, including but not limited to RAID0, 1, 3 and 5. The local handler has the option to read more data than requested. Additional data is pre-stored in SDRAM for subsequent reading. The local processor can use program-controlled IO or DMA to arrange data transfer between SDRAM and host system as required by the command.

In summary, the present invention includes a RAID storage device controller that provides a host interface for connecting the controller to a host system bus. The host interface is isolated from attached storage devices such as IDE disk drives, so that the number of drives actually connected is not limited by the interface protocol. Various device ports can be implemented, and various RAID strategies can be used, such as RAID3 and RAID5. In each case, the host interface provides a standard unified interface to the host, namely an ATA interface, preferably a dual-channel ATA interface. The host interface emulates an ATA single or dual channel interface and emulates one or two IDE devices per channel, regardless of the actual number of devices physically connected to the controller. This makes it possible, for example, to deploy five or seven IDE drives in RAID5 without changing the standard BIOS in the PCI host. This way, the RAID controller is transparent to standard dual-channel ATA controller boards.

It will be apparent to those skilled in the art that many changes may be made to the details of the above-described embodiments of the invention without departing from the basic principles of the invention. Accordingly, the scope of the invention should be defined by the appended claims.

Claims (20)

1. A storage device controller comprising: a host interface for connecting the controller to a host system bus, the host interface emulating a standard IDE channel and also emulating an IDE device as if connected to the IDE channel; and At least one physical interface is used to connect the storage device controller with a physical storage device. 2. The storage device controller of claim 1, wherein at least one of the physical interfaces implements an ATA port for connecting an ATA compatible storage device to the controller. 3. The storage device controller of claim 1, wherein the host interface emulates at least one of a primary channel and a secondary channel. 4. The storage device controller of claim 3, wherein said host interface emulates a single IDE device connected to each of said primary and secondary channels. 5. The storage device controller of claim 3, wherein the host interface emulates a primary IDE storage device and a secondary IDE storage device connected to the primary and secondary IDE storage devices. One of the channels to be channeled. 6. The storage device controller of claim 3, further comprising means for simulating a bus master DMA controller of a standard dual port IDE controller. 7. The storage device controller of claim 1, wherein the host interface emulates a single IDE device connected to the IDE channel. 8. The storage device controller of claim 1, wherein the host interface emulates a master IDE storage device and a slave IDE storage device connected to the IDE channel. 9. The storage device controller of claim 1, further comprising means for simulating a bus master DMA controller of a standard dual port IDE controller. 10. A RAID storage device controller comprising: a host interface for connecting the controller to a host system bus, the host interface simulating at least one ATA controller channel; said host interface also emulates at least one IDE device as though connected to said emulated ATA controller channel by implementing an IDE compliant command and control register block; at least two physical interfaces for connecting the storage device controller to a plurality of storage devices; and The local processor in the controller is used to control the access operation of the physical storage device. 11. The RAID storage device controller of claim 10, further comprising means for simulating a bus master DMA controller of a standard dual port IDE controller. 12. The RAID storage device controller as claimed in claim 10, further comprising: a buffer memory for buffering data transmission between the host system bus and the connected storage device; and a DMA engine, which arranged for transferring data between said host interface and said buffer memory. 13. The RAID storage device controller of claim 12, comprising a DMA engine arranged to transfer data between the buffer memory and the port interface. 14. The RAID storage device controller of claim 10, wherein the host interface emulates a primary ATA channel and a secondary ATA channel. 15. The RAID storage device controller of claim 14, wherein said host interface emulates a single IDE device connected to each of said primary and secondary channels. 16. The RAID storage device controller as claimed in claim 14, wherein the host interface emulates a master IDE storage device and a slave IDE storage device, the master IDE storage device and the slave IDE storage device being connected to the primary and at least one of the secondary channels. 17. The RAID storage device controller of claim 10, wherein the host interface emulates a master IDE device and a slave IDE device connected to the IDE channel. 18. The RAID storage device controller of claim 10, wherein the host interface emulates a single IDE device connected to the IDE channel. 19. The RAID storage device controller of claim 10, wherein the host interface emulates a master IDE storage device and a slave IDE storage device connected to the IDE channel. 20. A method for connecting a RAID storage device controller with a PCI bus host without modifying the existing host BIOS software, said method comprising the following steps: In the controller, simulating an ATA controller connected to the host; In said controller, also simulating an IDE storage device as if connected to said ATA controller; providing at least two physical port interfaces for connecting physical storage devices to the controller; and decoupling the host interface of the controller from the physical storage device so that the storage device controller appears to the host as an IDE device connected via the ATA interface regardless of the actual connection to the controller The actual number and interface type of the physical storage device interfaced by the physical port.

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